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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "drm_dp_helper.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define PINEVIEW_VCO_MIN                1700000
 106 #define PINEVIEW_VCO_MAX                3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* Pineview's Ncounter is a ring counter */
 110 #define PINEVIEW_N_MIN                3
 111 #define PINEVIEW_N_MAX                6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define PINEVIEW_M_MIN                2
 115 #define PINEVIEW_M_MAX              256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* Pineview M1 is reserved, and must be 0 */
 121 #define PINEVIEW_M1_MIN               0
 122 #define PINEVIEW_M1_MAX               0
 123 #define PINEVIEW_M2_MIN               0
 124 #define PINEVIEW_M2_MAX               254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define PINEVIEW_P_LVDS_MIN                   7
 130 #define PINEVIEW_P_LVDS_MAX                  112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* Ironlake */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IRONLAKE_DOT_MIN         25000
 242 #define IRONLAKE_DOT_MAX         350000
 243 #define IRONLAKE_VCO_MIN         1760000
 244 #define IRONLAKE_VCO_MAX         3510000
 245 #define IRONLAKE_N_MIN           1
 246 #define IRONLAKE_N_MAX           5
 247 #define IRONLAKE_M_MIN           79
 248 #define IRONLAKE_M_MAX           118
 249 #define IRONLAKE_M1_MIN          12
 250 #define IRONLAKE_M1_MAX          23
 251 #define IRONLAKE_M2_MIN          5
 252 #define IRONLAKE_M2_MAX          9
 253 #define IRONLAKE_P_SDVO_DAC_MIN  5
 254 #define IRONLAKE_P_SDVO_DAC_MAX  80
 255 #define IRONLAKE_P_LVDS_MIN      28
 256 #define IRONLAKE_P_LVDS_MAX      112
 257 #define IRONLAKE_P1_MIN          1
 258 #define IRONLAKE_P1_MAX          8
 259 #define IRONLAKE_P2_SDVO_DAC_SLOW 10
 260 #define IRONLAKE_P2_SDVO_DAC_FAST 5
 261 #define IRONLAKE_P2_LVDS_SLOW    14 /* single channel */
 262 #define IRONLAKE_P2_LVDS_FAST    7  /* double channel */
 263 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                              int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                            int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_pineview_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 459         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 460         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 461         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 462         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_pineview_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 474         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 475         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 476         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 477         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 478         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* Pineview only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_ironlake_sdvo = {
 488         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 489         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 490         .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
 491         .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
 492         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 493         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 494         .p   = { .min = IRONLAKE_P_SDVO_DAC_MIN,   .max = IRONLAKE_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IRONLAKE_P1_MIN,           .max = IRONLAKE_P1_MAX },
 496         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 497                  .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_ironlake_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_ironlake_lvds = {
 503         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 504         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 505         .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
 506         .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
 507         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 508         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 509         .p   = { .min = IRONLAKE_P_LVDS_MIN,       .max = IRONLAKE_P_LVDS_MAX },
 510         .p1  = { .min = IRONLAKE_P1_MIN,           .max = IRONLAKE_P1_MAX },
 511         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 512                  .p2_slow = IRONLAKE_P2_LVDS_SLOW,
 513                  .p2_fast = IRONLAKE_P2_LVDS_FAST },
 514         .find_pll = intel_ironlake_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_ironlake_lvds;
 522         else
 523                 limit = &intel_limits_ironlake_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IRONLAKE(dev))
 561                 limit = intel_ironlake_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_PINEVIEW(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_pineview_lvds;
 572                 else
 573                         limit = &intel_limits_pineview_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 584 static void pineview_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_PINEVIEW(dev)) {
 595                 pineview_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 710              clock.m1++) {
 711                 for (clock.m2 = limit->m2.min;
 712                      clock.m2 <= limit->m2.max; clock.m2++) {
 713                         /* m1 is always 0 in Pineview */
 714                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 715                                 break;
 716                         for (clock.n = limit->n.min;
 717                              clock.n <= limit->n.max; clock.n++) {
 718                                 for (clock.p1 = limit->p1.min;
 719                                         clock.p1 <= limit->p1.max; clock.p1++) {
 720                                         int this_err;
 721
 722                                         intel_clock(dev, refclk, &clock);
 723
 724                                         if (!intel_PLL_is_valid(crtc, &clock))
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740
 741 static bool
 742 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 743                             int target, int refclk, intel_clock_t *best_clock)
 744
 745 {
 746         struct drm_device *dev = crtc->dev;
 747         intel_clock_t clock;
 748         int err = target;
 749         bool found = false;
 750
 751         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 752
 753         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 754                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 755                         /* m1 is always 0 in Pineview */
 756                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 757                                 break;
 758                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 759                              clock.n++) {
 760                                 int this_err;
 761
 762                                 intel_clock(dev, refclk, &clock);
 763
 764                                 if (!intel_PLL_is_valid(crtc, &clock))
 765                                         continue;
 766
 767                                 this_err = abs(clock.dot - target);
 768                                 if (this_err < err) {
 769                                         *best_clock = clock;
 770                                         err = this_err;
 771                                         found = true;
 772                                 }
 773                         }
 774                 }
 775         }
 776
 777         return found;
 778 }
 779
 780 static bool
 781 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 782                         int target, int refclk, intel_clock_t *best_clock)
 783 {
 784         struct drm_device *dev = crtc->dev;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         intel_clock_t clock;
 787         int max_n;
 788         bool found;
 789         /* approximately equals target * 0.00488 */
 790         int err_most = (target >> 8) + (target >> 10);
 791         found = false;
 792
 793         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 794                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 795                     LVDS_CLKB_POWER_UP)
 796                         clock.p2 = limit->p2.p2_fast;
 797                 else
 798                         clock.p2 = limit->p2.p2_slow;
 799         } else {
 800                 if (target < limit->p2.dot_limit)
 801                         clock.p2 = limit->p2.p2_slow;
 802                 else
 803                         clock.p2 = limit->p2.p2_fast;
 804         }
 805
 806         memset(best_clock, 0, sizeof(*best_clock));
 807         max_n = limit->n.max;
 808         /* based on hardware requriment prefer smaller n to precision */
 809         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 810                 /* based on hardware requirment prefere larger m1,m2 */
 811                 for (clock.m1 = limit->m1.max;
 812                      clock.m1 >= limit->m1.min; clock.m1--) {
 813                         for (clock.m2 = limit->m2.max;
 814                              clock.m2 >= limit->m2.min; clock.m2--) {
 815                                 for (clock.p1 = limit->p1.max;
 816                                      clock.p1 >= limit->p1.min; clock.p1--) {
 817                                         int this_err;
 818
 819                                         intel_clock(dev, refclk, &clock);
 820                                         if (!intel_PLL_is_valid(crtc, &clock))
 821                                                 continue;
 822                                         this_err = abs(clock.dot - target) ;
 823                                         if (this_err < err_most) {
 824                                                 *best_clock = clock;
 825                                                 err_most = this_err;
 826                                                 max_n = clock.n;
 827                                                 found = true;
 828                                         }
 829                                 }
 830                         }
 831                 }
 832         }
 833         return found;
 834 }
 835
 836 static bool
 837 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 838                            int target, int refclk, intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->dev;
 841         intel_clock_t clock;
 842         if (target < 200000) {
 843                 clock.n = 1;
 844                 clock.p1 = 2;
 845                 clock.p2 = 10;
 846                 clock.m1 = 12;
 847                 clock.m2 = 9;
 848         } else {
 849                 clock.n = 2;
 850                 clock.p1 = 1;
 851                 clock.p2 = 10;
 852                 clock.m1 = 14;
 853                 clock.m2 = 8;
 854         }
 855         intel_clock(dev, refclk, &clock);
 856         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 857         return true;
 858 }
 859
 860 static bool
 861 intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 862                              int target, int refclk, intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc->dev;
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         intel_clock_t clock;
 867         int err_most = 47;
 868         int err_min = 10000;
 869
 870         /* eDP has only 2 clock choice, no n/m/p setting */
 871         if (HAS_eDP)
 872                 return true;
 873
 874         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 875                 return intel_find_pll_ironlake_dp(limit, crtc, target,
 876                                                refclk, best_clock);
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 880                     LVDS_CLKB_POWER_UP)
 881                         clock.p2 = limit->p2.p2_fast;
 882                 else
 883                         clock.p2 = limit->p2.p2_slow;
 884         } else {
 885                 if (target < limit->p2.dot_limit)
 886                         clock.p2 = limit->p2.p2_slow;
 887                 else
 888                         clock.p2 = limit->p2.p2_fast;
 889         }
 890
 891         memset(best_clock, 0, sizeof(*best_clock));
 892         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 893                 /* based on hardware requriment prefer smaller n to precision */
 894                 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
 895                         /* based on hardware requirment prefere larger m1,m2 */
 896                         for (clock.m1 = limit->m1.max;
 897                              clock.m1 >= limit->m1.min; clock.m1--) {
 898                                 for (clock.m2 = limit->m2.max;
 899                                      clock.m2 >= limit->m2.min; clock.m2--) {
 900                                         int this_err;
 901
 902                                         intel_clock(dev, refclk, &clock);
 903                                         if (!intel_PLL_is_valid(crtc, &clock))
 904                                                 continue;
 905                                         this_err = abs((10000 - (target*10000/clock.dot)));
 906                                         if (this_err < err_most) {
 907                                                 *best_clock = clock;
 908                                                 /* found on first matching */
 909                                                 goto out;
 910                                         } else if (this_err < err_min) {
 911                                                 *best_clock = clock;
 912                                                 err_min = this_err;
 913                                         }
 914                                 }
 915                         }
 916                 }
 917         }
 918 out:
 919         return true;
 920 }
 921
 922 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 923 static bool
 924 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 925                       int target, int refclk, intel_clock_t *best_clock)
 926 {
 927     intel_clock_t clock;
 928     if (target < 200000) {
 929         clock.p1 = 2;
 930         clock.p2 = 10;
 931         clock.n = 2;
 932         clock.m1 = 23;
 933         clock.m2 = 8;
 934     } else {
 935         clock.p1 = 1;
 936         clock.p2 = 10;
 937         clock.n = 1;
 938         clock.m1 = 14;
 939         clock.m2 = 2;
 940     }
 941     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 942     clock.p = (clock.p1 * clock.p2);
 943     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 944     clock.vco = 0;
 945     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 946     return true;
 947 }
 948
 949 void
 950 intel_wait_for_vblank(struct drm_device *dev)
 951 {
 952         /* Wait for 20ms, i.e. one cycle at 50hz. */
 953         msleep(20);
 954 }
 955
 956 /* Parameters have changed, update FBC info */
 957 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 958 {
 959         struct drm_device *dev = crtc->dev;
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         struct drm_framebuffer *fb = crtc->fb;
 962         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 963         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 965         int plane, i;
 966         u32 fbc_ctl, fbc_ctl2;
 967
 968         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 969
 970         if (fb->pitch < dev_priv->cfb_pitch)
 971                 dev_priv->cfb_pitch = fb->pitch;
 972
 973         /* FBC_CTL wants 64B units */
 974         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 975         dev_priv->cfb_fence = obj_priv->fence_reg;
 976         dev_priv->cfb_plane = intel_crtc->plane;
 977         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 978
 979         /* Clear old tags */
 980         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 981                 I915_WRITE(FBC_TAG + (i * 4), 0);
 982
 983         /* Set it up... */
 984         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 985         if (obj_priv->tiling_mode != I915_TILING_NONE)
 986                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 987         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 988         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 989
 990         /* enable it... */
 991         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 992         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 993         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 994         if (obj_priv->tiling_mode != I915_TILING_NONE)
 995                 fbc_ctl |= dev_priv->cfb_fence;
 996         I915_WRITE(FBC_CONTROL, fbc_ctl);
 997
 998         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
 999                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1000 }
1001
1002 void i8xx_disable_fbc(struct drm_device *dev)
1003 {
1004         struct drm_i915_private *dev_priv = dev->dev_private;
1005         u32 fbc_ctl;
1006
1007         if (!I915_HAS_FBC(dev))
1008                 return;
1009
1010         /* Disable compression */
1011         fbc_ctl = I915_READ(FBC_CONTROL);
1012         fbc_ctl &= ~FBC_CTL_EN;
1013         I915_WRITE(FBC_CONTROL, fbc_ctl);
1014
1015         /* Wait for compressing bit to clear */
1016         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1017                 ; /* nothing */
1018
1019         intel_wait_for_vblank(dev);
1020
1021         DRM_DEBUG_KMS("disabled FBC\n");
1022 }
1023
1024 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1025 {
1026         struct drm_device *dev = crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028
1029         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1030 }
1031
1032 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1033 {
1034         struct drm_device *dev = crtc->dev;
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         struct drm_framebuffer *fb = crtc->fb;
1037         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1038         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1040         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1041                      DPFC_CTL_PLANEB);
1042         unsigned long stall_watermark = 200;
1043         u32 dpfc_ctl;
1044
1045         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1046         dev_priv->cfb_fence = obj_priv->fence_reg;
1047         dev_priv->cfb_plane = intel_crtc->plane;
1048
1049         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1050         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1051                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1052                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1053         } else {
1054                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1055         }
1056
1057         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1058         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1059                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1060                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1061         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1062
1063         /* enable it... */
1064         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1065
1066         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1067 }
1068
1069 void g4x_disable_fbc(struct drm_device *dev)
1070 {
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         u32 dpfc_ctl;
1073
1074         /* Disable compression */
1075         dpfc_ctl = I915_READ(DPFC_CONTROL);
1076         dpfc_ctl &= ~DPFC_CTL_EN;
1077         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1078         intel_wait_for_vblank(dev);
1079
1080         DRM_DEBUG_KMS("disabled FBC\n");
1081 }
1082
1083 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1084 {
1085         struct drm_device *dev = crtc->dev;
1086         struct drm_i915_private *dev_priv = dev->dev_private;
1087
1088         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1089 }
1090
1091 /**
1092  * intel_update_fbc - enable/disable FBC as needed
1093  * @crtc: CRTC to point the compressor at
1094  * @mode: mode in use
1095  *
1096  * Set up the framebuffer compression hardware at mode set time.  We
1097  * enable it if possible:
1098  *   - plane A only (on pre-965)
1099  *   - no pixel mulitply/line duplication
1100  *   - no alpha buffer discard
1101  *   - no dual wide
1102  *   - framebuffer <= 2048 in width, 1536 in height
1103  *
1104  * We can't assume that any compression will take place (worst case),
1105  * so the compressed buffer has to be the same size as the uncompressed
1106  * one.  It also must reside (along with the line length buffer) in
1107  * stolen memory.
1108  *
1109  * We need to enable/disable FBC on a global basis.
1110  */
1111 static void intel_update_fbc(struct drm_crtc *crtc,
1112                              struct drm_display_mode *mode)
1113 {
1114         struct drm_device *dev = crtc->dev;
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         struct drm_framebuffer *fb = crtc->fb;
1117         struct intel_framebuffer *intel_fb;
1118         struct drm_i915_gem_object *obj_priv;
1119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1120         int plane = intel_crtc->plane;
1121
1122         if (!i915_powersave)
1123                 return;
1124
1125         if (!dev_priv->display.fbc_enabled ||
1126             !dev_priv->display.enable_fbc ||
1127             !dev_priv->display.disable_fbc)
1128                 return;
1129
1130         if (!crtc->fb)
1131                 return;
1132
1133         intel_fb = to_intel_framebuffer(fb);
1134         obj_priv = intel_fb->obj->driver_private;
1135
1136         /*
1137          * If FBC is already on, we just have to verify that we can
1138          * keep it that way...
1139          * Need to disable if:
1140          *   - changing FBC params (stride, fence, mode)
1141          *   - new fb is too large to fit in compressed buffer
1142          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1143          */
1144         if (intel_fb->obj->size > dev_priv->cfb_size) {
1145                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1146                                 "compression\n");
1147                 goto out_disable;
1148         }
1149         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1150             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1151                 DRM_DEBUG_KMS("mode incompatible with compression, "
1152                                 "disabling\n");
1153                 goto out_disable;
1154         }
1155         if ((mode->hdisplay > 2048) ||
1156             (mode->vdisplay > 1536)) {
1157                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1158                 goto out_disable;
1159         }
1160         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1161                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1162                 goto out_disable;
1163         }
1164         if (obj_priv->tiling_mode != I915_TILING_X) {
1165                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1166                 goto out_disable;
1167         }
1168
1169         if (dev_priv->display.fbc_enabled(crtc)) {
1170                 /* We can re-enable it in this case, but need to update pitch */
1171                 if (fb->pitch > dev_priv->cfb_pitch)
1172                         dev_priv->display.disable_fbc(dev);
1173                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1174                         dev_priv->display.disable_fbc(dev);
1175                 if (plane != dev_priv->cfb_plane)
1176                         dev_priv->display.disable_fbc(dev);
1177         }
1178
1179         if (!dev_priv->display.fbc_enabled(crtc)) {
1180                 /* Now try to turn it back on if possible */
1181                 dev_priv->display.enable_fbc(crtc, 500);
1182         }
1183
1184         return;
1185
1186 out_disable:
1187         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1188         /* Multiple disables should be harmless */
1189         if (dev_priv->display.fbc_enabled(crtc))
1190                 dev_priv->display.disable_fbc(dev);
1191 }
1192
1193 static int
1194 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1195 {
1196         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1197         u32 alignment;
1198         int ret;
1199
1200         switch (obj_priv->tiling_mode) {
1201         case I915_TILING_NONE:
1202                 alignment = 64 * 1024;
1203                 break;
1204         case I915_TILING_X:
1205                 /* pin() will align the object as required by fence */
1206                 alignment = 0;
1207                 break;
1208         case I915_TILING_Y:
1209                 /* FIXME: Is this true? */
1210                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1211                 return -EINVAL;
1212         default:
1213                 BUG();
1214         }
1215
1216         ret = i915_gem_object_pin(obj, alignment);
1217         if (ret != 0)
1218                 return ret;
1219
1220         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1221          * fence, whereas 965+ only requires a fence if using
1222          * framebuffer compression.  For simplicity, we always install
1223          * a fence as the cost is not that onerous.
1224          */
1225         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1226             obj_priv->tiling_mode != I915_TILING_NONE) {
1227                 ret = i915_gem_object_get_fence_reg(obj);
1228                 if (ret != 0) {
1229                         i915_gem_object_unpin(obj);
1230                         return ret;
1231                 }
1232         }
1233
1234         return 0;
1235 }
1236
1237 static int
1238 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1239                     struct drm_framebuffer *old_fb)
1240 {
1241         struct drm_device *dev = crtc->dev;
1242         struct drm_i915_private *dev_priv = dev->dev_private;
1243         struct drm_i915_master_private *master_priv;
1244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1245         struct intel_framebuffer *intel_fb;
1246         struct drm_i915_gem_object *obj_priv;
1247         struct drm_gem_object *obj;
1248         int pipe = intel_crtc->pipe;
1249         int plane = intel_crtc->plane;
1250         unsigned long Start, Offset;
1251         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1252         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1253         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1254         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1255         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1256         u32 dspcntr;
1257         int ret;
1258
1259         /* no fb bound */
1260         if (!crtc->fb) {
1261                 DRM_DEBUG_KMS("No FB bound\n");
1262                 return 0;
1263         }
1264
1265         switch (plane) {
1266         case 0:
1267         case 1:
1268                 break;
1269         default:
1270                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1271                 return -EINVAL;
1272         }
1273
1274         intel_fb = to_intel_framebuffer(crtc->fb);
1275         obj = intel_fb->obj;
1276         obj_priv = obj->driver_private;
1277
1278         mutex_lock(&dev->struct_mutex);
1279         ret = intel_pin_and_fence_fb_obj(dev, obj);
1280         if (ret != 0) {
1281                 mutex_unlock(&dev->struct_mutex);
1282                 return ret;
1283         }
1284
1285         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1286         if (ret != 0) {
1287                 i915_gem_object_unpin(obj);
1288                 mutex_unlock(&dev->struct_mutex);
1289                 return ret;
1290         }
1291
1292         dspcntr = I915_READ(dspcntr_reg);
1293         /* Mask out pixel format bits in case we change it */
1294         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1295         switch (crtc->fb->bits_per_pixel) {
1296         case 8:
1297                 dspcntr |= DISPPLANE_8BPP;
1298                 break;
1299         case 16:
1300                 if (crtc->fb->depth == 15)
1301                         dspcntr |= DISPPLANE_15_16BPP;
1302                 else
1303                         dspcntr |= DISPPLANE_16BPP;
1304                 break;
1305         case 24:
1306         case 32:
1307                 if (crtc->fb->depth == 30)
1308                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1309                 else
1310                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1311                 break;
1312         default:
1313                 DRM_ERROR("Unknown color depth\n");
1314                 i915_gem_object_unpin(obj);
1315                 mutex_unlock(&dev->struct_mutex);
1316                 return -EINVAL;
1317         }
1318         if (IS_I965G(dev)) {
1319                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1320                         dspcntr |= DISPPLANE_TILED;
1321                 else
1322                         dspcntr &= ~DISPPLANE_TILED;
1323         }
1324
1325         if (IS_IRONLAKE(dev))
1326                 /* must disable */
1327                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1328
1329         I915_WRITE(dspcntr_reg, dspcntr);
1330
1331         Start = obj_priv->gtt_offset;
1332         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1333
1334         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1335         I915_WRITE(dspstride, crtc->fb->pitch);
1336         if (IS_I965G(dev)) {
1337                 I915_WRITE(dspbase, Offset);
1338                 I915_READ(dspbase);
1339                 I915_WRITE(dspsurf, Start);
1340                 I915_READ(dspsurf);
1341                 I915_WRITE(dsptileoff, (y << 16) | x);
1342         } else {
1343                 I915_WRITE(dspbase, Start + Offset);
1344                 I915_READ(dspbase);
1345         }
1346
1347         if ((IS_I965G(dev) || plane == 0))
1348                 intel_update_fbc(crtc, &crtc->mode);
1349
1350         intel_wait_for_vblank(dev);
1351
1352         if (old_fb) {
1353                 intel_fb = to_intel_framebuffer(old_fb);
1354                 obj_priv = intel_fb->obj->driver_private;
1355                 i915_gem_object_unpin(intel_fb->obj);
1356         }
1357         intel_increase_pllclock(crtc, true);
1358
1359         mutex_unlock(&dev->struct_mutex);
1360
1361         if (!dev->primary->master)
1362                 return 0;
1363
1364         master_priv = dev->primary->master->driver_priv;
1365         if (!master_priv->sarea_priv)
1366                 return 0;
1367
1368         if (pipe) {
1369                 master_priv->sarea_priv->pipeB_x = x;
1370                 master_priv->sarea_priv->pipeB_y = y;
1371         } else {
1372                 master_priv->sarea_priv->pipeA_x = x;
1373                 master_priv->sarea_priv->pipeA_y = y;
1374         }
1375
1376         return 0;
1377 }
1378
1379 /* Disable the VGA plane that we never use */
1380 static void i915_disable_vga (struct drm_device *dev)
1381 {
1382         struct drm_i915_private *dev_priv = dev->dev_private;
1383         u8 sr1;
1384         u32 vga_reg;
1385
1386         if (IS_IRONLAKE(dev))
1387                 vga_reg = CPU_VGACNTRL;
1388         else
1389                 vga_reg = VGACNTRL;
1390
1391         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1392                 return;
1393
1394         I915_WRITE8(VGA_SR_INDEX, 1);
1395         sr1 = I915_READ8(VGA_SR_DATA);
1396         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1397         udelay(100);
1398
1399         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1400 }
1401
1402 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1403 {
1404         struct drm_device *dev = crtc->dev;
1405         struct drm_i915_private *dev_priv = dev->dev_private;
1406         u32 dpa_ctl;
1407
1408         DRM_DEBUG_KMS("\n");
1409         dpa_ctl = I915_READ(DP_A);
1410         dpa_ctl &= ~DP_PLL_ENABLE;
1411         I915_WRITE(DP_A, dpa_ctl);
1412 }
1413
1414 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1415 {
1416         struct drm_device *dev = crtc->dev;
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418         u32 dpa_ctl;
1419
1420         dpa_ctl = I915_READ(DP_A);
1421         dpa_ctl |= DP_PLL_ENABLE;
1422         I915_WRITE(DP_A, dpa_ctl);
1423         udelay(200);
1424 }
1425
1426
1427 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1428 {
1429         struct drm_device *dev = crtc->dev;
1430         struct drm_i915_private *dev_priv = dev->dev_private;
1431         u32 dpa_ctl;
1432
1433         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1434         dpa_ctl = I915_READ(DP_A);
1435         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1436
1437         if (clock < 200000) {
1438                 u32 temp;
1439                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1440                 /* workaround for 160Mhz:
1441                    1) program 0x4600c bits 15:0 = 0x8124
1442                    2) program 0x46010 bit 0 = 1
1443                    3) program 0x46034 bit 24 = 1
1444                    4) program 0x64000 bit 14 = 1
1445                    */
1446                 temp = I915_READ(0x4600c);
1447                 temp &= 0xffff0000;
1448                 I915_WRITE(0x4600c, temp | 0x8124);
1449
1450                 temp = I915_READ(0x46010);
1451                 I915_WRITE(0x46010, temp | 1);
1452
1453                 temp = I915_READ(0x46034);
1454                 I915_WRITE(0x46034, temp | (1 << 24));
1455         } else {
1456                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1457         }
1458         I915_WRITE(DP_A, dpa_ctl);
1459
1460         udelay(500);
1461 }
1462
1463 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1464 {
1465         struct drm_device *dev = crtc->dev;
1466         struct drm_i915_private *dev_priv = dev->dev_private;
1467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1468         int pipe = intel_crtc->pipe;
1469         int plane = intel_crtc->plane;
1470         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1471         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1472         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1473         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1474         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1475         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1476         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1477         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1478         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1479         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1480         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1481         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1482         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1483         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1484         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1485         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1486         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1487         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1488         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1489         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1490         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1491         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1492         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1493         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1494         u32 temp;
1495         int tries = 5, j, n;
1496
1497         /* XXX: When our outputs are all unaware of DPMS modes other than off
1498          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1499          */
1500         switch (mode) {
1501         case DRM_MODE_DPMS_ON:
1502         case DRM_MODE_DPMS_STANDBY:
1503         case DRM_MODE_DPMS_SUSPEND:
1504                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1505
1506                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1507                         temp = I915_READ(PCH_LVDS);
1508                         if ((temp & LVDS_PORT_EN) == 0) {
1509                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1510                                 POSTING_READ(PCH_LVDS);
1511                         }
1512                 }
1513
1514                 if (HAS_eDP) {
1515                         /* enable eDP PLL */
1516                         ironlake_enable_pll_edp(crtc);
1517                 } else {
1518                         /* enable PCH DPLL */
1519                         temp = I915_READ(pch_dpll_reg);
1520                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1521                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1522                                 I915_READ(pch_dpll_reg);
1523                         }
1524
1525                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1526                         temp = I915_READ(fdi_rx_reg);
1527                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1528                                         FDI_SEL_PCDCLK |
1529                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1530                         I915_READ(fdi_rx_reg);
1531                         udelay(200);
1532
1533                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1534                         temp = I915_READ(fdi_tx_reg);
1535                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1536                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1537                                 I915_READ(fdi_tx_reg);
1538                                 udelay(100);
1539                         }
1540                 }
1541
1542                 /* Enable panel fitting for LVDS */
1543                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1544                         temp = I915_READ(pf_ctl_reg);
1545                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1546
1547                         /* currently full aspect */
1548                         I915_WRITE(pf_win_pos, 0);
1549
1550                         I915_WRITE(pf_win_size,
1551                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1552                                    (dev_priv->panel_fixed_mode->vdisplay));
1553                 }
1554
1555                 /* Enable CPU pipe */
1556                 temp = I915_READ(pipeconf_reg);
1557                 if ((temp & PIPEACONF_ENABLE) == 0) {
1558                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1559                         I915_READ(pipeconf_reg);
1560                         udelay(100);
1561                 }
1562
1563                 /* configure and enable CPU plane */
1564                 temp = I915_READ(dspcntr_reg);
1565                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1566                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1567                         /* Flush the plane changes */
1568                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1569                 }
1570
1571                 if (!HAS_eDP) {
1572                         /* enable CPU FDI TX and PCH FDI RX */
1573                         temp = I915_READ(fdi_tx_reg);
1574                         temp |= FDI_TX_ENABLE;
1575                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1576                         temp &= ~FDI_LINK_TRAIN_NONE;
1577                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1578                         I915_WRITE(fdi_tx_reg, temp);
1579                         I915_READ(fdi_tx_reg);
1580
1581                         temp = I915_READ(fdi_rx_reg);
1582                         temp &= ~FDI_LINK_TRAIN_NONE;
1583                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1584                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1585                         I915_READ(fdi_rx_reg);
1586
1587                         udelay(150);
1588
1589                         /* Train FDI. */
1590                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1591                            for train result */
1592                         temp = I915_READ(fdi_rx_imr_reg);
1593                         temp &= ~FDI_RX_SYMBOL_LOCK;
1594                         temp &= ~FDI_RX_BIT_LOCK;
1595                         I915_WRITE(fdi_rx_imr_reg, temp);
1596                         I915_READ(fdi_rx_imr_reg);
1597                         udelay(150);
1598
1599                         temp = I915_READ(fdi_rx_iir_reg);
1600                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1601
1602                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1603                                 for (j = 0; j < tries; j++) {
1604                                         temp = I915_READ(fdi_rx_iir_reg);
1605                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1606                                                                 temp);
1607                                         if (temp & FDI_RX_BIT_LOCK)
1608                                                 break;
1609                                         udelay(200);
1610                                 }
1611                                 if (j != tries)
1612                                         I915_WRITE(fdi_rx_iir_reg,
1613                                                         temp | FDI_RX_BIT_LOCK);
1614                                 else
1615                                         DRM_DEBUG_KMS("train 1 fail\n");
1616                         } else {
1617                                 I915_WRITE(fdi_rx_iir_reg,
1618                                                 temp | FDI_RX_BIT_LOCK);
1619                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1620                         }
1621                         temp = I915_READ(fdi_tx_reg);
1622                         temp &= ~FDI_LINK_TRAIN_NONE;
1623                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1624                         I915_WRITE(fdi_tx_reg, temp);
1625
1626                         temp = I915_READ(fdi_rx_reg);
1627                         temp &= ~FDI_LINK_TRAIN_NONE;
1628                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1629                         I915_WRITE(fdi_rx_reg, temp);
1630
1631                         udelay(150);
1632
1633                         temp = I915_READ(fdi_rx_iir_reg);
1634                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1635
1636                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1637                                 for (j = 0; j < tries; j++) {
1638                                         temp = I915_READ(fdi_rx_iir_reg);
1639                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1640                                                                 temp);
1641                                         if (temp & FDI_RX_SYMBOL_LOCK)
1642                                                 break;
1643                                         udelay(200);
1644                                 }
1645                                 if (j != tries) {
1646                                         I915_WRITE(fdi_rx_iir_reg,
1647                                                         temp | FDI_RX_SYMBOL_LOCK);
1648                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1649                                 } else
1650                                         DRM_DEBUG_KMS("train 2 fail\n");
1651                         } else {
1652                                 I915_WRITE(fdi_rx_iir_reg,
1653                                                 temp | FDI_RX_SYMBOL_LOCK);
1654                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1655                         }
1656                         DRM_DEBUG_KMS("train done\n");
1657
1658                         /* set transcoder timing */
1659                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1660                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1661                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1662
1663                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1664                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1665                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1666
1667                         /* enable PCH transcoder */
1668                         temp = I915_READ(transconf_reg);
1669                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1670                         I915_READ(transconf_reg);
1671
1672                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1673                                 ;
1674
1675                         /* enable normal */
1676
1677                         temp = I915_READ(fdi_tx_reg);
1678                         temp &= ~FDI_LINK_TRAIN_NONE;
1679                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1680                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1681                         I915_READ(fdi_tx_reg);
1682
1683                         temp = I915_READ(fdi_rx_reg);
1684                         temp &= ~FDI_LINK_TRAIN_NONE;
1685                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1686                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1687                         I915_READ(fdi_rx_reg);
1688
1689                         /* wait one idle pattern time */
1690                         udelay(100);
1691
1692                 }
1693
1694                 intel_crtc_load_lut(crtc);
1695
1696         break;
1697         case DRM_MODE_DPMS_OFF:
1698                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1699
1700                 /* Disable display plane */
1701                 temp = I915_READ(dspcntr_reg);
1702                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1703                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1704                         /* Flush the plane changes */
1705                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1706                         I915_READ(dspbase_reg);
1707                 }
1708
1709                 i915_disable_vga(dev);
1710
1711                 /* disable cpu pipe, disable after all planes disabled */
1712                 temp = I915_READ(pipeconf_reg);
1713                 if ((temp & PIPEACONF_ENABLE) != 0) {
1714                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1715                         I915_READ(pipeconf_reg);
1716                         n = 0;
1717                         /* wait for cpu pipe off, pipe state */
1718                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1719                                 n++;
1720                                 if (n < 60) {
1721                                         udelay(500);
1722                                         continue;
1723                                 } else {
1724                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1725                                                                 pipe);
1726                                         break;
1727                                 }
1728                         }
1729                 } else
1730                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1731
1732                 udelay(100);
1733
1734                 /* Disable PF */
1735                 temp = I915_READ(pf_ctl_reg);
1736                 if ((temp & PF_ENABLE) != 0) {
1737                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1738                         I915_READ(pf_ctl_reg);
1739                 }
1740                 I915_WRITE(pf_win_size, 0);
1741
1742                 /* disable CPU FDI tx and PCH FDI rx */
1743                 temp = I915_READ(fdi_tx_reg);
1744                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1745                 I915_READ(fdi_tx_reg);
1746
1747                 temp = I915_READ(fdi_rx_reg);
1748                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1749                 I915_READ(fdi_rx_reg);
1750
1751                 udelay(100);
1752
1753                 /* still set train pattern 1 */
1754                 temp = I915_READ(fdi_tx_reg);
1755                 temp &= ~FDI_LINK_TRAIN_NONE;
1756                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1757                 I915_WRITE(fdi_tx_reg, temp);
1758
1759                 temp = I915_READ(fdi_rx_reg);
1760                 temp &= ~FDI_LINK_TRAIN_NONE;
1761                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1762                 I915_WRITE(fdi_rx_reg, temp);
1763
1764                 udelay(100);
1765
1766                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1767                         temp = I915_READ(PCH_LVDS);
1768                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1769                         I915_READ(PCH_LVDS);
1770                         udelay(100);
1771                 }
1772
1773                 /* disable PCH transcoder */
1774                 temp = I915_READ(transconf_reg);
1775                 if ((temp & TRANS_ENABLE) != 0) {
1776                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1777                         I915_READ(transconf_reg);
1778                         n = 0;
1779                         /* wait for PCH transcoder off, transcoder state */
1780                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1781                                 n++;
1782                                 if (n < 60) {
1783                                         udelay(500);
1784                                         continue;
1785                                 } else {
1786                                         DRM_DEBUG_KMS("transcoder %d off "
1787                                                         "delay\n", pipe);
1788                                         break;
1789                                 }
1790                         }
1791                 }
1792
1793                 udelay(100);
1794
1795                 /* disable PCH DPLL */
1796                 temp = I915_READ(pch_dpll_reg);
1797                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1798                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1799                         I915_READ(pch_dpll_reg);
1800                 }
1801
1802                 if (HAS_eDP) {
1803                         ironlake_disable_pll_edp(crtc);
1804                 }
1805
1806                 temp = I915_READ(fdi_rx_reg);
1807                 temp &= ~FDI_SEL_PCDCLK;
1808                 I915_WRITE(fdi_rx_reg, temp);
1809                 I915_READ(fdi_rx_reg);
1810
1811                 temp = I915_READ(fdi_rx_reg);
1812                 temp &= ~FDI_RX_PLL_ENABLE;
1813                 I915_WRITE(fdi_rx_reg, temp);
1814                 I915_READ(fdi_rx_reg);
1815
1816                 /* Disable CPU FDI TX PLL */
1817                 temp = I915_READ(fdi_tx_reg);
1818                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1819                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1820                         I915_READ(fdi_tx_reg);
1821                         udelay(100);
1822                 }
1823
1824                 /* Wait for the clocks to turn off. */
1825                 udelay(100);
1826                 break;
1827         }
1828 }
1829
1830 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1831 {
1832         struct intel_overlay *overlay;
1833         int ret;
1834
1835         if (!enable && intel_crtc->overlay) {
1836                 overlay = intel_crtc->overlay;
1837                 mutex_lock(&overlay->dev->struct_mutex);
1838                 for (;;) {
1839                         ret = intel_overlay_switch_off(overlay);
1840                         if (ret == 0)
1841                                 break;
1842
1843                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1844                         if (ret != 0) {
1845                                 /* overlay doesn't react anymore. Usually
1846                                  * results in a black screen and an unkillable
1847                                  * X server. */
1848                                 BUG();
1849                                 overlay->hw_wedged = HW_WEDGED;
1850                                 break;
1851                         }
1852                 }
1853                 mutex_unlock(&overlay->dev->struct_mutex);
1854         }
1855         /* Let userspace switch the overlay on again. In most cases userspace
1856          * has to recompute where to put it anyway. */
1857
1858         return;
1859 }
1860
1861 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1862 {
1863         struct drm_device *dev = crtc->dev;
1864         struct drm_i915_private *dev_priv = dev->dev_private;
1865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1866         int pipe = intel_crtc->pipe;
1867         int plane = intel_crtc->plane;
1868         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1869         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1870         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1871         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1872         u32 temp;
1873
1874         /* XXX: When our outputs are all unaware of DPMS modes other than off
1875          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1876          */
1877         switch (mode) {
1878         case DRM_MODE_DPMS_ON:
1879         case DRM_MODE_DPMS_STANDBY:
1880         case DRM_MODE_DPMS_SUSPEND:
1881                 intel_update_watermarks(dev);
1882
1883                 /* Enable the DPLL */
1884                 temp = I915_READ(dpll_reg);
1885                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1886                         I915_WRITE(dpll_reg, temp);
1887                         I915_READ(dpll_reg);
1888                         /* Wait for the clocks to stabilize. */
1889                         udelay(150);
1890                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1891                         I915_READ(dpll_reg);
1892                         /* Wait for the clocks to stabilize. */
1893                         udelay(150);
1894                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1895                         I915_READ(dpll_reg);
1896                         /* Wait for the clocks to stabilize. */
1897                         udelay(150);
1898                 }
1899
1900                 /* Enable the pipe */
1901                 temp = I915_READ(pipeconf_reg);
1902                 if ((temp & PIPEACONF_ENABLE) == 0)
1903                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1904
1905                 /* Enable the plane */
1906                 temp = I915_READ(dspcntr_reg);
1907                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1908                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1909                         /* Flush the plane changes */
1910                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1911                 }
1912
1913                 intel_crtc_load_lut(crtc);
1914
1915                 if ((IS_I965G(dev) || plane == 0))
1916                         intel_update_fbc(crtc, &crtc->mode);
1917
1918                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1919                 intel_crtc_dpms_overlay(intel_crtc, true);
1920         break;
1921         case DRM_MODE_DPMS_OFF:
1922                 intel_update_watermarks(dev);
1923
1924                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1925                 intel_crtc_dpms_overlay(intel_crtc, false);
1926                 drm_vblank_off(dev, pipe);
1927
1928                 if (dev_priv->cfb_plane == plane &&
1929                     dev_priv->display.disable_fbc)
1930                         dev_priv->display.disable_fbc(dev);
1931
1932                 /* Disable the VGA plane that we never use */
1933                 i915_disable_vga(dev);
1934
1935                 /* Disable display plane */
1936                 temp = I915_READ(dspcntr_reg);
1937                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1938                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1939                         /* Flush the plane changes */
1940                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1941                         I915_READ(dspbase_reg);
1942                 }
1943
1944                 if (!IS_I9XX(dev)) {
1945                         /* Wait for vblank for the disable to take effect */
1946                         intel_wait_for_vblank(dev);
1947                 }
1948
1949                 /* Next, disable display pipes */
1950                 temp = I915_READ(pipeconf_reg);
1951                 if ((temp & PIPEACONF_ENABLE) != 0) {
1952                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1953                         I915_READ(pipeconf_reg);
1954                 }
1955
1956                 /* Wait for vblank for the disable to take effect. */
1957                 intel_wait_for_vblank(dev);
1958
1959                 temp = I915_READ(dpll_reg);
1960                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1961                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1962                         I915_READ(dpll_reg);
1963                 }
1964
1965                 /* Wait for the clocks to turn off. */
1966                 udelay(150);
1967                 break;
1968         }
1969 }
1970
1971 /**
1972  * Sets the power management mode of the pipe and plane.
1973  *
1974  * This code should probably grow support for turning the cursor off and back
1975  * on appropriately at the same time as we're turning the pipe off/on.
1976  */
1977 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1978 {
1979         struct drm_device *dev = crtc->dev;
1980         struct drm_i915_private *dev_priv = dev->dev_private;
1981         struct drm_i915_master_private *master_priv;
1982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983         int pipe = intel_crtc->pipe;
1984         bool enabled;
1985
1986         dev_priv->display.dpms(crtc, mode);
1987
1988         intel_crtc->dpms_mode = mode;
1989
1990         if (!dev->primary->master)
1991                 return;
1992
1993         master_priv = dev->primary->master->driver_priv;
1994         if (!master_priv->sarea_priv)
1995                 return;
1996
1997         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1998
1999         switch (pipe) {
2000         case 0:
2001                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2002                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2003                 break;
2004         case 1:
2005                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2006                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2007                 break;
2008         default:
2009                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2010                 break;
2011         }
2012 }
2013
2014 static void intel_crtc_prepare (struct drm_crtc *crtc)
2015 {
2016         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2017         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2018 }
2019
2020 static void intel_crtc_commit (struct drm_crtc *crtc)
2021 {
2022         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2023         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2024 }
2025
2026 void intel_encoder_prepare (struct drm_encoder *encoder)
2027 {
2028         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2029         /* lvds has its own version of prepare see intel_lvds_prepare */
2030         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2031 }
2032
2033 void intel_encoder_commit (struct drm_encoder *encoder)
2034 {
2035         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2036         /* lvds has its own version of commit see intel_lvds_commit */
2037         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2038 }
2039
2040 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2041                                   struct drm_display_mode *mode,
2042                                   struct drm_display_mode *adjusted_mode)
2043 {
2044         struct drm_device *dev = crtc->dev;
2045         if (IS_IRONLAKE(dev)) {
2046                 /* FDI link clock is fixed at 2.7G */
2047                 if (mode->clock * 3 > 27000 * 4)
2048                         return MODE_CLOCK_HIGH;
2049         }
2050         return true;
2051 }
2052
2053 static int i945_get_display_clock_speed(struct drm_device *dev)
2054 {
2055         return 400000;
2056 }
2057
2058 static int i915_get_display_clock_speed(struct drm_device *dev)
2059 {
2060         return 333000;
2061 }
2062
2063 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2064 {
2065         return 200000;
2066 }
2067
2068 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2069 {
2070         u16 gcfgc = 0;
2071
2072         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2073
2074         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2075                 return 133000;
2076         else {
2077                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2078                 case GC_DISPLAY_CLOCK_333_MHZ:
2079                         return 333000;
2080                 default:
2081                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2082                         return 190000;
2083                 }
2084         }
2085 }
2086
2087 static int i865_get_display_clock_speed(struct drm_device *dev)
2088 {
2089         return 266000;
2090 }
2091
2092 static int i855_get_display_clock_speed(struct drm_device *dev)
2093 {
2094         u16 hpllcc = 0;
2095         /* Assume that the hardware is in the high speed state.  This
2096          * should be the default.
2097          */
2098         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2099         case GC_CLOCK_133_200:
2100         case GC_CLOCK_100_200:
2101                 return 200000;
2102         case GC_CLOCK_166_250:
2103                 return 250000;
2104         case GC_CLOCK_100_133:
2105                 return 133000;
2106         }
2107
2108         /* Shouldn't happen */
2109         return 0;
2110 }
2111
2112 static int i830_get_display_clock_speed(struct drm_device *dev)
2113 {
2114         return 133000;
2115 }
2116
2117 /**
2118  * Return the pipe currently connected to the panel fitter,
2119  * or -1 if the panel fitter is not present or not in use
2120  */
2121 int intel_panel_fitter_pipe (struct drm_device *dev)
2122 {
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124         u32  pfit_control;
2125
2126         /* i830 doesn't have a panel fitter */
2127         if (IS_I830(dev))
2128                 return -1;
2129
2130         pfit_control = I915_READ(PFIT_CONTROL);
2131
2132         /* See if the panel fitter is in use */
2133         if ((pfit_control & PFIT_ENABLE) == 0)
2134                 return -1;
2135
2136         /* 965 can place panel fitter on either pipe */
2137         if (IS_I965G(dev))
2138                 return (pfit_control >> 29) & 0x3;
2139
2140         /* older chips can only use pipe 1 */
2141         return 1;
2142 }
2143
2144 struct fdi_m_n {
2145         u32        tu;
2146         u32        gmch_m;
2147         u32        gmch_n;
2148         u32        link_m;
2149         u32        link_n;
2150 };
2151
2152 static void
2153 fdi_reduce_ratio(u32 *num, u32 *den)
2154 {
2155         while (*num > 0xffffff || *den > 0xffffff) {
2156                 *num >>= 1;
2157                 *den >>= 1;
2158         }
2159 }
2160
2161 #define DATA_N 0x800000
2162 #define LINK_N 0x80000
2163
2164 static void
2165 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2166                      int link_clock, struct fdi_m_n *m_n)
2167 {
2168         u64 temp;
2169
2170         m_n->tu = 64; /* default size */
2171
2172         temp = (u64) DATA_N * pixel_clock;
2173         temp = div_u64(temp, link_clock);
2174         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2175         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2176         m_n->gmch_n = DATA_N;
2177         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2178
2179         temp = (u64) LINK_N * pixel_clock;
2180         m_n->link_m = div_u64(temp, link_clock);
2181         m_n->link_n = LINK_N;
2182         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2183 }
2184
2185
2186 struct intel_watermark_params {
2187         unsigned long fifo_size;
2188         unsigned long max_wm;
2189         unsigned long default_wm;
2190         unsigned long guard_size;
2191         unsigned long cacheline_size;
2192 };
2193
2194 /* Pineview has different values for various configs */
2195 static struct intel_watermark_params pineview_display_wm = {
2196         PINEVIEW_DISPLAY_FIFO,
2197         PINEVIEW_MAX_WM,
2198         PINEVIEW_DFT_WM,
2199         PINEVIEW_GUARD_WM,
2200         PINEVIEW_FIFO_LINE_SIZE
2201 };
2202 static struct intel_watermark_params pineview_display_hplloff_wm = {
2203         PINEVIEW_DISPLAY_FIFO,
2204         PINEVIEW_MAX_WM,
2205         PINEVIEW_DFT_HPLLOFF_WM,
2206         PINEVIEW_GUARD_WM,
2207         PINEVIEW_FIFO_LINE_SIZE
2208 };
2209 static struct intel_watermark_params pineview_cursor_wm = {
2210         PINEVIEW_CURSOR_FIFO,
2211         PINEVIEW_CURSOR_MAX_WM,
2212         PINEVIEW_CURSOR_DFT_WM,
2213         PINEVIEW_CURSOR_GUARD_WM,
2214         PINEVIEW_FIFO_LINE_SIZE,
2215 };
2216 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2217         PINEVIEW_CURSOR_FIFO,
2218         PINEVIEW_CURSOR_MAX_WM,
2219         PINEVIEW_CURSOR_DFT_WM,
2220         PINEVIEW_CURSOR_GUARD_WM,
2221         PINEVIEW_FIFO_LINE_SIZE
2222 };
2223 static struct intel_watermark_params g4x_wm_info = {
2224         G4X_FIFO_SIZE,
2225         G4X_MAX_WM,
2226         G4X_MAX_WM,
2227         2,
2228         G4X_FIFO_LINE_SIZE,
2229 };
2230 static struct intel_watermark_params i945_wm_info = {
2231         I945_FIFO_SIZE,
2232         I915_MAX_WM,
2233         1,
2234         2,
2235         I915_FIFO_LINE_SIZE
2236 };
2237 static struct intel_watermark_params i915_wm_info = {
2238         I915_FIFO_SIZE,
2239         I915_MAX_WM,
2240         1,
2241         2,
2242         I915_FIFO_LINE_SIZE
2243 };
2244 static struct intel_watermark_params i855_wm_info = {
2245         I855GM_FIFO_SIZE,
2246         I915_MAX_WM,
2247         1,
2248         2,
2249         I830_FIFO_LINE_SIZE
2250 };
2251 static struct intel_watermark_params i830_wm_info = {
2252         I830_FIFO_SIZE,
2253         I915_MAX_WM,
2254         1,
2255         2,
2256         I830_FIFO_LINE_SIZE
2257 };
2258
2259 /**
2260  * intel_calculate_wm - calculate watermark level
2261  * @clock_in_khz: pixel clock
2262  * @wm: chip FIFO params
2263  * @pixel_size: display pixel size
2264  * @latency_ns: memory latency for the platform
2265  *
2266  * Calculate the watermark level (the level at which the display plane will
2267  * start fetching from memory again).  Each chip has a different display
2268  * FIFO size and allocation, so the caller needs to figure that out and pass
2269  * in the correct intel_watermark_params structure.
2270  *
2271  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2272  * on the pixel size.  When it reaches the watermark level, it'll start
2273  * fetching FIFO line sized based chunks from memory until the FIFO fills
2274  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2275  * will occur, and a display engine hang could result.
2276  */
2277 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2278                                         struct intel_watermark_params *wm,
2279                                         int pixel_size,
2280                                         unsigned long latency_ns)
2281 {
2282         long entries_required, wm_size;
2283
2284         /*
2285          * Note: we need to make sure we don't overflow for various clock &
2286          * latency values.
2287          * clocks go from a few thousand to several hundred thousand.
2288          * latency is usually a few thousand
2289          */
2290         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2291                 1000;
2292         entries_required /= wm->cacheline_size;
2293
2294         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2295
2296         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2297
2298         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2299
2300         /* Don't promote wm_size to unsigned... */
2301         if (wm_size > (long)wm->max_wm)
2302                 wm_size = wm->max_wm;
2303         if (wm_size <= 0)
2304                 wm_size = wm->default_wm;
2305         return wm_size;
2306 }
2307
2308 struct cxsr_latency {
2309         int is_desktop;
2310         unsigned long fsb_freq;
2311         unsigned long mem_freq;
2312         unsigned long display_sr;
2313         unsigned long display_hpll_disable;
2314         unsigned long cursor_sr;
2315         unsigned long cursor_hpll_disable;
2316 };
2317
2318 static struct cxsr_latency cxsr_latency_table[] = {
2319         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2320         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2321         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2322
2323         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2324         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2325         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2326
2327         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2328         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2329         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2330
2331         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2332         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2333         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2334
2335         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2336         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2337         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2338
2339         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2340         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2341         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2342 };
2343
2344 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2345                                                    int mem)
2346 {
2347         int i;
2348         struct cxsr_latency *latency;
2349
2350         if (fsb == 0 || mem == 0)
2351                 return NULL;
2352
2353         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2354                 latency = &cxsr_latency_table[i];
2355                 if (is_desktop == latency->is_desktop &&
2356                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2357                         return latency;
2358         }
2359
2360         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2361
2362         return NULL;
2363 }
2364
2365 static void pineview_disable_cxsr(struct drm_device *dev)
2366 {
2367         struct drm_i915_private *dev_priv = dev->dev_private;
2368         u32 reg;
2369
2370         /* deactivate cxsr */
2371         reg = I915_READ(DSPFW3);
2372         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2373         I915_WRITE(DSPFW3, reg);
2374         DRM_INFO("Big FIFO is disabled\n");
2375 }
2376
2377 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2378                                  int pixel_size)
2379 {
2380         struct drm_i915_private *dev_priv = dev->dev_private;
2381         u32 reg;
2382         unsigned long wm;
2383         struct cxsr_latency *latency;
2384
2385         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2386                 dev_priv->mem_freq);
2387         if (!latency) {
2388                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2389                 pineview_disable_cxsr(dev);
2390                 return;
2391         }
2392
2393         /* Display SR */
2394         wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2395                                 latency->display_sr);
2396         reg = I915_READ(DSPFW1);
2397         reg &= 0x7fffff;
2398         reg |= wm << 23;
2399         I915_WRITE(DSPFW1, reg);
2400         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2401
2402         /* cursor SR */
2403         wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2404                                 latency->cursor_sr);
2405         reg = I915_READ(DSPFW3);
2406         reg &= ~(0x3f << 24);
2407         reg |= (wm & 0x3f) << 24;
2408         I915_WRITE(DSPFW3, reg);
2409
2410         /* Display HPLL off SR */
2411         wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2412                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2413         reg = I915_READ(DSPFW3);
2414         reg &= 0xfffffe00;
2415         reg |= wm & 0x1ff;
2416         I915_WRITE(DSPFW3, reg);
2417
2418         /* cursor HPLL off SR */
2419         wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2420                                 latency->cursor_hpll_disable);
2421         reg = I915_READ(DSPFW3);
2422         reg &= ~(0x3f << 16);
2423         reg |= (wm & 0x3f) << 16;
2424         I915_WRITE(DSPFW3, reg);
2425         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2426
2427         /* activate cxsr */
2428         reg = I915_READ(DSPFW3);
2429         reg |= PINEVIEW_SELF_REFRESH_EN;
2430         I915_WRITE(DSPFW3, reg);
2431
2432         DRM_INFO("Big FIFO is enabled\n");
2433
2434         return;
2435 }
2436
2437 /*
2438  * Latency for FIFO fetches is dependent on several factors:
2439  *   - memory configuration (speed, channels)
2440  *   - chipset
2441  *   - current MCH state
2442  * It can be fairly high in some situations, so here we assume a fairly
2443  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2444  * set this value too high, the FIFO will fetch frequently to stay full)
2445  * and power consumption (set it too low to save power and we might see
2446  * FIFO underruns and display "flicker").
2447  *
2448  * A value of 5us seems to be a good balance; safe for very low end
2449  * platforms but not overly aggressive on lower latency configs.
2450  */
2451 const static int latency_ns = 5000;
2452
2453 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2454 {
2455         struct drm_i915_private *dev_priv = dev->dev_private;
2456         uint32_t dsparb = I915_READ(DSPARB);
2457         int size;
2458
2459         if (plane == 0)
2460                 size = dsparb & 0x7f;
2461         else
2462                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2463                         (dsparb & 0x7f);
2464
2465         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2466                         plane ? "B" : "A", size);
2467
2468         return size;
2469 }
2470
2471 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2472 {
2473         struct drm_i915_private *dev_priv = dev->dev_private;
2474         uint32_t dsparb = I915_READ(DSPARB);
2475         int size;
2476
2477         if (plane == 0)
2478                 size = dsparb & 0x1ff;
2479         else
2480                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2481                         (dsparb & 0x1ff);
2482         size >>= 1; /* Convert to cachelines */
2483
2484         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2485                         plane ? "B" : "A", size);
2486
2487         return size;
2488 }
2489
2490 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2491 {
2492         struct drm_i915_private *dev_priv = dev->dev_private;
2493         uint32_t dsparb = I915_READ(DSPARB);
2494         int size;
2495
2496         size = dsparb & 0x7f;
2497         size >>= 2; /* Convert to cachelines */
2498
2499         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2500                         plane ? "B" : "A",
2501                   size);
2502
2503         return size;
2504 }
2505
2506 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2507 {
2508         struct drm_i915_private *dev_priv = dev->dev_private;
2509         uint32_t dsparb = I915_READ(DSPARB);
2510         int size;
2511
2512         size = dsparb & 0x7f;
2513         size >>= 1; /* Convert to cachelines */
2514
2515         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2516                         plane ? "B" : "A", size);
2517
2518         return size;
2519 }
2520
2521 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2522                           int planeb_clock, int sr_hdisplay, int pixel_size)
2523 {
2524         struct drm_i915_private *dev_priv = dev->dev_private;
2525         int total_size, cacheline_size;
2526         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2527         struct intel_watermark_params planea_params, planeb_params;
2528         unsigned long line_time_us;
2529         int sr_clock, sr_entries = 0, entries_required;
2530
2531         /* Create copies of the base settings for each pipe */
2532         planea_params = planeb_params = g4x_wm_info;
2533
2534         /* Grab a couple of global values before we overwrite them */
2535         total_size = planea_params.fifo_size;
2536         cacheline_size = planea_params.cacheline_size;
2537
2538         /*
2539          * Note: we need to make sure we don't overflow for various clock &
2540          * latency values.
2541          * clocks go from a few thousand to several hundred thousand.
2542          * latency is usually a few thousand
2543          */
2544         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2545                 1000;
2546         entries_required /= G4X_FIFO_LINE_SIZE;
2547         planea_wm = entries_required + planea_params.guard_size;
2548
2549         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2550                 1000;
2551         entries_required /= G4X_FIFO_LINE_SIZE;
2552         planeb_wm = entries_required + planeb_params.guard_size;
2553
2554         cursora_wm = cursorb_wm = 16;
2555         cursor_sr = 32;
2556
2557         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2558
2559         /* Calc sr entries for one plane configs */
2560         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2561                 /* self-refresh has much higher latency */
2562                 const static int sr_latency_ns = 12000;
2563
2564                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2565                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2566
2567                 /* Use ns/us then divide to preserve precision */
2568                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2569                               pixel_size * sr_hdisplay) / 1000;
2570                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2571                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2572                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2573         }
2574
2575         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2576                   planea_wm, planeb_wm, sr_entries);
2577
2578         planea_wm &= 0x3f;
2579         planeb_wm &= 0x3f;
2580
2581         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2582                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2583                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2584         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2585                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2586         /* HPLL off in SR has some issues on G4x... disable it */
2587         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2588                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2589 }
2590
2591 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2592                            int planeb_clock, int sr_hdisplay, int pixel_size)
2593 {
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         unsigned long line_time_us;
2596         int sr_clock, sr_entries, srwm = 1;
2597
2598         /* Calc sr entries for one plane configs */
2599         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2600                 /* self-refresh has much higher latency */
2601                 const static int sr_latency_ns = 12000;
2602
2603                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2604                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2605
2606                 /* Use ns/us then divide to preserve precision */
2607                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2608                               pixel_size * sr_hdisplay) / 1000;
2609                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2610                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2611                 srwm = I945_FIFO_SIZE - sr_entries;
2612                 if (srwm < 0)
2613                         srwm = 1;
2614                 srwm &= 0x3f;
2615                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2616         }
2617
2618         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2619                       srwm);
2620
2621         /* 965 has limitations... */
2622         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2623                    (8 << 0));
2624         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2625 }
2626
2627 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2628                            int planeb_clock, int sr_hdisplay, int pixel_size)
2629 {
2630         struct drm_i915_private *dev_priv = dev->dev_private;
2631         uint32_t fwater_lo;
2632         uint32_t fwater_hi;
2633         int total_size, cacheline_size, cwm, srwm = 1;
2634         int planea_wm, planeb_wm;
2635         struct intel_watermark_params planea_params, planeb_params;
2636         unsigned long line_time_us;
2637         int sr_clock, sr_entries = 0;
2638
2639         /* Create copies of the base settings for each pipe */
2640         if (IS_I965GM(dev) || IS_I945GM(dev))
2641                 planea_params = planeb_params = i945_wm_info;
2642         else if (IS_I9XX(dev))
2643                 planea_params = planeb_params = i915_wm_info;
2644         else
2645                 planea_params = planeb_params = i855_wm_info;
2646
2647         /* Grab a couple of global values before we overwrite them */
2648         total_size = planea_params.fifo_size;
2649         cacheline_size = planea_params.cacheline_size;
2650
2651         /* Update per-plane FIFO sizes */
2652         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2653         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2654
2655         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2656                                        pixel_size, latency_ns);
2657         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2658                                        pixel_size, latency_ns);
2659         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2660
2661         /*
2662          * Overlay gets an aggressive default since video jitter is bad.
2663          */
2664         cwm = 2;
2665
2666         /* Calc sr entries for one plane configs */
2667         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2668             (!planea_clock || !planeb_clock)) {
2669                 /* self-refresh has much higher latency */
2670                 const static int sr_latency_ns = 6000;
2671
2672                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2673                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2674
2675                 /* Use ns/us then divide to preserve precision */
2676                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2677                               pixel_size * sr_hdisplay) / 1000;
2678                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2679                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2680                 srwm = total_size - sr_entries;
2681                 if (srwm < 0)
2682                         srwm = 1;
2683                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2684         }
2685
2686         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2687                   planea_wm, planeb_wm, cwm, srwm);
2688
2689         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2690         fwater_hi = (cwm & 0x1f);
2691
2692         /* Set request length to 8 cachelines per fetch */
2693         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2694         fwater_hi = fwater_hi | (1 << 8);
2695
2696         I915_WRITE(FW_BLC, fwater_lo);
2697         I915_WRITE(FW_BLC2, fwater_hi);
2698 }
2699
2700 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2701                            int unused2, int pixel_size)
2702 {
2703         struct drm_i915_private *dev_priv = dev->dev_private;
2704         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2705         int planea_wm;
2706
2707         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2708
2709         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2710                                        pixel_size, latency_ns);
2711         fwater_lo |= (3<<8) | planea_wm;
2712
2713         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2714
2715         I915_WRITE(FW_BLC, fwater_lo);
2716 }
2717
2718 /**
2719  * intel_update_watermarks - update FIFO watermark values based on current modes
2720  *
2721  * Calculate watermark values for the various WM regs based on current mode
2722  * and plane configuration.
2723  *
2724  * There are several cases to deal with here:
2725  *   - normal (i.e. non-self-refresh)
2726  *   - self-refresh (SR) mode
2727  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2728  *   - lines are small relative to FIFO size (buffer can hold more than 2
2729  *     lines), so need to account for TLB latency
2730  *
2731  *   The normal calculation is:
2732  *     watermark = dotclock * bytes per pixel * latency
2733  *   where latency is platform & configuration dependent (we assume pessimal
2734  *   values here).
2735  *
2736  *   The SR calculation is:
2737  *     watermark = (trunc(latency/line time)+1) * surface width *
2738  *       bytes per pixel
2739  *   where
2740  *     line time = htotal / dotclock
2741  *   and latency is assumed to be high, as above.
2742  *
2743  * The final value programmed to the register should always be rounded up,
2744  * and include an extra 2 entries to account for clock crossings.
2745  *
2746  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2747  * to set the non-SR watermarks to 8.
2748   */
2749 static void intel_update_watermarks(struct drm_device *dev)
2750 {
2751         struct drm_i915_private *dev_priv = dev->dev_private;
2752         struct drm_crtc *crtc;
2753         struct intel_crtc *intel_crtc;
2754         int sr_hdisplay = 0;
2755         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2756         int enabled = 0, pixel_size = 0;
2757
2758         if (!dev_priv->display.update_wm)
2759                 return;
2760
2761         /* Get the clock config from both planes */
2762         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2763                 intel_crtc = to_intel_crtc(crtc);
2764                 if (crtc->enabled) {
2765                         enabled++;
2766                         if (intel_crtc->plane == 0) {
2767                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2768                                           intel_crtc->pipe, crtc->mode.clock);
2769                                 planea_clock = crtc->mode.clock;
2770                         } else {
2771                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2772                                           intel_crtc->pipe, crtc->mode.clock);
2773                                 planeb_clock = crtc->mode.clock;
2774                         }
2775                         sr_hdisplay = crtc->mode.hdisplay;
2776                         sr_clock = crtc->mode.clock;
2777                         if (crtc->fb)
2778                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2779                         else
2780                                 pixel_size = 4; /* by default */
2781                 }
2782         }
2783
2784         if (enabled <= 0)
2785                 return;
2786
2787         /* Single plane configs can enable self refresh */
2788         if (enabled == 1 && IS_PINEVIEW(dev))
2789                 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2790         else if (IS_PINEVIEW(dev))
2791                 pineview_disable_cxsr(dev);
2792
2793         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2794                                     sr_hdisplay, pixel_size);
2795 }
2796
2797 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2798                                struct drm_display_mode *mode,
2799                                struct drm_display_mode *adjusted_mode,
2800                                int x, int y,
2801                                struct drm_framebuffer *old_fb)
2802 {
2803         struct drm_device *dev = crtc->dev;
2804         struct drm_i915_private *dev_priv = dev->dev_private;
2805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806         int pipe = intel_crtc->pipe;
2807         int plane = intel_crtc->plane;
2808         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2809         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2810         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2811         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2812         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2813         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2814         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2815         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2816         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2817         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2818         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2819         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2820         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2821         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2822         int refclk, num_outputs = 0;
2823         intel_clock_t clock, reduced_clock;
2824         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2825         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2826         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2827         bool is_edp = false;
2828         struct drm_mode_config *mode_config = &dev->mode_config;
2829         struct drm_connector *connector;
2830         const intel_limit_t *limit;
2831         int ret;
2832         struct fdi_m_n m_n = {0};
2833         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2834         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2835         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2836         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2837         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2838         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2839         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2840         int lvds_reg = LVDS;
2841         u32 temp;
2842         int sdvo_pixel_multiply;
2843         int target_clock;
2844
2845         drm_vblank_pre_modeset(dev, pipe);
2846
2847         list_for_each_entry(connector, &mode_config->connector_list, head) {
2848                 struct intel_output *intel_output = to_intel_output(connector);
2849
2850                 if (!connector->encoder || connector->encoder->crtc != crtc)
2851                         continue;
2852
2853                 switch (intel_output->type) {
2854                 case INTEL_OUTPUT_LVDS:
2855                         is_lvds = true;
2856                         break;
2857                 case INTEL_OUTPUT_SDVO:
2858                 case INTEL_OUTPUT_HDMI:
2859                         is_sdvo = true;
2860                         if (intel_output->needs_tv_clock)
2861                                 is_tv = true;
2862                         break;
2863                 case INTEL_OUTPUT_DVO:
2864                         is_dvo = true;
2865                         break;
2866                 case INTEL_OUTPUT_TVOUT:
2867                         is_tv = true;
2868                         break;
2869                 case INTEL_OUTPUT_ANALOG:
2870                         is_crt = true;
2871                         break;
2872                 case INTEL_OUTPUT_DISPLAYPORT:
2873                         is_dp = true;
2874                         break;
2875                 case INTEL_OUTPUT_EDP:
2876                         is_edp = true;
2877                         break;
2878                 }
2879
2880                 num_outputs++;
2881         }
2882
2883         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2884                 refclk = dev_priv->lvds_ssc_freq * 1000;
2885                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2886                                         refclk / 1000);
2887         } else if (IS_I9XX(dev)) {
2888                 refclk = 96000;
2889                 if (IS_IRONLAKE(dev))
2890                         refclk = 120000; /* 120Mhz refclk */
2891         } else {
2892                 refclk = 48000;
2893         }
2894
2895
2896         /*
2897          * Returns a set of divisors for the desired target clock with the given
2898          * refclk, or FALSE.  The returned values represent the clock equation:
2899          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2900          */
2901         limit = intel_limit(crtc);
2902         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2903         if (!ok) {
2904                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2905                 drm_vblank_post_modeset(dev, pipe);
2906                 return -EINVAL;
2907         }
2908
2909         if (is_lvds && limit->find_reduced_pll &&
2910                         dev_priv->lvds_downclock_avail) {
2911                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2912                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2913                                                             dev_priv->lvds_downclock,
2914                                                             refclk,
2915                                                             &reduced_clock);
2916                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2917                         /*
2918                          * If the different P is found, it means that we can't
2919                          * switch the display clock by using the FP0/FP1.
2920                          * In such case we will disable the LVDS downclock
2921                          * feature.
2922                          */
2923                         DRM_DEBUG_KMS("Different P is found for "
2924                                                 "LVDS clock/downclock\n");
2925                         has_reduced_clock = 0;
2926                 }
2927         }
2928         /* SDVO TV has fixed PLL values depend on its clock range,
2929            this mirrors vbios setting. */
2930         if (is_sdvo && is_tv) {
2931                 if (adjusted_mode->clock >= 100000
2932                                 && adjusted_mode->clock < 140500) {
2933                         clock.p1 = 2;
2934                         clock.p2 = 10;
2935                         clock.n = 3;
2936                         clock.m1 = 16;
2937                         clock.m2 = 8;
2938                 } else if (adjusted_mode->clock >= 140500
2939                                 && adjusted_mode->clock <= 200000) {
2940                         clock.p1 = 1;
2941                         clock.p2 = 10;
2942                         clock.n = 6;
2943                         clock.m1 = 12;
2944                         clock.m2 = 8;
2945                 }
2946         }
2947
2948         /* FDI link */
2949         if (IS_IRONLAKE(dev)) {
2950                 int lane, link_bw, bpp;
2951                 /* eDP doesn't require FDI link, so just set DP M/N
2952                    according to current link config */
2953                 if (is_edp) {
2954                         struct drm_connector *edp;
2955                         target_clock = mode->clock;
2956                         edp = intel_pipe_get_output(crtc);
2957                         intel_edp_link_config(to_intel_output(edp),
2958                                         &lane, &link_bw);
2959                 } else {
2960                         /* DP over FDI requires target mode clock
2961                            instead of link clock */
2962                         if (is_dp)
2963                                 target_clock = mode->clock;
2964                         else
2965                                 target_clock = adjusted_mode->clock;
2966                         lane = 4;
2967                         link_bw = 270000;
2968                 }
2969
2970                 /* determine panel color depth */
2971                 temp = I915_READ(pipeconf_reg);
2972
2973                 switch (temp & PIPE_BPC_MASK) {
2974                 case PIPE_8BPC:
2975                         bpp = 24;
2976                         break;
2977                 case PIPE_10BPC:
2978                         bpp = 30;
2979                         break;
2980                 case PIPE_6BPC:
2981                         bpp = 18;
2982                         break;
2983                 case PIPE_12BPC:
2984                         bpp = 36;
2985                         break;
2986                 default:
2987                         DRM_ERROR("unknown pipe bpc value\n");
2988                         bpp = 24;
2989                 }
2990
2991                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
2992         }
2993
2994         /* Ironlake: try to setup display ref clock before DPLL
2995          * enabling. This is only under driver's control after
2996          * PCH B stepping, previous chipset stepping should be
2997          * ignoring this setting.
2998          */
2999         if (IS_IRONLAKE(dev)) {
3000                 temp = I915_READ(PCH_DREF_CONTROL);
3001                 /* Always enable nonspread source */
3002                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3003                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3004                 I915_WRITE(PCH_DREF_CONTROL, temp);
3005                 POSTING_READ(PCH_DREF_CONTROL);
3006
3007                 temp &= ~DREF_SSC_SOURCE_MASK;
3008                 temp |= DREF_SSC_SOURCE_ENABLE;
3009                 I915_WRITE(PCH_DREF_CONTROL, temp);
3010                 POSTING_READ(PCH_DREF_CONTROL);
3011
3012                 udelay(200);
3013
3014                 if (is_edp) {
3015                         if (dev_priv->lvds_use_ssc) {
3016                                 temp |= DREF_SSC1_ENABLE;
3017                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3018                                 POSTING_READ(PCH_DREF_CONTROL);
3019
3020                                 udelay(200);
3021
3022                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3023                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3024                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3025                                 POSTING_READ(PCH_DREF_CONTROL);
3026                         } else {
3027                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3028                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3029                                 POSTING_READ(PCH_DREF_CONTROL);
3030                         }
3031                 }
3032         }
3033
3034         if (IS_PINEVIEW(dev)) {
3035                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3036                 if (has_reduced_clock)
3037                         fp2 = (1 << reduced_clock.n) << 16 |
3038                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3039         } else {
3040                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3041                 if (has_reduced_clock)
3042                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3043                                 reduced_clock.m2;
3044         }
3045
3046         if (!IS_IRONLAKE(dev))
3047                 dpll = DPLL_VGA_MODE_DIS;
3048
3049         if (IS_I9XX(dev)) {
3050                 if (is_lvds)
3051                         dpll |= DPLLB_MODE_LVDS;
3052                 else
3053                         dpll |= DPLLB_MODE_DAC_SERIAL;
3054                 if (is_sdvo) {
3055                         dpll |= DPLL_DVO_HIGH_SPEED;
3056                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3057                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3058                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3059                         else if (IS_IRONLAKE(dev))
3060                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3061                 }
3062                 if (is_dp)
3063                         dpll |= DPLL_DVO_HIGH_SPEED;
3064
3065                 /* compute bitmask from p1 value */
3066                 if (IS_PINEVIEW(dev))
3067                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3068                 else {
3069                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3070                         /* also FPA1 */
3071                         if (IS_IRONLAKE(dev))
3072                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3073                         if (IS_G4X(dev) && has_reduced_clock)
3074                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3075                 }
3076                 switch (clock.p2) {
3077                 case 5:
3078                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3079                         break;
3080                 case 7:
3081                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3082                         break;
3083                 case 10:
3084                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3085                         break;
3086                 case 14:
3087                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3088                         break;
3089                 }
3090                 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
3091                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3092         } else {
3093                 if (is_lvds) {
3094                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3095                 } else {
3096                         if (clock.p1 == 2)
3097                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3098                         else
3099                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3100                         if (clock.p2 == 4)
3101                                 dpll |= PLL_P2_DIVIDE_BY_4;
3102                 }
3103         }
3104
3105         if (is_sdvo && is_tv)
3106                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3107         else if (is_tv)
3108                 /* XXX: just matching BIOS for now */
3109                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3110                 dpll |= 3;
3111         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3112                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3113         else
3114                 dpll |= PLL_REF_INPUT_DREFCLK;
3115
3116         /* setup pipeconf */
3117         pipeconf = I915_READ(pipeconf_reg);
3118
3119         /* Set up the display plane register */
3120         dspcntr = DISPPLANE_GAMMA_ENABLE;
3121
3122         /* Ironlake's plane is forced to pipe, bit 24 is to
3123            enable color space conversion */
3124         if (!IS_IRONLAKE(dev)) {
3125                 if (pipe == 0)
3126                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3127                 else
3128                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3129         }
3130
3131         if (pipe == 0 && !IS_I965G(dev)) {
3132                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3133                  * core speed.
3134                  *
3135                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3136                  * pipe == 0 check?
3137                  */
3138                 if (mode->clock >
3139                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3140                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3141                 else
3142                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3143         }
3144
3145         dspcntr |= DISPLAY_PLANE_ENABLE;
3146         pipeconf |= PIPEACONF_ENABLE;
3147         dpll |= DPLL_VCO_ENABLE;
3148
3149
3150         /* Disable the panel fitter if it was on our pipe */
3151         if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
3152                 I915_WRITE(PFIT_CONTROL, 0);
3153
3154         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3155         drm_mode_debug_printmodeline(mode);
3156
3157         /* assign to Ironlake registers */
3158         if (IS_IRONLAKE(dev)) {
3159                 fp_reg = pch_fp_reg;
3160                 dpll_reg = pch_dpll_reg;
3161         }
3162
3163         if (is_edp) {
3164                 ironlake_disable_pll_edp(crtc);
3165         } else if ((dpll & DPLL_VCO_ENABLE)) {
3166                 I915_WRITE(fp_reg, fp);
3167                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3168                 I915_READ(dpll_reg);
3169                 udelay(150);
3170         }
3171
3172         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3173          * This is an exception to the general rule that mode_set doesn't turn
3174          * things on.
3175          */
3176         if (is_lvds) {
3177                 u32 lvds;
3178
3179                 if (IS_IRONLAKE(dev))
3180                         lvds_reg = PCH_LVDS;
3181
3182                 lvds = I915_READ(lvds_reg);
3183                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3184                 /* set the corresponsding LVDS_BORDER bit */
3185                 lvds |= dev_priv->lvds_border_bits;
3186                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3187                  * set the DPLLs for dual-channel mode or not.
3188                  */
3189                 if (clock.p2 == 7)
3190                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3191                 else
3192                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3193
3194                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3195                  * appropriately here, but we need to look more thoroughly into how
3196                  * panels behave in the two modes.
3197                  */
3198
3199                 I915_WRITE(lvds_reg, lvds);
3200                 I915_READ(lvds_reg);
3201         }
3202         if (is_dp)
3203                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3204
3205         if (!is_edp) {
3206                 I915_WRITE(fp_reg, fp);
3207                 I915_WRITE(dpll_reg, dpll);
3208                 I915_READ(dpll_reg);
3209                 /* Wait for the clocks to stabilize. */
3210                 udelay(150);
3211
3212                 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
3213                         if (is_sdvo) {
3214                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3215                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3216                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3217                         } else
3218                                 I915_WRITE(dpll_md_reg, 0);
3219                 } else {
3220                         /* write it again -- the BIOS does, after all */
3221                         I915_WRITE(dpll_reg, dpll);
3222                 }
3223                 I915_READ(dpll_reg);
3224                 /* Wait for the clocks to stabilize. */
3225                 udelay(150);
3226         }
3227
3228         if (is_lvds && has_reduced_clock && i915_powersave) {
3229                 I915_WRITE(fp_reg + 4, fp2);
3230                 intel_crtc->lowfreq_avail = true;
3231                 if (HAS_PIPE_CXSR(dev)) {
3232                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3233                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3234                 }
3235         } else {
3236                 I915_WRITE(fp_reg + 4, fp);
3237                 intel_crtc->lowfreq_avail = false;
3238                 if (HAS_PIPE_CXSR(dev)) {
3239                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3240                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3241                 }
3242         }
3243
3244         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3245                    ((adjusted_mode->crtc_htotal - 1) << 16));
3246         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3247                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3248         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3249                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3250         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3251                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3252         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3253                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3254         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3255                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3256         /* pipesrc and dspsize control the size that is scaled from, which should
3257          * always be the user's requested size.
3258          */
3259         if (!IS_IRONLAKE(dev)) {
3260                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3261                                 (mode->hdisplay - 1));
3262                 I915_WRITE(dsppos_reg, 0);
3263         }
3264         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3265
3266         if (IS_IRONLAKE(dev)) {
3267                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3268                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3269                 I915_WRITE(link_m1_reg, m_n.link_m);
3270                 I915_WRITE(link_n1_reg, m_n.link_n);
3271
3272                 if (is_edp) {
3273                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3274                 } else {
3275                         /* enable FDI RX PLL too */
3276                         temp = I915_READ(fdi_rx_reg);
3277                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3278                         udelay(200);
3279                 }
3280         }
3281
3282         I915_WRITE(pipeconf_reg, pipeconf);
3283         I915_READ(pipeconf_reg);
3284
3285         intel_wait_for_vblank(dev);
3286
3287         if (IS_IRONLAKE(dev)) {
3288                 /* enable address swizzle for tiling buffer */
3289                 temp = I915_READ(DISP_ARB_CTL);
3290                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3291         }
3292
3293         I915_WRITE(dspcntr_reg, dspcntr);
3294
3295         /* Flush the plane changes */
3296         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3297
3298         if ((IS_I965G(dev) || plane == 0))
3299                 intel_update_fbc(crtc, &crtc->mode);
3300
3301         intel_update_watermarks(dev);
3302
3303         drm_vblank_post_modeset(dev, pipe);
3304
3305         return ret;
3306 }
3307
3308 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3309 void intel_crtc_load_lut(struct drm_crtc *crtc)
3310 {
3311         struct drm_device *dev = crtc->dev;
3312         struct drm_i915_private *dev_priv = dev->dev_private;
3313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3314         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3315         int i;
3316
3317         /* The clocks have to be on to load the palette. */
3318         if (!crtc->enabled)
3319                 return;
3320
3321         /* use legacy palette for Ironlake */
3322         if (IS_IRONLAKE(dev))
3323                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3324                                                    LGC_PALETTE_B;
3325
3326         for (i = 0; i < 256; i++) {
3327                 I915_WRITE(palreg + 4 * i,
3328                            (intel_crtc->lut_r[i] << 16) |
3329                            (intel_crtc->lut_g[i] << 8) |
3330                            intel_crtc->lut_b[i]);
3331         }
3332 }
3333
3334 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3335                                  struct drm_file *file_priv,
3336                                  uint32_t handle,
3337                                  uint32_t width, uint32_t height)
3338 {
3339         struct drm_device *dev = crtc->dev;
3340         struct drm_i915_private *dev_priv = dev->dev_private;
3341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3342         struct drm_gem_object *bo;
3343         struct drm_i915_gem_object *obj_priv;
3344         int pipe = intel_crtc->pipe;
3345         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3346         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3347         uint32_t temp = I915_READ(control);
3348         size_t addr;
3349         int ret;
3350
3351         DRM_DEBUG_KMS("\n");
3352
3353         /* if we want to turn off the cursor ignore width and height */
3354         if (!handle) {
3355                 DRM_DEBUG_KMS("cursor off\n");
3356                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3357                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3358                         temp |= CURSOR_MODE_DISABLE;
3359                 } else {
3360                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3361                 }
3362                 addr = 0;
3363                 bo = NULL;
3364                 mutex_lock(&dev->struct_mutex);
3365                 goto finish;
3366         }
3367
3368         /* Currently we only support 64x64 cursors */
3369         if (width != 64 || height != 64) {
3370                 DRM_ERROR("we currently only support 64x64 cursors\n");
3371                 return -EINVAL;
3372         }
3373
3374         bo = drm_gem_object_lookup(dev, file_priv, handle);
3375         if (!bo)
3376                 return -ENOENT;
3377
3378         obj_priv = bo->driver_private;
3379
3380         if (bo->size < width * height * 4) {
3381                 DRM_ERROR("buffer is to small\n");
3382                 ret = -ENOMEM;
3383                 goto fail;
3384         }
3385
3386         /* we only need to pin inside GTT if cursor is non-phy */
3387         mutex_lock(&dev->struct_mutex);
3388         if (!dev_priv->info->cursor_needs_physical) {
3389                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3390                 if (ret) {
3391                         DRM_ERROR("failed to pin cursor bo\n");
3392                         goto fail_locked;
3393                 }
3394                 addr = obj_priv->gtt_offset;
3395         } else {
3396                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3397                 if (ret) {
3398                         DRM_ERROR("failed to attach phys object\n");
3399                         goto fail_locked;
3400                 }
3401                 addr = obj_priv->phys_obj->handle->busaddr;
3402         }
3403
3404         if (!IS_I9XX(dev))
3405                 I915_WRITE(CURSIZE, (height << 12) | width);
3406
3407         /* Hooray for CUR*CNTR differences */
3408         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3409                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3410                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3411                 temp |= (pipe << 28); /* Connect to correct pipe */
3412         } else {
3413                 temp &= ~(CURSOR_FORMAT_MASK);
3414                 temp |= CURSOR_ENABLE;
3415                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3416         }
3417
3418  finish:
3419         I915_WRITE(control, temp);
3420         I915_WRITE(base, addr);
3421
3422         if (intel_crtc->cursor_bo) {
3423                 if (dev_priv->info->cursor_needs_physical) {
3424                         if (intel_crtc->cursor_bo != bo)
3425                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3426                 } else
3427                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3428                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3429         }
3430
3431         mutex_unlock(&dev->struct_mutex);
3432
3433         intel_crtc->cursor_addr = addr;
3434         intel_crtc->cursor_bo = bo;
3435
3436         return 0;
3437 fail:
3438         mutex_lock(&dev->struct_mutex);
3439 fail_locked:
3440         drm_gem_object_unreference(bo);
3441         mutex_unlock(&dev->struct_mutex);
3442         return ret;
3443 }
3444
3445 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3446 {
3447         struct drm_device *dev = crtc->dev;
3448         struct drm_i915_private *dev_priv = dev->dev_private;
3449         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3450         struct intel_framebuffer *intel_fb;
3451         int pipe = intel_crtc->pipe;
3452         uint32_t temp = 0;
3453         uint32_t adder;
3454
3455         if (crtc->fb) {
3456                 intel_fb = to_intel_framebuffer(crtc->fb);
3457                 intel_mark_busy(dev, intel_fb->obj);
3458         }
3459
3460         if (x < 0) {
3461                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3462                 x = -x;
3463         }
3464         if (y < 0) {
3465                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3466                 y = -y;
3467         }
3468
3469         temp |= x << CURSOR_X_SHIFT;
3470         temp |= y << CURSOR_Y_SHIFT;
3471
3472         adder = intel_crtc->cursor_addr;
3473         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3474         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3475
3476         return 0;
3477 }
3478
3479 /** Sets the color ramps on behalf of RandR */
3480 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3481                                  u16 blue, int regno)
3482 {
3483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3484
3485         intel_crtc->lut_r[regno] = red >> 8;
3486         intel_crtc->lut_g[regno] = green >> 8;
3487         intel_crtc->lut_b[regno] = blue >> 8;
3488 }
3489
3490 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3491                              u16 *blue, int regno)
3492 {
3493         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3494
3495         *red = intel_crtc->lut_r[regno] << 8;
3496         *green = intel_crtc->lut_g[regno] << 8;
3497         *blue = intel_crtc->lut_b[regno] << 8;
3498 }
3499
3500 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3501                                  u16 *blue, uint32_t size)
3502 {
3503         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3504         int i;
3505
3506         if (size != 256)
3507                 return;
3508
3509         for (i = 0; i < 256; i++) {
3510                 intel_crtc->lut_r[i] = red[i] >> 8;
3511                 intel_crtc->lut_g[i] = green[i] >> 8;
3512                 intel_crtc->lut_b[i] = blue[i] >> 8;
3513         }
3514
3515         intel_crtc_load_lut(crtc);
3516 }
3517
3518 /**
3519  * Get a pipe with a simple mode set on it for doing load-based monitor
3520  * detection.
3521  *
3522  * It will be up to the load-detect code to adjust the pipe as appropriate for
3523  * its requirements.  The pipe will be connected to no other outputs.
3524  *
3525  * Currently this code will only succeed if there is a pipe with no outputs
3526  * configured for it.  In the future, it could choose to temporarily disable
3527  * some outputs to free up a pipe for its use.
3528  *
3529  * \return crtc, or NULL if no pipes are available.
3530  */
3531
3532 /* VESA 640x480x72Hz mode to set on the pipe */
3533 static struct drm_display_mode load_detect_mode = {
3534         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3535                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3536 };
3537
3538 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3539                                             struct drm_display_mode *mode,
3540                                             int *dpms_mode)
3541 {
3542         struct intel_crtc *intel_crtc;
3543         struct drm_crtc *possible_crtc;
3544         struct drm_crtc *supported_crtc =NULL;
3545         struct drm_encoder *encoder = &intel_output->enc;
3546         struct drm_crtc *crtc = NULL;
3547         struct drm_device *dev = encoder->dev;
3548         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3549         struct drm_crtc_helper_funcs *crtc_funcs;
3550         int i = -1;
3551
3552         /*
3553          * Algorithm gets a little messy:
3554          *   - if the connector already has an assigned crtc, use it (but make
3555          *     sure it's on first)
3556          *   - try to find the first unused crtc that can drive this connector,
3557          *     and use that if we find one
3558          *   - if there are no unused crtcs available, try to use the first
3559          *     one we found that supports the connector
3560          */
3561
3562         /* See if we already have a CRTC for this connector */
3563         if (encoder->crtc) {
3564                 crtc = encoder->crtc;
3565                 /* Make sure the crtc and connector are running */
3566                 intel_crtc = to_intel_crtc(crtc);
3567                 *dpms_mode = intel_crtc->dpms_mode;
3568                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3569                         crtc_funcs = crtc->helper_private;
3570                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3571                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3572                 }
3573                 return crtc;
3574         }
3575
3576         /* Find an unused one (if possible) */
3577         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3578                 i++;
3579                 if (!(encoder->possible_crtcs & (1 << i)))
3580                         continue;
3581                 if (!possible_crtc->enabled) {
3582                         crtc = possible_crtc;
3583                         break;
3584                 }
3585                 if (!supported_crtc)
3586                         supported_crtc = possible_crtc;
3587         }
3588
3589         /*
3590          * If we didn't find an unused CRTC, don't use any.
3591          */
3592         if (!crtc) {
3593                 return NULL;
3594         }
3595
3596         encoder->crtc = crtc;
3597         intel_output->base.encoder = encoder;
3598         intel_output->load_detect_temp = true;
3599
3600         intel_crtc = to_intel_crtc(crtc);
3601         *dpms_mode = intel_crtc->dpms_mode;
3602
3603         if (!crtc->enabled) {
3604                 if (!mode)
3605                         mode = &load_detect_mode;
3606                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3607         } else {
3608                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3609                         crtc_funcs = crtc->helper_private;
3610                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3611                 }
3612
3613                 /* Add this connector to the crtc */
3614                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3615                 encoder_funcs->commit(encoder);
3616         }
3617         /* let the connector get through one full cycle before testing */
3618         intel_wait_for_vblank(dev);
3619
3620         return crtc;
3621 }
3622
3623 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3624 {
3625         struct drm_encoder *encoder = &intel_output->enc;
3626         struct drm_device *dev = encoder->dev;
3627         struct drm_crtc *crtc = encoder->crtc;
3628         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3629         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3630
3631         if (intel_output->load_detect_temp) {
3632                 encoder->crtc = NULL;
3633                 intel_output->base.encoder = NULL;
3634                 intel_output->load_detect_temp = false;
3635                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3636                 drm_helper_disable_unused_functions(dev);
3637         }
3638
3639         /* Switch crtc and output back off if necessary */
3640         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3641                 if (encoder->crtc == crtc)
3642                         encoder_funcs->dpms(encoder, dpms_mode);
3643                 crtc_funcs->dpms(crtc, dpms_mode);
3644         }
3645 }
3646
3647 /* Returns the clock of the currently programmed mode of the given pipe. */
3648 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3649 {
3650         struct drm_i915_private *dev_priv = dev->dev_private;
3651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3652         int pipe = intel_crtc->pipe;
3653         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3654         u32 fp;
3655         intel_clock_t clock;
3656
3657         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3658                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3659         else
3660                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3661
3662         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3663         if (IS_PINEVIEW(dev)) {
3664                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3665                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3666         } else {
3667                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3668                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3669         }
3670
3671         if (IS_I9XX(dev)) {
3672                 if (IS_PINEVIEW(dev))
3673                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3674                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3675                 else
3676                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3677                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3678
3679                 switch (dpll & DPLL_MODE_MASK) {
3680                 case DPLLB_MODE_DAC_SERIAL:
3681                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3682                                 5 : 10;
3683                         break;
3684                 case DPLLB_MODE_LVDS:
3685                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3686                                 7 : 14;
3687                         break;
3688                 default:
3689                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3690                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3691                         return 0;
3692                 }
3693
3694                 /* XXX: Handle the 100Mhz refclk */
3695                 intel_clock(dev, 96000, &clock);
3696         } else {
3697                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3698
3699                 if (is_lvds) {
3700                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3701                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3702                         clock.p2 = 14;
3703
3704                         if ((dpll & PLL_REF_INPUT_MASK) ==
3705                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3706                                 /* XXX: might not be 66MHz */
3707                                 intel_clock(dev, 66000, &clock);
3708                         } else
3709                                 intel_clock(dev, 48000, &clock);
3710                 } else {
3711                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3712                                 clock.p1 = 2;
3713                         else {
3714                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3715                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3716                         }
3717                         if (dpll & PLL_P2_DIVIDE_BY_4)
3718                                 clock.p2 = 4;
3719                         else
3720                                 clock.p2 = 2;
3721
3722                         intel_clock(dev, 48000, &clock);
3723                 }
3724         }
3725
3726         /* XXX: It would be nice to validate the clocks, but we can't reuse
3727          * i830PllIsValid() because it relies on the xf86_config connector
3728          * configuration being accurate, which it isn't necessarily.
3729          */
3730
3731         return clock.dot;
3732 }
3733
3734 /** Returns the currently programmed mode of the given pipe. */
3735 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3736                                              struct drm_crtc *crtc)
3737 {
3738         struct drm_i915_private *dev_priv = dev->dev_private;
3739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740         int pipe = intel_crtc->pipe;
3741         struct drm_display_mode *mode;
3742         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3743         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3744         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3745         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3746
3747         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3748         if (!mode)
3749                 return NULL;
3750
3751         mode->clock = intel_crtc_clock_get(dev, crtc);
3752         mode->hdisplay = (htot & 0xffff) + 1;
3753         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3754         mode->hsync_start = (hsync & 0xffff) + 1;
3755         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3756         mode->vdisplay = (vtot & 0xffff) + 1;
3757         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3758         mode->vsync_start = (vsync & 0xffff) + 1;
3759         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3760
3761         drm_mode_set_name(mode);
3762         drm_mode_set_crtcinfo(mode, 0);
3763
3764         return mode;
3765 }
3766
3767 #define GPU_IDLE_TIMEOUT 500 /* ms */
3768
3769 /* When this timer fires, we've been idle for awhile */
3770 static void intel_gpu_idle_timer(unsigned long arg)
3771 {
3772         struct drm_device *dev = (struct drm_device *)arg;
3773         drm_i915_private_t *dev_priv = dev->dev_private;
3774
3775         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3776
3777         dev_priv->busy = false;
3778
3779         queue_work(dev_priv->wq, &dev_priv->idle_work);
3780 }
3781
3782 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3783
3784 static void intel_crtc_idle_timer(unsigned long arg)
3785 {
3786         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3787         struct drm_crtc *crtc = &intel_crtc->base;
3788         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3789
3790         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3791
3792         intel_crtc->busy = false;
3793
3794         queue_work(dev_priv->wq, &dev_priv->idle_work);
3795 }
3796
3797 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3798 {
3799         struct drm_device *dev = crtc->dev;
3800         drm_i915_private_t *dev_priv = dev->dev_private;
3801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3802         int pipe = intel_crtc->pipe;
3803         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3804         int dpll = I915_READ(dpll_reg);
3805
3806         if (IS_IRONLAKE(dev))
3807                 return;
3808
3809         if (!dev_priv->lvds_downclock_avail)
3810                 return;
3811
3812         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3813                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3814
3815                 /* Unlock panel regs */
3816                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3817
3818                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3819                 I915_WRITE(dpll_reg, dpll);
3820                 dpll = I915_READ(dpll_reg);
3821                 intel_wait_for_vblank(dev);
3822                 dpll = I915_READ(dpll_reg);
3823                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3824                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3825
3826                 /* ...and lock them again */
3827                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3828         }
3829
3830         /* Schedule downclock */
3831         if (schedule)
3832                 mod_timer(&intel_crtc->idle_timer, jiffies +
3833                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3834 }
3835
3836 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3837 {
3838         struct drm_device *dev = crtc->dev;
3839         drm_i915_private_t *dev_priv = dev->dev_private;
3840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3841         int pipe = intel_crtc->pipe;
3842         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3843         int dpll = I915_READ(dpll_reg);
3844
3845         if (IS_IRONLAKE(dev))
3846                 return;
3847
3848         if (!dev_priv->lvds_downclock_avail)
3849                 return;
3850
3851         /*
3852          * Since this is called by a timer, we should never get here in
3853          * the manual case.
3854          */
3855         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3856                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3857
3858                 /* Unlock panel regs */
3859                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3860
3861                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3862                 I915_WRITE(dpll_reg, dpll);
3863                 dpll = I915_READ(dpll_reg);
3864                 intel_wait_for_vblank(dev);
3865                 dpll = I915_READ(dpll_reg);
3866                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3867                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3868
3869                 /* ...and lock them again */
3870                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3871         }
3872
3873 }
3874
3875 /**
3876  * intel_idle_update - adjust clocks for idleness
3877  * @work: work struct
3878  *
3879  * Either the GPU or display (or both) went idle.  Check the busy status
3880  * here and adjust the CRTC and GPU clocks as necessary.
3881  */
3882 static void intel_idle_update(struct work_struct *work)
3883 {
3884         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3885                                                     idle_work);
3886         struct drm_device *dev = dev_priv->dev;
3887         struct drm_crtc *crtc;
3888         struct intel_crtc *intel_crtc;
3889
3890         if (!i915_powersave)
3891                 return;
3892
3893         mutex_lock(&dev->struct_mutex);
3894
3895         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3896                 /* Skip inactive CRTCs */
3897                 if (!crtc->fb)
3898                         continue;
3899
3900                 intel_crtc = to_intel_crtc(crtc);
3901                 if (!intel_crtc->busy)
3902                         intel_decrease_pllclock(crtc);
3903         }
3904
3905         mutex_unlock(&dev->struct_mutex);
3906 }
3907
3908 /**
3909  * intel_mark_busy - mark the GPU and possibly the display busy
3910  * @dev: drm device
3911  * @obj: object we're operating on
3912  *
3913  * Callers can use this function to indicate that the GPU is busy processing
3914  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3915  * buffer), we'll also mark the display as busy, so we know to increase its
3916  * clock frequency.
3917  */
3918 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3919 {
3920         drm_i915_private_t *dev_priv = dev->dev_private;
3921         struct drm_crtc *crtc = NULL;
3922         struct intel_framebuffer *intel_fb;
3923         struct intel_crtc *intel_crtc;
3924
3925         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3926                 return;
3927
3928         if (!dev_priv->busy)
3929                 dev_priv->busy = true;
3930         else
3931                 mod_timer(&dev_priv->idle_timer, jiffies +
3932                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3933
3934         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3935                 if (!crtc->fb)
3936                         continue;
3937
3938                 intel_crtc = to_intel_crtc(crtc);
3939                 intel_fb = to_intel_framebuffer(crtc->fb);
3940                 if (intel_fb->obj == obj) {
3941                         if (!intel_crtc->busy) {
3942                                 /* Non-busy -> busy, upclock */
3943                                 intel_increase_pllclock(crtc, true);
3944                                 intel_crtc->busy = true;
3945                         } else {
3946                                 /* Busy -> busy, put off timer */
3947                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3948                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3949                         }
3950                 }
3951         }
3952 }
3953
3954 static void intel_crtc_destroy(struct drm_crtc *crtc)
3955 {
3956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3957
3958         drm_crtc_cleanup(crtc);
3959         kfree(intel_crtc);
3960 }
3961
3962 struct intel_unpin_work {
3963         struct work_struct work;
3964         struct drm_device *dev;
3965         struct drm_gem_object *obj;
3966         struct drm_pending_vblank_event *event;
3967         int pending;
3968 };
3969
3970 static void intel_unpin_work_fn(struct work_struct *__work)
3971 {
3972         struct intel_unpin_work *work =
3973                 container_of(__work, struct intel_unpin_work, work);
3974
3975         mutex_lock(&work->dev->struct_mutex);
3976         i915_gem_object_unpin(work->obj);
3977         drm_gem_object_unreference(work->obj);
3978         mutex_unlock(&work->dev->struct_mutex);
3979         kfree(work);
3980 }
3981
3982 void intel_finish_page_flip(struct drm_device *dev, int pipe)
3983 {
3984         drm_i915_private_t *dev_priv = dev->dev_private;
3985         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3987         struct intel_unpin_work *work;
3988         struct drm_i915_gem_object *obj_priv;
3989         struct drm_pending_vblank_event *e;
3990         struct timeval now;
3991         unsigned long flags;
3992
3993         /* Ignore early vblank irqs */
3994         if (intel_crtc == NULL)
3995                 return;
3996
3997         spin_lock_irqsave(&dev->event_lock, flags);
3998         work = intel_crtc->unpin_work;
3999         if (work == NULL || !work->pending) {
4000                 spin_unlock_irqrestore(&dev->event_lock, flags);
4001                 return;
4002         }
4003
4004         intel_crtc->unpin_work = NULL;
4005         drm_vblank_put(dev, intel_crtc->pipe);
4006
4007         if (work->event) {
4008                 e = work->event;
4009                 do_gettimeofday(&now);
4010                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4011                 e->event.tv_sec = now.tv_sec;
4012                 e->event.tv_usec = now.tv_usec;
4013                 list_add_tail(&e->base.link,
4014                               &e->base.file_priv->event_list);
4015                 wake_up_interruptible(&e->base.file_priv->event_wait);
4016         }
4017
4018         spin_unlock_irqrestore(&dev->event_lock, flags);
4019
4020         obj_priv = work->obj->driver_private;
4021         if (atomic_dec_and_test(&obj_priv->pending_flip))
4022                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4023         schedule_work(&work->work);
4024 }
4025
4026 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4027 {
4028         drm_i915_private_t *dev_priv = dev->dev_private;
4029         struct intel_crtc *intel_crtc =
4030                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4031         unsigned long flags;
4032
4033         spin_lock_irqsave(&dev->event_lock, flags);
4034         if (intel_crtc->unpin_work)
4035                 intel_crtc->unpin_work->pending = 1;
4036         spin_unlock_irqrestore(&dev->event_lock, flags);
4037 }
4038
4039 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4040                                 struct drm_framebuffer *fb,
4041                                 struct drm_pending_vblank_event *event)
4042 {
4043         struct drm_device *dev = crtc->dev;
4044         struct drm_i915_private *dev_priv = dev->dev_private;
4045         struct intel_framebuffer *intel_fb;
4046         struct drm_i915_gem_object *obj_priv;
4047         struct drm_gem_object *obj;
4048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4049         struct intel_unpin_work *work;
4050         unsigned long flags;
4051         int ret;
4052         RING_LOCALS;
4053
4054         work = kzalloc(sizeof *work, GFP_KERNEL);
4055         if (work == NULL)
4056                 return -ENOMEM;
4057
4058         mutex_lock(&dev->struct_mutex);
4059
4060         work->event = event;
4061         work->dev = crtc->dev;
4062         intel_fb = to_intel_framebuffer(crtc->fb);
4063         work->obj = intel_fb->obj;
4064         INIT_WORK(&work->work, intel_unpin_work_fn);
4065
4066         /* We borrow the event spin lock for protecting unpin_work */
4067         spin_lock_irqsave(&dev->event_lock, flags);
4068         if (intel_crtc->unpin_work) {
4069                 spin_unlock_irqrestore(&dev->event_lock, flags);
4070                 kfree(work);
4071                 mutex_unlock(&dev->struct_mutex);
4072                 return -EBUSY;
4073         }
4074         intel_crtc->unpin_work = work;
4075         spin_unlock_irqrestore(&dev->event_lock, flags);
4076
4077         intel_fb = to_intel_framebuffer(fb);
4078         obj = intel_fb->obj;
4079
4080         ret = intel_pin_and_fence_fb_obj(dev, obj);
4081         if (ret != 0) {
4082                 kfree(work);
4083                 mutex_unlock(&dev->struct_mutex);
4084                 return ret;
4085         }
4086
4087         /* Reference the old fb object for the scheduled work. */
4088         drm_gem_object_reference(work->obj);
4089
4090         crtc->fb = fb;
4091         i915_gem_object_flush_write_domain(obj);
4092         drm_vblank_get(dev, intel_crtc->pipe);
4093         obj_priv = obj->driver_private;
4094         atomic_inc(&obj_priv->pending_flip);
4095
4096         BEGIN_LP_RING(4);
4097         OUT_RING(MI_DISPLAY_FLIP |
4098                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4099         OUT_RING(fb->pitch);
4100         if (IS_I965G(dev)) {
4101                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4102                 OUT_RING((fb->width << 16) | fb->height);
4103         } else {
4104                 OUT_RING(obj_priv->gtt_offset);
4105                 OUT_RING(MI_NOOP);
4106         }
4107         ADVANCE_LP_RING();
4108
4109         mutex_unlock(&dev->struct_mutex);
4110
4111         return 0;
4112 }
4113
4114 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4115         .dpms = intel_crtc_dpms,
4116         .mode_fixup = intel_crtc_mode_fixup,
4117         .mode_set = intel_crtc_mode_set,
4118         .mode_set_base = intel_pipe_set_base,
4119         .prepare = intel_crtc_prepare,
4120         .commit = intel_crtc_commit,
4121         .load_lut = intel_crtc_load_lut,
4122 };
4123
4124 static const struct drm_crtc_funcs intel_crtc_funcs = {
4125         .cursor_set = intel_crtc_cursor_set,
4126         .cursor_move = intel_crtc_cursor_move,
4127         .gamma_set = intel_crtc_gamma_set,
4128         .set_config = drm_crtc_helper_set_config,
4129         .destroy = intel_crtc_destroy,
4130         .page_flip = intel_crtc_page_flip,
4131 };
4132
4133
4134 static void intel_crtc_init(struct drm_device *dev, int pipe)
4135 {
4136         drm_i915_private_t *dev_priv = dev->dev_private;
4137         struct intel_crtc *intel_crtc;
4138         int i;
4139
4140         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4141         if (intel_crtc == NULL)
4142                 return;
4143
4144         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4145
4146         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4147         intel_crtc->pipe = pipe;
4148         intel_crtc->plane = pipe;
4149         for (i = 0; i < 256; i++) {
4150                 intel_crtc->lut_r[i] = i;
4151                 intel_crtc->lut_g[i] = i;
4152                 intel_crtc->lut_b[i] = i;
4153         }
4154
4155         /* Swap pipes & planes for FBC on pre-965 */
4156         intel_crtc->pipe = pipe;
4157         intel_crtc->plane = pipe;
4158         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4159                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4160                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4161         }
4162
4163         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4164                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4165         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4166         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4167
4168         intel_crtc->cursor_addr = 0;
4169         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4170         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4171
4172         intel_crtc->busy = false;
4173
4174         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4175                     (unsigned long)intel_crtc);
4176 }
4177
4178 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4179                                 struct drm_file *file_priv)
4180 {
4181         drm_i915_private_t *dev_priv = dev->dev_private;
4182         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4183         struct drm_mode_object *drmmode_obj;
4184         struct intel_crtc *crtc;
4185
4186         if (!dev_priv) {
4187                 DRM_ERROR("called with no initialization\n");
4188                 return -EINVAL;
4189         }
4190
4191         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4192                         DRM_MODE_OBJECT_CRTC);
4193
4194         if (!drmmode_obj) {
4195                 DRM_ERROR("no such CRTC id\n");
4196                 return -EINVAL;
4197         }
4198
4199         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4200         pipe_from_crtc_id->pipe = crtc->pipe;
4201
4202         return 0;
4203 }
4204
4205 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4206 {
4207         struct drm_crtc *crtc = NULL;
4208
4209         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4210                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4211                 if (intel_crtc->pipe == pipe)
4212                         break;
4213         }
4214         return crtc;
4215 }
4216
4217 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4218 {
4219         int index_mask = 0;
4220         struct drm_connector *connector;
4221         int entry = 0;
4222
4223         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4224                 struct intel_output *intel_output = to_intel_output(connector);
4225                 if (type_mask & intel_output->clone_mask)
4226                         index_mask |= (1 << entry);
4227                 entry++;
4228         }
4229         return index_mask;
4230 }
4231
4232
4233 static void intel_setup_outputs(struct drm_device *dev)
4234 {
4235         struct drm_i915_private *dev_priv = dev->dev_private;
4236         struct drm_connector *connector;
4237
4238         intel_crt_init(dev);
4239
4240         /* Set up integrated LVDS */
4241         if (IS_MOBILE(dev) && !IS_I830(dev))
4242                 intel_lvds_init(dev);
4243
4244         if (IS_IRONLAKE(dev)) {
4245                 int found;
4246
4247                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4248                         intel_dp_init(dev, DP_A);
4249
4250                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4251                         /* check SDVOB */
4252                         /* found = intel_sdvo_init(dev, HDMIB); */
4253                         found = 0;
4254                         if (!found)
4255                                 intel_hdmi_init(dev, HDMIB);
4256                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4257                                 intel_dp_init(dev, PCH_DP_B);
4258                 }
4259
4260                 if (I915_READ(HDMIC) & PORT_DETECTED)
4261                         intel_hdmi_init(dev, HDMIC);
4262
4263                 if (I915_READ(HDMID) & PORT_DETECTED)
4264                         intel_hdmi_init(dev, HDMID);
4265
4266                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4267                         intel_dp_init(dev, PCH_DP_C);
4268
4269                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4270                         intel_dp_init(dev, PCH_DP_D);
4271
4272         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4273                 bool found = false;
4274
4275                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4276                         DRM_DEBUG_KMS("probing SDVOB\n");
4277                         found = intel_sdvo_init(dev, SDVOB);
4278                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4279                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4280                                 intel_hdmi_init(dev, SDVOB);
4281                         }
4282
4283                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4284                                 DRM_DEBUG_KMS("probing DP_B\n");
4285                                 intel_dp_init(dev, DP_B);
4286                         }
4287                 }
4288
4289                 /* Before G4X SDVOC doesn't have its own detect register */
4290
4291                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4292                         DRM_DEBUG_KMS("probing SDVOC\n");
4293                         found = intel_sdvo_init(dev, SDVOC);
4294                 }
4295
4296                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4297
4298                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4299                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4300                                 intel_hdmi_init(dev, SDVOC);
4301                         }
4302                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4303                                 DRM_DEBUG_KMS("probing DP_C\n");
4304                                 intel_dp_init(dev, DP_C);
4305                         }
4306                 }
4307
4308                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4309                     (I915_READ(DP_D) & DP_DETECTED)) {
4310                         DRM_DEBUG_KMS("probing DP_D\n");
4311                         intel_dp_init(dev, DP_D);
4312                 }
4313         } else if (IS_I8XX(dev))
4314                 intel_dvo_init(dev);
4315
4316         if (SUPPORTS_TV(dev))
4317                 intel_tv_init(dev);
4318
4319         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4320                 struct intel_output *intel_output = to_intel_output(connector);
4321                 struct drm_encoder *encoder = &intel_output->enc;
4322
4323                 encoder->possible_crtcs = intel_output->crtc_mask;
4324                 encoder->possible_clones = intel_connector_clones(dev,
4325                                                 intel_output->clone_mask);
4326         }
4327 }
4328
4329 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4330 {
4331         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4332         struct drm_device *dev = fb->dev;
4333
4334         if (fb->fbdev)
4335                 intelfb_remove(dev, fb);
4336
4337         drm_framebuffer_cleanup(fb);
4338         mutex_lock(&dev->struct_mutex);
4339         drm_gem_object_unreference(intel_fb->obj);
4340         mutex_unlock(&dev->struct_mutex);
4341
4342         kfree(intel_fb);
4343 }
4344
4345 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4346                                                 struct drm_file *file_priv,
4347                                                 unsigned int *handle)
4348 {
4349         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4350         struct drm_gem_object *object = intel_fb->obj;
4351
4352         return drm_gem_handle_create(file_priv, object, handle);
4353 }
4354
4355 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4356         .destroy = intel_user_framebuffer_destroy,
4357         .create_handle = intel_user_framebuffer_create_handle,
4358 };
4359
4360 int intel_framebuffer_create(struct drm_device *dev,
4361                              struct drm_mode_fb_cmd *mode_cmd,
4362                              struct drm_framebuffer **fb,
4363                              struct drm_gem_object *obj)
4364 {
4365         struct intel_framebuffer *intel_fb;
4366         int ret;
4367
4368         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4369         if (!intel_fb)
4370                 return -ENOMEM;
4371
4372         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4373         if (ret) {
4374                 DRM_ERROR("framebuffer init failed %d\n", ret);
4375                 return ret;
4376         }
4377
4378         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4379
4380         intel_fb->obj = obj;
4381
4382         *fb = &intel_fb->base;
4383
4384         return 0;
4385 }
4386
4387
4388 static struct drm_framebuffer *
4389 intel_user_framebuffer_create(struct drm_device *dev,
4390                               struct drm_file *filp,
4391                               struct drm_mode_fb_cmd *mode_cmd)
4392 {
4393         struct drm_gem_object *obj;
4394         struct drm_framebuffer *fb;
4395         int ret;
4396
4397         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4398         if (!obj)
4399                 return NULL;
4400
4401         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4402         if (ret) {
4403                 mutex_lock(&dev->struct_mutex);
4404                 drm_gem_object_unreference(obj);
4405                 mutex_unlock(&dev->struct_mutex);
4406                 return NULL;
4407         }
4408
4409         return fb;
4410 }
4411
4412 static const struct drm_mode_config_funcs intel_mode_funcs = {
4413         .fb_create = intel_user_framebuffer_create,
4414         .fb_changed = intelfb_probe,
4415 };
4416
4417 void intel_init_clock_gating(struct drm_device *dev)
4418 {
4419         struct drm_i915_private *dev_priv = dev->dev_private;
4420
4421         /*
4422          * Disable clock gating reported to work incorrectly according to the
4423          * specs, but enable as much else as we can.
4424          */
4425         if (IS_IRONLAKE(dev)) {
4426                 return;
4427         } else if (IS_G4X(dev)) {
4428                 uint32_t dspclk_gate;
4429                 I915_WRITE(RENCLK_GATE_D1, 0);
4430                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4431                        GS_UNIT_CLOCK_GATE_DISABLE |
4432                        CL_UNIT_CLOCK_GATE_DISABLE);
4433                 I915_WRITE(RAMCLK_GATE_D, 0);
4434                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4435                         OVRUNIT_CLOCK_GATE_DISABLE |
4436                         OVCUNIT_CLOCK_GATE_DISABLE;
4437                 if (IS_GM45(dev))
4438                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4439                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4440         } else if (IS_I965GM(dev)) {
4441                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4442                 I915_WRITE(RENCLK_GATE_D2, 0);
4443                 I915_WRITE(DSPCLK_GATE_D, 0);
4444                 I915_WRITE(RAMCLK_GATE_D, 0);
4445                 I915_WRITE16(DEUC, 0);
4446         } else if (IS_I965G(dev)) {
4447                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4448                        I965_RCC_CLOCK_GATE_DISABLE |
4449                        I965_RCPB_CLOCK_GATE_DISABLE |
4450                        I965_ISC_CLOCK_GATE_DISABLE |
4451                        I965_FBC_CLOCK_GATE_DISABLE);
4452                 I915_WRITE(RENCLK_GATE_D2, 0);
4453         } else if (IS_I9XX(dev)) {
4454                 u32 dstate = I915_READ(D_STATE);
4455
4456                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4457                         DSTATE_DOT_CLOCK_GATING;
4458                 I915_WRITE(D_STATE, dstate);
4459         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4460                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4461         } else if (IS_I830(dev)) {
4462                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4463         }
4464
4465         /*
4466          * GPU can automatically power down the render unit if given a page
4467          * to save state.
4468          */
4469         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4470                 struct drm_gem_object *pwrctx;
4471                 struct drm_i915_gem_object *obj_priv;
4472                 int ret;
4473
4474                 if (dev_priv->pwrctx) {
4475                         obj_priv = dev_priv->pwrctx->driver_private;
4476                 } else {
4477                         pwrctx = drm_gem_object_alloc(dev, 4096);
4478                         if (!pwrctx) {
4479                                 DRM_DEBUG("failed to alloc power context, "
4480                                           "RC6 disabled\n");
4481                                 goto out;
4482                         }
4483
4484                         ret = i915_gem_object_pin(pwrctx, 4096);
4485                         if (ret) {
4486                                 DRM_ERROR("failed to pin power context: %d\n",
4487                                           ret);
4488                                 drm_gem_object_unreference(pwrctx);
4489                                 goto out;
4490                         }
4491
4492                         i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4493
4494                         dev_priv->pwrctx = pwrctx;
4495                         obj_priv = pwrctx->driver_private;
4496                 }
4497
4498                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4499                 I915_WRITE(MCHBAR_RENDER_STANDBY,
4500                            I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4501         }
4502
4503 out:
4504         return;
4505 }
4506
4507 /* Set up chip specific display functions */
4508 static void intel_init_display(struct drm_device *dev)
4509 {
4510         struct drm_i915_private *dev_priv = dev->dev_private;
4511
4512         /* We always want a DPMS function */
4513         if (IS_IRONLAKE(dev))
4514                 dev_priv->display.dpms = ironlake_crtc_dpms;
4515         else
4516                 dev_priv->display.dpms = i9xx_crtc_dpms;
4517
4518         /* Only mobile has FBC, leave pointers NULL for other chips */
4519         if (IS_MOBILE(dev)) {
4520                 if (IS_GM45(dev)) {
4521                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4522                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4523                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4524                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4525                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4526                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4527                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4528                 }
4529                 /* 855GM needs testing */
4530         }
4531
4532         /* Returns the core display clock speed */
4533         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4534                 dev_priv->display.get_display_clock_speed =
4535                         i945_get_display_clock_speed;
4536         else if (IS_I915G(dev))
4537                 dev_priv->display.get_display_clock_speed =
4538                         i915_get_display_clock_speed;
4539         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4540                 dev_priv->display.get_display_clock_speed =
4541                         i9xx_misc_get_display_clock_speed;
4542         else if (IS_I915GM(dev))
4543                 dev_priv->display.get_display_clock_speed =
4544                         i915gm_get_display_clock_speed;
4545         else if (IS_I865G(dev))
4546                 dev_priv->display.get_display_clock_speed =
4547                         i865_get_display_clock_speed;
4548         else if (IS_I85X(dev))
4549                 dev_priv->display.get_display_clock_speed =
4550                         i855_get_display_clock_speed;
4551         else /* 852, 830 */
4552                 dev_priv->display.get_display_clock_speed =
4553                         i830_get_display_clock_speed;
4554
4555         /* For FIFO watermark updates */
4556         if (IS_IRONLAKE(dev))
4557                 dev_priv->display.update_wm = NULL;
4558         else if (IS_G4X(dev))
4559                 dev_priv->display.update_wm = g4x_update_wm;
4560         else if (IS_I965G(dev))
4561                 dev_priv->display.update_wm = i965_update_wm;
4562         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4563                 dev_priv->display.update_wm = i9xx_update_wm;
4564                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4565         } else {
4566                 if (IS_I85X(dev))
4567                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4568                 else if (IS_845G(dev))
4569                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4570                 else
4571                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4572                 dev_priv->display.update_wm = i830_update_wm;
4573         }
4574 }
4575
4576 void intel_modeset_init(struct drm_device *dev)
4577 {
4578         struct drm_i915_private *dev_priv = dev->dev_private;
4579         int num_pipe;
4580         int i;
4581
4582         drm_mode_config_init(dev);
4583
4584         dev->mode_config.min_width = 0;
4585         dev->mode_config.min_height = 0;
4586
4587         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4588
4589         intel_init_display(dev);
4590
4591         if (IS_I965G(dev)) {
4592                 dev->mode_config.max_width = 8192;
4593                 dev->mode_config.max_height = 8192;
4594         } else if (IS_I9XX(dev)) {
4595                 dev->mode_config.max_width = 4096;
4596                 dev->mode_config.max_height = 4096;
4597         } else {
4598                 dev->mode_config.max_width = 2048;
4599                 dev->mode_config.max_height = 2048;
4600         }
4601
4602         /* set memory base */
4603         if (IS_I9XX(dev))
4604                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4605         else
4606                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4607
4608         if (IS_MOBILE(dev) || IS_I9XX(dev))
4609                 num_pipe = 2;
4610         else
4611                 num_pipe = 1;
4612         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4613                   num_pipe, num_pipe > 1 ? "s" : "");
4614
4615         if (IS_I85X(dev))
4616                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4617         else if (IS_I9XX(dev) || IS_G4X(dev))
4618                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4619
4620         for (i = 0; i < num_pipe; i++) {
4621                 intel_crtc_init(dev, i);
4622         }
4623
4624         intel_setup_outputs(dev);
4625
4626         intel_init_clock_gating(dev);
4627
4628         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4629         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4630                     (unsigned long)dev);
4631
4632         intel_setup_overlay(dev);
4633
4634         if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4635                                                         dev_priv->fsb_freq,
4636                                                         dev_priv->mem_freq))
4637                 DRM_INFO("failed to find known CxSR latency "
4638                          "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4639                          dev_priv->fsb_freq, dev_priv->mem_freq);
4640 }
4641
4642 void intel_modeset_cleanup(struct drm_device *dev)
4643 {
4644         struct drm_i915_private *dev_priv = dev->dev_private;
4645         struct drm_crtc *crtc;
4646         struct intel_crtc *intel_crtc;
4647
4648         mutex_lock(&dev->struct_mutex);
4649
4650         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4651                 /* Skip inactive CRTCs */
4652                 if (!crtc->fb)
4653                         continue;
4654
4655                 intel_crtc = to_intel_crtc(crtc);
4656                 intel_increase_pllclock(crtc, false);
4657                 del_timer_sync(&intel_crtc->idle_timer);
4658         }
4659
4660         del_timer_sync(&dev_priv->idle_timer);
4661
4662         if (dev_priv->display.disable_fbc)
4663                 dev_priv->display.disable_fbc(dev);
4664
4665         if (dev_priv->pwrctx) {
4666                 struct drm_i915_gem_object *obj_priv;
4667
4668                 obj_priv = dev_priv->pwrctx->driver_private;
4669                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4670                 I915_READ(PWRCTXA);
4671                 i915_gem_object_unpin(dev_priv->pwrctx);
4672                 drm_gem_object_unreference(dev_priv->pwrctx);
4673         }
4674
4675         mutex_unlock(&dev->struct_mutex);
4676
4677         drm_mode_config_cleanup(dev);
4678 }
4679
4680
4681 /* current intel driver doesn't take advantage of encoders
4682    always give back the encoder for the connector
4683 */
4684 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4685 {
4686         struct intel_output *intel_output = to_intel_output(connector);
4687
4688         return &intel_output->enc;
4689 }
4690
4691 /*
4692  * set vga decode state - true == enable VGA decode
4693  */
4694 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4695 {
4696         struct drm_i915_private *dev_priv = dev->dev_private;
4697         u16 gmch_ctrl;
4698
4699         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4700         if (state)
4701                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4702         else
4703                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4704         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4705         return 0;
4706 }