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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "drm_dp_helper.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73 };
  74
  75 #define I8XX_DOT_MIN              25000
  76 #define I8XX_DOT_MAX             350000
  77 #define I8XX_VCO_MIN             930000
  78 #define I8XX_VCO_MAX            1400000
  79 #define I8XX_N_MIN                    3
  80 #define I8XX_N_MAX                   16
  81 #define I8XX_M_MIN                   96
  82 #define I8XX_M_MAX                  140
  83 #define I8XX_M1_MIN                  18
  84 #define I8XX_M1_MAX                  26
  85 #define I8XX_M2_MIN                   6
  86 #define I8XX_M2_MAX                  16
  87 #define I8XX_P_MIN                    4
  88 #define I8XX_P_MAX                  128
  89 #define I8XX_P1_MIN                   2
  90 #define I8XX_P1_MAX                  33
  91 #define I8XX_P1_LVDS_MIN              1
  92 #define I8XX_P1_LVDS_MAX              6
  93 #define I8XX_P2_SLOW                  4
  94 #define I8XX_P2_FAST                  2
  95 #define I8XX_P2_LVDS_SLOW             14
  96 #define I8XX_P2_LVDS_FAST             7
  97 #define I8XX_P2_SLOW_LIMIT       165000
  98
  99 #define I9XX_DOT_MIN              20000
 100 #define I9XX_DOT_MAX             400000
 101 #define I9XX_VCO_MIN            1400000
 102 #define I9XX_VCO_MAX            2800000
 103 #define PINEVIEW_VCO_MIN                1700000
 104 #define PINEVIEW_VCO_MAX                3500000
 105 #define I9XX_N_MIN                    1
 106 #define I9XX_N_MAX                    6
 107 /* Pineview's Ncounter is a ring counter */
 108 #define PINEVIEW_N_MIN                3
 109 #define PINEVIEW_N_MAX                6
 110 #define I9XX_M_MIN                   70
 111 #define I9XX_M_MAX                  120
 112 #define PINEVIEW_M_MIN                2
 113 #define PINEVIEW_M_MAX              256
 114 #define I9XX_M1_MIN                  10
 115 #define I9XX_M1_MAX                  22
 116 #define I9XX_M2_MIN                   5
 117 #define I9XX_M2_MAX                   9
 118 /* Pineview M1 is reserved, and must be 0 */
 119 #define PINEVIEW_M1_MIN               0
 120 #define PINEVIEW_M1_MAX               0
 121 #define PINEVIEW_M2_MIN               0
 122 #define PINEVIEW_M2_MAX               254
 123 #define I9XX_P_SDVO_DAC_MIN           5
 124 #define I9XX_P_SDVO_DAC_MAX          80
 125 #define I9XX_P_LVDS_MIN               7
 126 #define I9XX_P_LVDS_MAX              98
 127 #define PINEVIEW_P_LVDS_MIN                   7
 128 #define PINEVIEW_P_LVDS_MAX                  112
 129 #define I9XX_P1_MIN                   1
 130 #define I9XX_P1_MAX                   8
 131 #define I9XX_P2_SDVO_DAC_SLOW                10
 132 #define I9XX_P2_SDVO_DAC_FAST                 5
 133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 134 #define I9XX_P2_LVDS_SLOW                    14
 135 #define I9XX_P2_LVDS_FAST                     7
 136 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 137
 138 /*The parameter is for SDVO on G4x platform*/
 139 #define G4X_DOT_SDVO_MIN           25000
 140 #define G4X_DOT_SDVO_MAX           270000
 141 #define G4X_VCO_MIN                1750000
 142 #define G4X_VCO_MAX                3500000
 143 #define G4X_N_SDVO_MIN             1
 144 #define G4X_N_SDVO_MAX             4
 145 #define G4X_M_SDVO_MIN             104
 146 #define G4X_M_SDVO_MAX             138
 147 #define G4X_M1_SDVO_MIN            17
 148 #define G4X_M1_SDVO_MAX            23
 149 #define G4X_M2_SDVO_MIN            5
 150 #define G4X_M2_SDVO_MAX            11
 151 #define G4X_P_SDVO_MIN             10
 152 #define G4X_P_SDVO_MAX             30
 153 #define G4X_P1_SDVO_MIN            1
 154 #define G4X_P1_SDVO_MAX            3
 155 #define G4X_P2_SDVO_SLOW           10
 156 #define G4X_P2_SDVO_FAST           10
 157 #define G4X_P2_SDVO_LIMIT          270000
 158
 159 /*The parameter is for HDMI_DAC on G4x platform*/
 160 #define G4X_DOT_HDMI_DAC_MIN           22000
 161 #define G4X_DOT_HDMI_DAC_MAX           400000
 162 #define G4X_N_HDMI_DAC_MIN             1
 163 #define G4X_N_HDMI_DAC_MAX             4
 164 #define G4X_M_HDMI_DAC_MIN             104
 165 #define G4X_M_HDMI_DAC_MAX             138
 166 #define G4X_M1_HDMI_DAC_MIN            16
 167 #define G4X_M1_HDMI_DAC_MAX            23
 168 #define G4X_M2_HDMI_DAC_MIN            5
 169 #define G4X_M2_HDMI_DAC_MAX            11
 170 #define G4X_P_HDMI_DAC_MIN             5
 171 #define G4X_P_HDMI_DAC_MAX             80
 172 #define G4X_P1_HDMI_DAC_MIN            1
 173 #define G4X_P1_HDMI_DAC_MAX            8
 174 #define G4X_P2_HDMI_DAC_SLOW           10
 175 #define G4X_P2_HDMI_DAC_FAST           5
 176 #define G4X_P2_HDMI_DAC_LIMIT          165000
 177
 178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 196
 197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 215
 216 /*The parameter is for DISPLAY PORT on G4x platform*/
 217 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 218 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 219 #define G4X_N_DISPLAY_PORT_MIN             1
 220 #define G4X_N_DISPLAY_PORT_MAX             2
 221 #define G4X_M_DISPLAY_PORT_MIN             97
 222 #define G4X_M_DISPLAY_PORT_MAX             108
 223 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 224 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 225 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 226 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 227 #define G4X_P_DISPLAY_PORT_MIN             10
 228 #define G4X_P_DISPLAY_PORT_MAX             20
 229 #define G4X_P1_DISPLAY_PORT_MIN            1
 230 #define G4X_P1_DISPLAY_PORT_MAX            2
 231 #define G4X_P2_DISPLAY_PORT_SLOW           10
 232 #define G4X_P2_DISPLAY_PORT_FAST           10
 233 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 234
 235 /* Ironlake */
 236 /* as we calculate clock using (register_value + 2) for
 237    N/M1/M2, so here the range value for them is (actual_value-2).
 238  */
 239 #define IRONLAKE_DOT_MIN         25000
 240 #define IRONLAKE_DOT_MAX         350000
 241 #define IRONLAKE_VCO_MIN         1760000
 242 #define IRONLAKE_VCO_MAX         3510000
 243 #define IRONLAKE_N_MIN           1
 244 #define IRONLAKE_N_MAX           6
 245 #define IRONLAKE_M_MIN           79
 246 #define IRONLAKE_M_MAX           127
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P_SDVO_DAC_MIN  5
 252 #define IRONLAKE_P_SDVO_DAC_MAX  80
 253 #define IRONLAKE_P_LVDS_MIN      28
 254 #define IRONLAKE_P_LVDS_MAX      112
 255 #define IRONLAKE_P1_MIN          1
 256 #define IRONLAKE_P1_MAX          8
 257 #define IRONLAKE_P2_SDVO_DAC_SLOW 10
 258 #define IRONLAKE_P2_SDVO_DAC_FAST 5
 259 #define IRONLAKE_P2_LVDS_SLOW    14 /* single channel */
 260 #define IRONLAKE_P2_LVDS_FAST    7  /* double channel */
 261 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 262
 263 #define IRONLAKE_P_DISPLAY_PORT_MIN     10
 264 #define IRONLAKE_P_DISPLAY_PORT_MAX     20
 265 #define IRONLAKE_P2_DISPLAY_PORT_FAST   10
 266 #define IRONLAKE_P2_DISPLAY_PORT_SLOW   10
 267 #define IRONLAKE_P2_DISPLAY_PORT_LIMIT  0
 268 #define IRONLAKE_P1_DISPLAY_PORT_MIN    1
 269 #define IRONLAKE_P1_DISPLAY_PORT_MAX    2
 270
 271 static bool
 272 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                     int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                            int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297 };
 298
 299 static const intel_limit_t intel_limits_i8xx_lvds = {
 300         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 301         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 302         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 303         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 304         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 305         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 306         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 307         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 308         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 309                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 310         .find_pll = intel_find_best_PLL,
 311 };
 312
 313 static const intel_limit_t intel_limits_i9xx_sdvo = {
 314         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 315         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 316         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 317         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 318         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 319         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 320         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 321         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 322         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 323                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 324         .find_pll = intel_find_best_PLL,
 325 };
 326
 327 static const intel_limit_t intel_limits_i9xx_lvds = {
 328         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 329         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 330         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 331         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 332         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 333         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 334         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 335         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 336         /* The single-channel range is 25-112Mhz, and dual-channel
 337          * is 80-224Mhz.  Prefer single channel as much as possible.
 338          */
 339         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 340                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 341         .find_pll = intel_find_best_PLL,
 342 };
 343
 344     /* below parameter and function is for G4X Chipset Family*/
 345 static const intel_limit_t intel_limits_g4x_sdvo = {
 346         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 347         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 348         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 349         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 350         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 351         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 352         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 353         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 354         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 355                  .p2_slow = G4X_P2_SDVO_SLOW,
 356                  .p2_fast = G4X_P2_SDVO_FAST
 357         },
 358         .find_pll = intel_g4x_find_best_PLL,
 359 };
 360
 361 static const intel_limit_t intel_limits_g4x_hdmi = {
 362         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 363         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 364         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 365         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 366         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 367         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 368         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 369         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 370         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 371                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 372                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 373         },
 374         .find_pll = intel_g4x_find_best_PLL,
 375 };
 376
 377 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 378         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 379                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 380         .vco = { .min = G4X_VCO_MIN,
 381                  .max = G4X_VCO_MAX },
 382         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 383                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 384         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 386         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 387                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 388         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 390         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 392         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 394         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 395                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 396                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 397         },
 398         .find_pll = intel_g4x_find_best_PLL,
 399 };
 400
 401 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 402         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 403                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 404         .vco = { .min = G4X_VCO_MIN,
 405                  .max = G4X_VCO_MAX },
 406         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 407                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 408         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 409                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 410         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 411                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 412         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 413                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 414         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 415                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 416         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 417                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 418         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 419                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 420                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 421         },
 422         .find_pll = intel_g4x_find_best_PLL,
 423 };
 424
 425 static const intel_limit_t intel_limits_g4x_display_port = {
 426         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 427                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 428         .vco = { .min = G4X_VCO_MIN,
 429                  .max = G4X_VCO_MAX},
 430         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 431                  .max = G4X_N_DISPLAY_PORT_MAX },
 432         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 433                  .max = G4X_M_DISPLAY_PORT_MAX },
 434         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 435                  .max = G4X_M1_DISPLAY_PORT_MAX },
 436         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 437                  .max = G4X_M2_DISPLAY_PORT_MAX },
 438         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 439                  .max = G4X_P_DISPLAY_PORT_MAX },
 440         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 441                  .max = G4X_P1_DISPLAY_PORT_MAX},
 442         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 443                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 444                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 445         .find_pll = intel_find_pll_g4x_dp,
 446 };
 447
 448 static const intel_limit_t intel_limits_pineview_sdvo = {
 449         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 450         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 451         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 452         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 453         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 454         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 455         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 456         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 457         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 458                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 459         .find_pll = intel_find_best_PLL,
 460 };
 461
 462 static const intel_limit_t intel_limits_pineview_lvds = {
 463         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 464         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 465         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 466         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 467         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 468         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 469         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 470         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 471         /* Pineview only supports single-channel mode. */
 472         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 473                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 474         .find_pll = intel_find_best_PLL,
 475 };
 476
 477 static const intel_limit_t intel_limits_ironlake_sdvo = {
 478         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 479         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 480         .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
 481         .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
 482         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 483         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 484         .p   = { .min = IRONLAKE_P_SDVO_DAC_MIN,   .max = IRONLAKE_P_SDVO_DAC_MAX },
 485         .p1  = { .min = IRONLAKE_P1_MIN,           .max = IRONLAKE_P1_MAX },
 486         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 487                  .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW,
 488                  .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST },
 489         .find_pll = intel_g4x_find_best_PLL,
 490 };
 491
 492 static const intel_limit_t intel_limits_ironlake_lvds = {
 493         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 494         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 495         .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
 496         .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
 497         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 498         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 499         .p   = { .min = IRONLAKE_P_LVDS_MIN,       .max = IRONLAKE_P_LVDS_MAX },
 500         .p1  = { .min = IRONLAKE_P1_MIN,           .max = IRONLAKE_P1_MAX },
 501         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 502                  .p2_slow = IRONLAKE_P2_LVDS_SLOW,
 503                  .p2_fast = IRONLAKE_P2_LVDS_FAST },
 504         .find_pll = intel_g4x_find_best_PLL,
 505 };
 506
 507 static const intel_limit_t intel_limits_ironlake_display_port = {
 508         .dot = { .min = IRONLAKE_DOT_MIN,
 509                  .max = IRONLAKE_DOT_MAX },
 510         .vco = { .min = IRONLAKE_VCO_MIN,
 511                  .max = IRONLAKE_VCO_MAX},
 512         .n   = { .min = IRONLAKE_N_MIN,
 513                  .max = IRONLAKE_N_MAX },
 514         .m   = { .min = IRONLAKE_M_MIN,
 515                  .max = IRONLAKE_M_MAX },
 516         .m1  = { .min = IRONLAKE_M1_MIN,
 517                  .max = IRONLAKE_M1_MAX },
 518         .m2  = { .min = IRONLAKE_M2_MIN,
 519                  .max = IRONLAKE_M2_MAX },
 520         .p   = { .min = IRONLAKE_P_DISPLAY_PORT_MIN,
 521                  .max = IRONLAKE_P_DISPLAY_PORT_MAX },
 522         .p1  = { .min = IRONLAKE_P1_DISPLAY_PORT_MIN,
 523                  .max = IRONLAKE_P1_DISPLAY_PORT_MAX},
 524         .p2  = { .dot_limit = IRONLAKE_P2_DISPLAY_PORT_LIMIT,
 525                  .p2_slow = IRONLAKE_P2_DISPLAY_PORT_SLOW,
 526                  .p2_fast = IRONLAKE_P2_DISPLAY_PORT_FAST },
 527         .find_pll = intel_find_pll_ironlake_dp,
 528 };
 529
 530 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 531 {
 532         const intel_limit_t *limit;
 533         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 534                 limit = &intel_limits_ironlake_lvds;
 535         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 536                         HAS_eDP)
 537                 limit = &intel_limits_ironlake_display_port;
 538         else
 539                 limit = &intel_limits_ironlake_sdvo;
 540
 541         return limit;
 542 }
 543
 544 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 545 {
 546         struct drm_device *dev = crtc->dev;
 547         struct drm_i915_private *dev_priv = dev->dev_private;
 548         const intel_limit_t *limit;
 549
 550         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 551                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 552                     LVDS_CLKB_POWER_UP)
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_dual_channel_lvds;
 555                 else
 556                         /* LVDS with dual channel */
 557                         limit = &intel_limits_g4x_single_channel_lvds;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 559                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 560                 limit = &intel_limits_g4x_hdmi;
 561         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 562                 limit = &intel_limits_g4x_sdvo;
 563         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 564                 limit = &intel_limits_g4x_display_port;
 565         } else /* The option is for other outputs */
 566                 limit = &intel_limits_i9xx_sdvo;
 567
 568         return limit;
 569 }
 570
 571 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 572 {
 573         struct drm_device *dev = crtc->dev;
 574         const intel_limit_t *limit;
 575
 576         if (IS_IRONLAKE(dev))
 577                 limit = intel_ironlake_limit(crtc);
 578         else if (IS_G4X(dev)) {
 579                 limit = intel_g4x_limit(crtc);
 580         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 581                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 582                         limit = &intel_limits_i9xx_lvds;
 583                 else
 584                         limit = &intel_limits_i9xx_sdvo;
 585         } else if (IS_PINEVIEW(dev)) {
 586                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 587                         limit = &intel_limits_pineview_lvds;
 588                 else
 589                         limit = &intel_limits_pineview_sdvo;
 590         } else {
 591                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 592                         limit = &intel_limits_i8xx_lvds;
 593                 else
 594                         limit = &intel_limits_i8xx_dvo;
 595         }
 596         return limit;
 597 }
 598
 599 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 600 static void pineview_clock(int refclk, intel_clock_t *clock)
 601 {
 602         clock->m = clock->m2 + 2;
 603         clock->p = clock->p1 * clock->p2;
 604         clock->vco = refclk * clock->m / clock->n;
 605         clock->dot = clock->vco / clock->p;
 606 }
 607
 608 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 609 {
 610         if (IS_PINEVIEW(dev)) {
 611                 pineview_clock(refclk, clock);
 612                 return;
 613         }
 614         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 615         clock->p = clock->p1 * clock->p2;
 616         clock->vco = refclk * clock->m / (clock->n + 2);
 617         clock->dot = clock->vco / clock->p;
 618 }
 619
 620 /**
 621  * Returns whether any output on the specified pipe is of the specified type
 622  */
 623 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 624 {
 625     struct drm_device *dev = crtc->dev;
 626     struct drm_mode_config *mode_config = &dev->mode_config;
 627     struct drm_connector *l_entry;
 628
 629     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 630             if (l_entry->encoder &&
 631                 l_entry->encoder->crtc == crtc) {
 632                     struct intel_output *intel_output = to_intel_output(l_entry);
 633                     if (intel_output->type == type)
 634                             return true;
 635             }
 636     }
 637     return false;
 638 }
 639
 640 struct drm_connector *
 641 intel_pipe_get_output (struct drm_crtc *crtc)
 642 {
 643     struct drm_device *dev = crtc->dev;
 644     struct drm_mode_config *mode_config = &dev->mode_config;
 645     struct drm_connector *l_entry, *ret = NULL;
 646
 647     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 648             if (l_entry->encoder &&
 649                 l_entry->encoder->crtc == crtc) {
 650                     ret = l_entry;
 651                     break;
 652             }
 653     }
 654     return ret;
 655 }
 656
 657 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 658 /**
 659  * Returns whether the given set of divisors are valid for a given refclk with
 660  * the given connectors.
 661  */
 662
 663 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 664 {
 665         const intel_limit_t *limit = intel_limit (crtc);
 666         struct drm_device *dev = crtc->dev;
 667
 668         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 669                 INTELPllInvalid ("p1 out of range\n");
 670         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 671                 INTELPllInvalid ("p out of range\n");
 672         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 673                 INTELPllInvalid ("m2 out of range\n");
 674         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 675                 INTELPllInvalid ("m1 out of range\n");
 676         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 677                 INTELPllInvalid ("m1 <= m2\n");
 678         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 679                 INTELPllInvalid ("m out of range\n");
 680         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 681                 INTELPllInvalid ("n out of range\n");
 682         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 683                 INTELPllInvalid ("vco out of range\n");
 684         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 685          * connector, etc., rather than just a single range.
 686          */
 687         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 688                 INTELPllInvalid ("dot out of range\n");
 689
 690         return true;
 691 }
 692
 693 static bool
 694 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 695                     int target, int refclk, intel_clock_t *best_clock)
 696
 697 {
 698         struct drm_device *dev = crtc->dev;
 699         struct drm_i915_private *dev_priv = dev->dev_private;
 700         intel_clock_t clock;
 701         int err = target;
 702
 703         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 704             (I915_READ(LVDS)) != 0) {
 705                 /*
 706                  * For LVDS, if the panel is on, just rely on its current
 707                  * settings for dual-channel.  We haven't figured out how to
 708                  * reliably set up different single/dual channel state, if we
 709                  * even can.
 710                  */
 711                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 712                     LVDS_CLKB_POWER_UP)
 713                         clock.p2 = limit->p2.p2_fast;
 714                 else
 715                         clock.p2 = limit->p2.p2_slow;
 716         } else {
 717                 if (target < limit->p2.dot_limit)
 718                         clock.p2 = limit->p2.p2_slow;
 719                 else
 720                         clock.p2 = limit->p2.p2_fast;
 721         }
 722
 723         memset (best_clock, 0, sizeof (*best_clock));
 724
 725         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 726              clock.m1++) {
 727                 for (clock.m2 = limit->m2.min;
 728                      clock.m2 <= limit->m2.max; clock.m2++) {
 729                         /* m1 is always 0 in Pineview */
 730                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 731                                 break;
 732                         for (clock.n = limit->n.min;
 733                              clock.n <= limit->n.max; clock.n++) {
 734                                 for (clock.p1 = limit->p1.min;
 735                                         clock.p1 <= limit->p1.max; clock.p1++) {
 736                                         int this_err;
 737
 738                                         intel_clock(dev, refclk, &clock);
 739
 740                                         if (!intel_PLL_is_valid(crtc, &clock))
 741                                                 continue;
 742
 743                                         this_err = abs(clock.dot - target);
 744                                         if (this_err < err) {
 745                                                 *best_clock = clock;
 746                                                 err = this_err;
 747                                         }
 748                                 }
 749                         }
 750                 }
 751         }
 752
 753         return (err != target);
 754 }
 755
 756 static bool
 757 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 758                         int target, int refclk, intel_clock_t *best_clock)
 759 {
 760         struct drm_device *dev = crtc->dev;
 761         struct drm_i915_private *dev_priv = dev->dev_private;
 762         intel_clock_t clock;
 763         int max_n;
 764         bool found;
 765         /* approximately equals target * 0.00488 */
 766         int err_most = (target >> 8) + (target >> 10);
 767         found = false;
 768
 769         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 770                 int lvds_reg;
 771
 772                 if (IS_IRONLAKE(dev))
 773                         lvds_reg = PCH_LVDS;
 774                 else
 775                         lvds_reg = LVDS;
 776                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 777                     LVDS_CLKB_POWER_UP)
 778                         clock.p2 = limit->p2.p2_fast;
 779                 else
 780                         clock.p2 = limit->p2.p2_slow;
 781         } else {
 782                 if (target < limit->p2.dot_limit)
 783                         clock.p2 = limit->p2.p2_slow;
 784                 else
 785                         clock.p2 = limit->p2.p2_fast;
 786         }
 787
 788         memset(best_clock, 0, sizeof(*best_clock));
 789         max_n = limit->n.max;
 790         /* based on hardware requriment prefer smaller n to precision */
 791         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 792                 /* based on hardware requirment prefere larger m1,m2 */
 793                 for (clock.m1 = limit->m1.max;
 794                      clock.m1 >= limit->m1.min; clock.m1--) {
 795                         for (clock.m2 = limit->m2.max;
 796                              clock.m2 >= limit->m2.min; clock.m2--) {
 797                                 for (clock.p1 = limit->p1.max;
 798                                      clock.p1 >= limit->p1.min; clock.p1--) {
 799                                         int this_err;
 800
 801                                         intel_clock(dev, refclk, &clock);
 802                                         if (!intel_PLL_is_valid(crtc, &clock))
 803                                                 continue;
 804                                         this_err = abs(clock.dot - target) ;
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *best_clock)
 821 {
 822         struct drm_device *dev = crtc->dev;
 823         intel_clock_t clock;
 824
 825         /* return directly when it is eDP */
 826         if (HAS_eDP)
 827                 return true;
 828
 829         if (target < 200000) {
 830                 clock.n = 1;
 831                 clock.p1 = 2;
 832                 clock.p2 = 10;
 833                 clock.m1 = 12;
 834                 clock.m2 = 9;
 835         } else {
 836                 clock.n = 2;
 837                 clock.p1 = 1;
 838                 clock.p2 = 10;
 839                 clock.m1 = 14;
 840                 clock.m2 = 8;
 841         }
 842         intel_clock(dev, refclk, &clock);
 843         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 844         return true;
 845 }
 846
 847 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 848 static bool
 849 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 850                       int target, int refclk, intel_clock_t *best_clock)
 851 {
 852     intel_clock_t clock;
 853     if (target < 200000) {
 854         clock.p1 = 2;
 855         clock.p2 = 10;
 856         clock.n = 2;
 857         clock.m1 = 23;
 858         clock.m2 = 8;
 859     } else {
 860         clock.p1 = 1;
 861         clock.p2 = 10;
 862         clock.n = 1;
 863         clock.m1 = 14;
 864         clock.m2 = 2;
 865     }
 866     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 867     clock.p = (clock.p1 * clock.p2);
 868     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 869     clock.vco = 0;
 870     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 871     return true;
 872 }
 873
 874 void
 875 intel_wait_for_vblank(struct drm_device *dev)
 876 {
 877         /* Wait for 20ms, i.e. one cycle at 50hz. */
 878         msleep(20);
 879 }
 880
 881 /* Parameters have changed, update FBC info */
 882 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 883 {
 884         struct drm_device *dev = crtc->dev;
 885         struct drm_i915_private *dev_priv = dev->dev_private;
 886         struct drm_framebuffer *fb = crtc->fb;
 887         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 888         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 890         int plane, i;
 891         u32 fbc_ctl, fbc_ctl2;
 892
 893         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 894
 895         if (fb->pitch < dev_priv->cfb_pitch)
 896                 dev_priv->cfb_pitch = fb->pitch;
 897
 898         /* FBC_CTL wants 64B units */
 899         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 900         dev_priv->cfb_fence = obj_priv->fence_reg;
 901         dev_priv->cfb_plane = intel_crtc->plane;
 902         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 903
 904         /* Clear old tags */
 905         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 906                 I915_WRITE(FBC_TAG + (i * 4), 0);
 907
 908         /* Set it up... */
 909         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 910         if (obj_priv->tiling_mode != I915_TILING_NONE)
 911                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 912         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 913         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 914
 915         /* enable it... */
 916         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 917         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 918         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 919         if (obj_priv->tiling_mode != I915_TILING_NONE)
 920                 fbc_ctl |= dev_priv->cfb_fence;
 921         I915_WRITE(FBC_CONTROL, fbc_ctl);
 922
 923         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
 924                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
 925 }
 926
 927 void i8xx_disable_fbc(struct drm_device *dev)
 928 {
 929         struct drm_i915_private *dev_priv = dev->dev_private;
 930         u32 fbc_ctl;
 931
 932         if (!I915_HAS_FBC(dev))
 933                 return;
 934
 935         /* Disable compression */
 936         fbc_ctl = I915_READ(FBC_CONTROL);
 937         fbc_ctl &= ~FBC_CTL_EN;
 938         I915_WRITE(FBC_CONTROL, fbc_ctl);
 939
 940         /* Wait for compressing bit to clear */
 941         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
 942                 ; /* nothing */
 943
 944         intel_wait_for_vblank(dev);
 945
 946         DRM_DEBUG_KMS("disabled FBC\n");
 947 }
 948
 949 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
 950 {
 951         struct drm_device *dev = crtc->dev;
 952         struct drm_i915_private *dev_priv = dev->dev_private;
 953
 954         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 955 }
 956
 957 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 958 {
 959         struct drm_device *dev = crtc->dev;
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         struct drm_framebuffer *fb = crtc->fb;
 962         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 963         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 965         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
 966                      DPFC_CTL_PLANEB);
 967         unsigned long stall_watermark = 200;
 968         u32 dpfc_ctl;
 969
 970         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 971         dev_priv->cfb_fence = obj_priv->fence_reg;
 972         dev_priv->cfb_plane = intel_crtc->plane;
 973
 974         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 975         if (obj_priv->tiling_mode != I915_TILING_NONE) {
 976                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
 977                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 978         } else {
 979                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
 980         }
 981
 982         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 983         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 984                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 985                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 986         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 987
 988         /* enable it... */
 989         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 990
 991         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 992 }
 993
 994 void g4x_disable_fbc(struct drm_device *dev)
 995 {
 996         struct drm_i915_private *dev_priv = dev->dev_private;
 997         u32 dpfc_ctl;
 998
 999         /* Disable compression */
1000         dpfc_ctl = I915_READ(DPFC_CONTROL);
1001         dpfc_ctl &= ~DPFC_CTL_EN;
1002         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1003         intel_wait_for_vblank(dev);
1004
1005         DRM_DEBUG_KMS("disabled FBC\n");
1006 }
1007
1008 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1009 {
1010         struct drm_device *dev = crtc->dev;
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012
1013         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1014 }
1015
1016 /**
1017  * intel_update_fbc - enable/disable FBC as needed
1018  * @crtc: CRTC to point the compressor at
1019  * @mode: mode in use
1020  *
1021  * Set up the framebuffer compression hardware at mode set time.  We
1022  * enable it if possible:
1023  *   - plane A only (on pre-965)
1024  *   - no pixel mulitply/line duplication
1025  *   - no alpha buffer discard
1026  *   - no dual wide
1027  *   - framebuffer <= 2048 in width, 1536 in height
1028  *
1029  * We can't assume that any compression will take place (worst case),
1030  * so the compressed buffer has to be the same size as the uncompressed
1031  * one.  It also must reside (along with the line length buffer) in
1032  * stolen memory.
1033  *
1034  * We need to enable/disable FBC on a global basis.
1035  */
1036 static void intel_update_fbc(struct drm_crtc *crtc,
1037                              struct drm_display_mode *mode)
1038 {
1039         struct drm_device *dev = crtc->dev;
1040         struct drm_i915_private *dev_priv = dev->dev_private;
1041         struct drm_framebuffer *fb = crtc->fb;
1042         struct intel_framebuffer *intel_fb;
1043         struct drm_i915_gem_object *obj_priv;
1044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1045         int plane = intel_crtc->plane;
1046
1047         if (!i915_powersave)
1048                 return;
1049
1050         if (!dev_priv->display.fbc_enabled ||
1051             !dev_priv->display.enable_fbc ||
1052             !dev_priv->display.disable_fbc)
1053                 return;
1054
1055         if (!crtc->fb)
1056                 return;
1057
1058         intel_fb = to_intel_framebuffer(fb);
1059         obj_priv = intel_fb->obj->driver_private;
1060
1061         /*
1062          * If FBC is already on, we just have to verify that we can
1063          * keep it that way...
1064          * Need to disable if:
1065          *   - changing FBC params (stride, fence, mode)
1066          *   - new fb is too large to fit in compressed buffer
1067          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1068          */
1069         if (intel_fb->obj->size > dev_priv->cfb_size) {
1070                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1071                                 "compression\n");
1072                 goto out_disable;
1073         }
1074         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1075             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1076                 DRM_DEBUG_KMS("mode incompatible with compression, "
1077                                 "disabling\n");
1078                 goto out_disable;
1079         }
1080         if ((mode->hdisplay > 2048) ||
1081             (mode->vdisplay > 1536)) {
1082                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1083                 goto out_disable;
1084         }
1085         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1086                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1087                 goto out_disable;
1088         }
1089         if (obj_priv->tiling_mode != I915_TILING_X) {
1090                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1091                 goto out_disable;
1092         }
1093
1094         if (dev_priv->display.fbc_enabled(crtc)) {
1095                 /* We can re-enable it in this case, but need to update pitch */
1096                 if (fb->pitch > dev_priv->cfb_pitch)
1097                         dev_priv->display.disable_fbc(dev);
1098                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1099                         dev_priv->display.disable_fbc(dev);
1100                 if (plane != dev_priv->cfb_plane)
1101                         dev_priv->display.disable_fbc(dev);
1102         }
1103
1104         if (!dev_priv->display.fbc_enabled(crtc)) {
1105                 /* Now try to turn it back on if possible */
1106                 dev_priv->display.enable_fbc(crtc, 500);
1107         }
1108
1109         return;
1110
1111 out_disable:
1112         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1113         /* Multiple disables should be harmless */
1114         if (dev_priv->display.fbc_enabled(crtc))
1115                 dev_priv->display.disable_fbc(dev);
1116 }
1117
1118 static int
1119 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1120 {
1121         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1122         u32 alignment;
1123         int ret;
1124
1125         switch (obj_priv->tiling_mode) {
1126         case I915_TILING_NONE:
1127                 alignment = 64 * 1024;
1128                 break;
1129         case I915_TILING_X:
1130                 /* pin() will align the object as required by fence */
1131                 alignment = 0;
1132                 break;
1133         case I915_TILING_Y:
1134                 /* FIXME: Is this true? */
1135                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1136                 return -EINVAL;
1137         default:
1138                 BUG();
1139         }
1140
1141         ret = i915_gem_object_pin(obj, alignment);
1142         if (ret != 0)
1143                 return ret;
1144
1145         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1146          * fence, whereas 965+ only requires a fence if using
1147          * framebuffer compression.  For simplicity, we always install
1148          * a fence as the cost is not that onerous.
1149          */
1150         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1151             obj_priv->tiling_mode != I915_TILING_NONE) {
1152                 ret = i915_gem_object_get_fence_reg(obj);
1153                 if (ret != 0) {
1154                         i915_gem_object_unpin(obj);
1155                         return ret;
1156                 }
1157         }
1158
1159         return 0;
1160 }
1161
1162 static int
1163 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1164                     struct drm_framebuffer *old_fb)
1165 {
1166         struct drm_device *dev = crtc->dev;
1167         struct drm_i915_private *dev_priv = dev->dev_private;
1168         struct drm_i915_master_private *master_priv;
1169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1170         struct intel_framebuffer *intel_fb;
1171         struct drm_i915_gem_object *obj_priv;
1172         struct drm_gem_object *obj;
1173         int pipe = intel_crtc->pipe;
1174         int plane = intel_crtc->plane;
1175         unsigned long Start, Offset;
1176         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1177         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1178         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1179         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1180         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1181         u32 dspcntr;
1182         int ret;
1183
1184         /* no fb bound */
1185         if (!crtc->fb) {
1186                 DRM_DEBUG_KMS("No FB bound\n");
1187                 return 0;
1188         }
1189
1190         switch (plane) {
1191         case 0:
1192         case 1:
1193                 break;
1194         default:
1195                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1196                 return -EINVAL;
1197         }
1198
1199         intel_fb = to_intel_framebuffer(crtc->fb);
1200         obj = intel_fb->obj;
1201         obj_priv = obj->driver_private;
1202
1203         mutex_lock(&dev->struct_mutex);
1204         ret = intel_pin_and_fence_fb_obj(dev, obj);
1205         if (ret != 0) {
1206                 mutex_unlock(&dev->struct_mutex);
1207                 return ret;
1208         }
1209
1210         ret = i915_gem_object_set_to_display_plane(obj);
1211         if (ret != 0) {
1212                 i915_gem_object_unpin(obj);
1213                 mutex_unlock(&dev->struct_mutex);
1214                 return ret;
1215         }
1216
1217         dspcntr = I915_READ(dspcntr_reg);
1218         /* Mask out pixel format bits in case we change it */
1219         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1220         switch (crtc->fb->bits_per_pixel) {
1221         case 8:
1222                 dspcntr |= DISPPLANE_8BPP;
1223                 break;
1224         case 16:
1225                 if (crtc->fb->depth == 15)
1226                         dspcntr |= DISPPLANE_15_16BPP;
1227                 else
1228                         dspcntr |= DISPPLANE_16BPP;
1229                 break;
1230         case 24:
1231         case 32:
1232                 if (crtc->fb->depth == 30)
1233                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1234                 else
1235                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1236                 break;
1237         default:
1238                 DRM_ERROR("Unknown color depth\n");
1239                 i915_gem_object_unpin(obj);
1240                 mutex_unlock(&dev->struct_mutex);
1241                 return -EINVAL;
1242         }
1243         if (IS_I965G(dev)) {
1244                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1245                         dspcntr |= DISPPLANE_TILED;
1246                 else
1247                         dspcntr &= ~DISPPLANE_TILED;
1248         }
1249
1250         if (IS_IRONLAKE(dev))
1251                 /* must disable */
1252                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1253
1254         I915_WRITE(dspcntr_reg, dspcntr);
1255
1256         Start = obj_priv->gtt_offset;
1257         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1258
1259         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1260         I915_WRITE(dspstride, crtc->fb->pitch);
1261         if (IS_I965G(dev)) {
1262                 I915_WRITE(dspbase, Offset);
1263                 I915_READ(dspbase);
1264                 I915_WRITE(dspsurf, Start);
1265                 I915_READ(dspsurf);
1266                 I915_WRITE(dsptileoff, (y << 16) | x);
1267         } else {
1268                 I915_WRITE(dspbase, Start + Offset);
1269                 I915_READ(dspbase);
1270         }
1271
1272         if ((IS_I965G(dev) || plane == 0))
1273                 intel_update_fbc(crtc, &crtc->mode);
1274
1275         intel_wait_for_vblank(dev);
1276
1277         if (old_fb) {
1278                 intel_fb = to_intel_framebuffer(old_fb);
1279                 obj_priv = intel_fb->obj->driver_private;
1280                 i915_gem_object_unpin(intel_fb->obj);
1281         }
1282         intel_increase_pllclock(crtc, true);
1283
1284         mutex_unlock(&dev->struct_mutex);
1285
1286         if (!dev->primary->master)
1287                 return 0;
1288
1289         master_priv = dev->primary->master->driver_priv;
1290         if (!master_priv->sarea_priv)
1291                 return 0;
1292
1293         if (pipe) {
1294                 master_priv->sarea_priv->pipeB_x = x;
1295                 master_priv->sarea_priv->pipeB_y = y;
1296         } else {
1297                 master_priv->sarea_priv->pipeA_x = x;
1298                 master_priv->sarea_priv->pipeA_y = y;
1299         }
1300
1301         return 0;
1302 }
1303
1304 /* Disable the VGA plane that we never use */
1305 static void i915_disable_vga (struct drm_device *dev)
1306 {
1307         struct drm_i915_private *dev_priv = dev->dev_private;
1308         u8 sr1;
1309         u32 vga_reg;
1310
1311         if (IS_IRONLAKE(dev))
1312                 vga_reg = CPU_VGACNTRL;
1313         else
1314                 vga_reg = VGACNTRL;
1315
1316         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1317                 return;
1318
1319         I915_WRITE8(VGA_SR_INDEX, 1);
1320         sr1 = I915_READ8(VGA_SR_DATA);
1321         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1322         udelay(100);
1323
1324         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1325 }
1326
1327 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1328 {
1329         struct drm_device *dev = crtc->dev;
1330         struct drm_i915_private *dev_priv = dev->dev_private;
1331         u32 dpa_ctl;
1332
1333         DRM_DEBUG_KMS("\n");
1334         dpa_ctl = I915_READ(DP_A);
1335         dpa_ctl &= ~DP_PLL_ENABLE;
1336         I915_WRITE(DP_A, dpa_ctl);
1337 }
1338
1339 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1340 {
1341         struct drm_device *dev = crtc->dev;
1342         struct drm_i915_private *dev_priv = dev->dev_private;
1343         u32 dpa_ctl;
1344
1345         dpa_ctl = I915_READ(DP_A);
1346         dpa_ctl |= DP_PLL_ENABLE;
1347         I915_WRITE(DP_A, dpa_ctl);
1348         udelay(200);
1349 }
1350
1351
1352 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1353 {
1354         struct drm_device *dev = crtc->dev;
1355         struct drm_i915_private *dev_priv = dev->dev_private;
1356         u32 dpa_ctl;
1357
1358         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1359         dpa_ctl = I915_READ(DP_A);
1360         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1361
1362         if (clock < 200000) {
1363                 u32 temp;
1364                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1365                 /* workaround for 160Mhz:
1366                    1) program 0x4600c bits 15:0 = 0x8124
1367                    2) program 0x46010 bit 0 = 1
1368                    3) program 0x46034 bit 24 = 1
1369                    4) program 0x64000 bit 14 = 1
1370                    */
1371                 temp = I915_READ(0x4600c);
1372                 temp &= 0xffff0000;
1373                 I915_WRITE(0x4600c, temp | 0x8124);
1374
1375                 temp = I915_READ(0x46010);
1376                 I915_WRITE(0x46010, temp | 1);
1377
1378                 temp = I915_READ(0x46034);
1379                 I915_WRITE(0x46034, temp | (1 << 24));
1380         } else {
1381                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1382         }
1383         I915_WRITE(DP_A, dpa_ctl);
1384
1385         udelay(500);
1386 }
1387
1388 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1389 {
1390         struct drm_device *dev = crtc->dev;
1391         struct drm_i915_private *dev_priv = dev->dev_private;
1392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1393         int pipe = intel_crtc->pipe;
1394         int plane = intel_crtc->plane;
1395         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1396         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1397         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1398         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1399         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1400         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1401         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1402         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1403         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1404         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1405         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1406         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1407         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1408         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1409         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1410         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1411         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1412         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1413         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1414         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1415         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1416         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1417         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1418         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1419         u32 temp;
1420         int tries = 5, j, n;
1421         u32 pipe_bpc;
1422
1423         temp = I915_READ(pipeconf_reg);
1424         pipe_bpc = temp & PIPE_BPC_MASK;
1425
1426         /* XXX: When our outputs are all unaware of DPMS modes other than off
1427          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1428          */
1429         switch (mode) {
1430         case DRM_MODE_DPMS_ON:
1431         case DRM_MODE_DPMS_STANDBY:
1432         case DRM_MODE_DPMS_SUSPEND:
1433                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1434
1435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1436                         temp = I915_READ(PCH_LVDS);
1437                         if ((temp & LVDS_PORT_EN) == 0) {
1438                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1439                                 POSTING_READ(PCH_LVDS);
1440                         }
1441                 }
1442
1443                 if (HAS_eDP) {
1444                         /* enable eDP PLL */
1445                         ironlake_enable_pll_edp(crtc);
1446                 } else {
1447                         /* enable PCH DPLL */
1448                         temp = I915_READ(pch_dpll_reg);
1449                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1450                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1451                                 I915_READ(pch_dpll_reg);
1452                         }
1453
1454                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1455                         temp = I915_READ(fdi_rx_reg);
1456                         /*
1457                          * make the BPC in FDI Rx be consistent with that in
1458                          * pipeconf reg.
1459                          */
1460                         temp &= ~(0x7 << 16);
1461                         temp |= (pipe_bpc << 11);
1462                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1463                                         FDI_SEL_PCDCLK |
1464                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1465                         I915_READ(fdi_rx_reg);
1466                         udelay(200);
1467
1468                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1469                         temp = I915_READ(fdi_tx_reg);
1470                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1471                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1472                                 I915_READ(fdi_tx_reg);
1473                                 udelay(100);
1474                         }
1475                 }
1476
1477                 /* Enable panel fitting for LVDS */
1478                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1479                         temp = I915_READ(pf_ctl_reg);
1480                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1481
1482                         /* currently full aspect */
1483                         I915_WRITE(pf_win_pos, 0);
1484
1485                         I915_WRITE(pf_win_size,
1486                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1487                                    (dev_priv->panel_fixed_mode->vdisplay));
1488                 }
1489
1490                 /* Enable CPU pipe */
1491                 temp = I915_READ(pipeconf_reg);
1492                 if ((temp & PIPEACONF_ENABLE) == 0) {
1493                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1494                         I915_READ(pipeconf_reg);
1495                         udelay(100);
1496                 }
1497
1498                 /* configure and enable CPU plane */
1499                 temp = I915_READ(dspcntr_reg);
1500                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1501                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1502                         /* Flush the plane changes */
1503                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1504                 }
1505
1506                 if (!HAS_eDP) {
1507                         /* enable CPU FDI TX and PCH FDI RX */
1508                         temp = I915_READ(fdi_tx_reg);
1509                         temp |= FDI_TX_ENABLE;
1510                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1511                         temp &= ~FDI_LINK_TRAIN_NONE;
1512                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1513                         I915_WRITE(fdi_tx_reg, temp);
1514                         I915_READ(fdi_tx_reg);
1515
1516                         temp = I915_READ(fdi_rx_reg);
1517                         temp &= ~FDI_LINK_TRAIN_NONE;
1518                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1519                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1520                         I915_READ(fdi_rx_reg);
1521
1522                         udelay(150);
1523
1524                         /* Train FDI. */
1525                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1526                            for train result */
1527                         temp = I915_READ(fdi_rx_imr_reg);
1528                         temp &= ~FDI_RX_SYMBOL_LOCK;
1529                         temp &= ~FDI_RX_BIT_LOCK;
1530                         I915_WRITE(fdi_rx_imr_reg, temp);
1531                         I915_READ(fdi_rx_imr_reg);
1532                         udelay(150);
1533
1534                         temp = I915_READ(fdi_rx_iir_reg);
1535                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1536
1537                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1538                                 for (j = 0; j < tries; j++) {
1539                                         temp = I915_READ(fdi_rx_iir_reg);
1540                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1541                                                                 temp);
1542                                         if (temp & FDI_RX_BIT_LOCK)
1543                                                 break;
1544                                         udelay(200);
1545                                 }
1546                                 if (j != tries)
1547                                         I915_WRITE(fdi_rx_iir_reg,
1548                                                         temp | FDI_RX_BIT_LOCK);
1549                                 else
1550                                         DRM_DEBUG_KMS("train 1 fail\n");
1551                         } else {
1552                                 I915_WRITE(fdi_rx_iir_reg,
1553                                                 temp | FDI_RX_BIT_LOCK);
1554                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1555                         }
1556                         temp = I915_READ(fdi_tx_reg);
1557                         temp &= ~FDI_LINK_TRAIN_NONE;
1558                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1559                         I915_WRITE(fdi_tx_reg, temp);
1560
1561                         temp = I915_READ(fdi_rx_reg);
1562                         temp &= ~FDI_LINK_TRAIN_NONE;
1563                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1564                         I915_WRITE(fdi_rx_reg, temp);
1565
1566                         udelay(150);
1567
1568                         temp = I915_READ(fdi_rx_iir_reg);
1569                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1570
1571                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1572                                 for (j = 0; j < tries; j++) {
1573                                         temp = I915_READ(fdi_rx_iir_reg);
1574                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1575                                                                 temp);
1576                                         if (temp & FDI_RX_SYMBOL_LOCK)
1577                                                 break;
1578                                         udelay(200);
1579                                 }
1580                                 if (j != tries) {
1581                                         I915_WRITE(fdi_rx_iir_reg,
1582                                                         temp | FDI_RX_SYMBOL_LOCK);
1583                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1584                                 } else
1585                                         DRM_DEBUG_KMS("train 2 fail\n");
1586                         } else {
1587                                 I915_WRITE(fdi_rx_iir_reg,
1588                                                 temp | FDI_RX_SYMBOL_LOCK);
1589                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1590                         }
1591                         DRM_DEBUG_KMS("train done\n");
1592
1593                         /* set transcoder timing */
1594                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1595                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1596                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1597
1598                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1599                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1600                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1601
1602                         /* enable PCH transcoder */
1603                         temp = I915_READ(transconf_reg);
1604                         /*
1605                          * make the BPC in transcoder be consistent with
1606                          * that in pipeconf reg.
1607                          */
1608                         temp &= ~PIPE_BPC_MASK;
1609                         temp |= pipe_bpc;
1610                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1611                         I915_READ(transconf_reg);
1612
1613                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1614                                 ;
1615
1616                         /* enable normal */
1617
1618                         temp = I915_READ(fdi_tx_reg);
1619                         temp &= ~FDI_LINK_TRAIN_NONE;
1620                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1621                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1622                         I915_READ(fdi_tx_reg);
1623
1624                         temp = I915_READ(fdi_rx_reg);
1625                         temp &= ~FDI_LINK_TRAIN_NONE;
1626                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1627                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1628                         I915_READ(fdi_rx_reg);
1629
1630                         /* wait one idle pattern time */
1631                         udelay(100);
1632
1633                 }
1634
1635                 intel_crtc_load_lut(crtc);
1636
1637         break;
1638         case DRM_MODE_DPMS_OFF:
1639                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1640
1641                 drm_vblank_off(dev, pipe);
1642                 /* Disable display plane */
1643                 temp = I915_READ(dspcntr_reg);
1644                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1645                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1646                         /* Flush the plane changes */
1647                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1648                         I915_READ(dspbase_reg);
1649                 }
1650
1651                 i915_disable_vga(dev);
1652
1653                 /* disable cpu pipe, disable after all planes disabled */
1654                 temp = I915_READ(pipeconf_reg);
1655                 if ((temp & PIPEACONF_ENABLE) != 0) {
1656                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1657                         I915_READ(pipeconf_reg);
1658                         n = 0;
1659                         /* wait for cpu pipe off, pipe state */
1660                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1661                                 n++;
1662                                 if (n < 60) {
1663                                         udelay(500);
1664                                         continue;
1665                                 } else {
1666                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1667                                                                 pipe);
1668                                         break;
1669                                 }
1670                         }
1671                 } else
1672                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1673
1674                 udelay(100);
1675
1676                 /* Disable PF */
1677                 temp = I915_READ(pf_ctl_reg);
1678                 if ((temp & PF_ENABLE) != 0) {
1679                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1680                         I915_READ(pf_ctl_reg);
1681                 }
1682                 I915_WRITE(pf_win_size, 0);
1683
1684                 /* disable CPU FDI tx and PCH FDI rx */
1685                 temp = I915_READ(fdi_tx_reg);
1686                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1687                 I915_READ(fdi_tx_reg);
1688
1689                 temp = I915_READ(fdi_rx_reg);
1690                 /* BPC in FDI rx is consistent with that in pipeconf */
1691                 temp &= ~(0x07 << 16);
1692                 temp |= (pipe_bpc << 11);
1693                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1694                 I915_READ(fdi_rx_reg);
1695
1696                 udelay(100);
1697
1698                 /* still set train pattern 1 */
1699                 temp = I915_READ(fdi_tx_reg);
1700                 temp &= ~FDI_LINK_TRAIN_NONE;
1701                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1702                 I915_WRITE(fdi_tx_reg, temp);
1703
1704                 temp = I915_READ(fdi_rx_reg);
1705                 temp &= ~FDI_LINK_TRAIN_NONE;
1706                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1707                 I915_WRITE(fdi_rx_reg, temp);
1708
1709                 udelay(100);
1710
1711                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1712                         temp = I915_READ(PCH_LVDS);
1713                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1714                         I915_READ(PCH_LVDS);
1715                         udelay(100);
1716                 }
1717
1718                 /* disable PCH transcoder */
1719                 temp = I915_READ(transconf_reg);
1720                 if ((temp & TRANS_ENABLE) != 0) {
1721                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1722                         I915_READ(transconf_reg);
1723                         n = 0;
1724                         /* wait for PCH transcoder off, transcoder state */
1725                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1726                                 n++;
1727                                 if (n < 60) {
1728                                         udelay(500);
1729                                         continue;
1730                                 } else {
1731                                         DRM_DEBUG_KMS("transcoder %d off "
1732                                                         "delay\n", pipe);
1733                                         break;
1734                                 }
1735                         }
1736                 }
1737                 temp = I915_READ(transconf_reg);
1738                 /* BPC in transcoder is consistent with that in pipeconf */
1739                 temp &= ~PIPE_BPC_MASK;
1740                 temp |= pipe_bpc;
1741                 I915_WRITE(transconf_reg, temp);
1742                 I915_READ(transconf_reg);
1743                 udelay(100);
1744
1745                 /* disable PCH DPLL */
1746                 temp = I915_READ(pch_dpll_reg);
1747                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1748                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1749                         I915_READ(pch_dpll_reg);
1750                 }
1751
1752                 if (HAS_eDP) {
1753                         ironlake_disable_pll_edp(crtc);
1754                 }
1755
1756                 temp = I915_READ(fdi_rx_reg);
1757                 temp &= ~FDI_SEL_PCDCLK;
1758                 I915_WRITE(fdi_rx_reg, temp);
1759                 I915_READ(fdi_rx_reg);
1760
1761                 temp = I915_READ(fdi_rx_reg);
1762                 temp &= ~FDI_RX_PLL_ENABLE;
1763                 I915_WRITE(fdi_rx_reg, temp);
1764                 I915_READ(fdi_rx_reg);
1765
1766                 /* Disable CPU FDI TX PLL */
1767                 temp = I915_READ(fdi_tx_reg);
1768                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1769                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1770                         I915_READ(fdi_tx_reg);
1771                         udelay(100);
1772                 }
1773
1774                 /* Wait for the clocks to turn off. */
1775                 udelay(100);
1776                 break;
1777         }
1778 }
1779
1780 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1781 {
1782         struct intel_overlay *overlay;
1783         int ret;
1784
1785         if (!enable && intel_crtc->overlay) {
1786                 overlay = intel_crtc->overlay;
1787                 mutex_lock(&overlay->dev->struct_mutex);
1788                 for (;;) {
1789                         ret = intel_overlay_switch_off(overlay);
1790                         if (ret == 0)
1791                                 break;
1792
1793                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1794                         if (ret != 0) {
1795                                 /* overlay doesn't react anymore. Usually
1796                                  * results in a black screen and an unkillable
1797                                  * X server. */
1798                                 BUG();
1799                                 overlay->hw_wedged = HW_WEDGED;
1800                                 break;
1801                         }
1802                 }
1803                 mutex_unlock(&overlay->dev->struct_mutex);
1804         }
1805         /* Let userspace switch the overlay on again. In most cases userspace
1806          * has to recompute where to put it anyway. */
1807
1808         return;
1809 }
1810
1811 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1812 {
1813         struct drm_device *dev = crtc->dev;
1814         struct drm_i915_private *dev_priv = dev->dev_private;
1815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1816         int pipe = intel_crtc->pipe;
1817         int plane = intel_crtc->plane;
1818         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1819         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1820         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1821         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1822         u32 temp;
1823
1824         /* XXX: When our outputs are all unaware of DPMS modes other than off
1825          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1826          */
1827         switch (mode) {
1828         case DRM_MODE_DPMS_ON:
1829         case DRM_MODE_DPMS_STANDBY:
1830         case DRM_MODE_DPMS_SUSPEND:
1831                 intel_update_watermarks(dev);
1832
1833                 /* Enable the DPLL */
1834                 temp = I915_READ(dpll_reg);
1835                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1836                         I915_WRITE(dpll_reg, temp);
1837                         I915_READ(dpll_reg);
1838                         /* Wait for the clocks to stabilize. */
1839                         udelay(150);
1840                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1841                         I915_READ(dpll_reg);
1842                         /* Wait for the clocks to stabilize. */
1843                         udelay(150);
1844                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1845                         I915_READ(dpll_reg);
1846                         /* Wait for the clocks to stabilize. */
1847                         udelay(150);
1848                 }
1849
1850                 /* Enable the pipe */
1851                 temp = I915_READ(pipeconf_reg);
1852                 if ((temp & PIPEACONF_ENABLE) == 0)
1853                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1854
1855                 /* Enable the plane */
1856                 temp = I915_READ(dspcntr_reg);
1857                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1858                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1859                         /* Flush the plane changes */
1860                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1861                 }
1862
1863                 intel_crtc_load_lut(crtc);
1864
1865                 if ((IS_I965G(dev) || plane == 0))
1866                         intel_update_fbc(crtc, &crtc->mode);
1867
1868                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1869                 intel_crtc_dpms_overlay(intel_crtc, true);
1870         break;
1871         case DRM_MODE_DPMS_OFF:
1872                 intel_update_watermarks(dev);
1873
1874                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1875                 intel_crtc_dpms_overlay(intel_crtc, false);
1876                 drm_vblank_off(dev, pipe);
1877
1878                 if (dev_priv->cfb_plane == plane &&
1879                     dev_priv->display.disable_fbc)
1880                         dev_priv->display.disable_fbc(dev);
1881
1882                 /* Disable the VGA plane that we never use */
1883                 i915_disable_vga(dev);
1884
1885                 /* Disable display plane */
1886                 temp = I915_READ(dspcntr_reg);
1887                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1888                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1889                         /* Flush the plane changes */
1890                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1891                         I915_READ(dspbase_reg);
1892                 }
1893
1894                 if (!IS_I9XX(dev)) {
1895                         /* Wait for vblank for the disable to take effect */
1896                         intel_wait_for_vblank(dev);
1897                 }
1898
1899                 /* Next, disable display pipes */
1900                 temp = I915_READ(pipeconf_reg);
1901                 if ((temp & PIPEACONF_ENABLE) != 0) {
1902                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1903                         I915_READ(pipeconf_reg);
1904                 }
1905
1906                 /* Wait for vblank for the disable to take effect. */
1907                 intel_wait_for_vblank(dev);
1908
1909                 temp = I915_READ(dpll_reg);
1910                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1911                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1912                         I915_READ(dpll_reg);
1913                 }
1914
1915                 /* Wait for the clocks to turn off. */
1916                 udelay(150);
1917                 break;
1918         }
1919 }
1920
1921 /**
1922  * Sets the power management mode of the pipe and plane.
1923  *
1924  * This code should probably grow support for turning the cursor off and back
1925  * on appropriately at the same time as we're turning the pipe off/on.
1926  */
1927 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1928 {
1929         struct drm_device *dev = crtc->dev;
1930         struct drm_i915_private *dev_priv = dev->dev_private;
1931         struct drm_i915_master_private *master_priv;
1932         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1933         int pipe = intel_crtc->pipe;
1934         bool enabled;
1935
1936         dev_priv->display.dpms(crtc, mode);
1937
1938         intel_crtc->dpms_mode = mode;
1939
1940         if (!dev->primary->master)
1941                 return;
1942
1943         master_priv = dev->primary->master->driver_priv;
1944         if (!master_priv->sarea_priv)
1945                 return;
1946
1947         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1948
1949         switch (pipe) {
1950         case 0:
1951                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1952                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1953                 break;
1954         case 1:
1955                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1956                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1957                 break;
1958         default:
1959                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1960                 break;
1961         }
1962 }
1963
1964 static void intel_crtc_prepare (struct drm_crtc *crtc)
1965 {
1966         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1967         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1968 }
1969
1970 static void intel_crtc_commit (struct drm_crtc *crtc)
1971 {
1972         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1973         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1974 }
1975
1976 void intel_encoder_prepare (struct drm_encoder *encoder)
1977 {
1978         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1979         /* lvds has its own version of prepare see intel_lvds_prepare */
1980         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1981 }
1982
1983 void intel_encoder_commit (struct drm_encoder *encoder)
1984 {
1985         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1986         /* lvds has its own version of commit see intel_lvds_commit */
1987         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1988 }
1989
1990 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1991                                   struct drm_display_mode *mode,
1992                                   struct drm_display_mode *adjusted_mode)
1993 {
1994         struct drm_device *dev = crtc->dev;
1995         if (IS_IRONLAKE(dev)) {
1996                 /* FDI link clock is fixed at 2.7G */
1997                 if (mode->clock * 3 > 27000 * 4)
1998                         return MODE_CLOCK_HIGH;
1999         }
2000         return true;
2001 }
2002
2003 static int i945_get_display_clock_speed(struct drm_device *dev)
2004 {
2005         return 400000;
2006 }
2007
2008 static int i915_get_display_clock_speed(struct drm_device *dev)
2009 {
2010         return 333000;
2011 }
2012
2013 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2014 {
2015         return 200000;
2016 }
2017
2018 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2019 {
2020         u16 gcfgc = 0;
2021
2022         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2023
2024         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2025                 return 133000;
2026         else {
2027                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2028                 case GC_DISPLAY_CLOCK_333_MHZ:
2029                         return 333000;
2030                 default:
2031                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2032                         return 190000;
2033                 }
2034         }
2035 }
2036
2037 static int i865_get_display_clock_speed(struct drm_device *dev)
2038 {
2039         return 266000;
2040 }
2041
2042 static int i855_get_display_clock_speed(struct drm_device *dev)
2043 {
2044         u16 hpllcc = 0;
2045         /* Assume that the hardware is in the high speed state.  This
2046          * should be the default.
2047          */
2048         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2049         case GC_CLOCK_133_200:
2050         case GC_CLOCK_100_200:
2051                 return 200000;
2052         case GC_CLOCK_166_250:
2053                 return 250000;
2054         case GC_CLOCK_100_133:
2055                 return 133000;
2056         }
2057
2058         /* Shouldn't happen */
2059         return 0;
2060 }
2061
2062 static int i830_get_display_clock_speed(struct drm_device *dev)
2063 {
2064         return 133000;
2065 }
2066
2067 /**
2068  * Return the pipe currently connected to the panel fitter,
2069  * or -1 if the panel fitter is not present or not in use
2070  */
2071 int intel_panel_fitter_pipe (struct drm_device *dev)
2072 {
2073         struct drm_i915_private *dev_priv = dev->dev_private;
2074         u32  pfit_control;
2075
2076         /* i830 doesn't have a panel fitter */
2077         if (IS_I830(dev))
2078                 return -1;
2079
2080         pfit_control = I915_READ(PFIT_CONTROL);
2081
2082         /* See if the panel fitter is in use */
2083         if ((pfit_control & PFIT_ENABLE) == 0)
2084                 return -1;
2085
2086         /* 965 can place panel fitter on either pipe */
2087         if (IS_I965G(dev))
2088                 return (pfit_control >> 29) & 0x3;
2089
2090         /* older chips can only use pipe 1 */
2091         return 1;
2092 }
2093
2094 struct fdi_m_n {
2095         u32        tu;
2096         u32        gmch_m;
2097         u32        gmch_n;
2098         u32        link_m;
2099         u32        link_n;
2100 };
2101
2102 static void
2103 fdi_reduce_ratio(u32 *num, u32 *den)
2104 {
2105         while (*num > 0xffffff || *den > 0xffffff) {
2106                 *num >>= 1;
2107                 *den >>= 1;
2108         }
2109 }
2110
2111 #define DATA_N 0x800000
2112 #define LINK_N 0x80000
2113
2114 static void
2115 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2116                      int link_clock, struct fdi_m_n *m_n)
2117 {
2118         u64 temp;
2119
2120         m_n->tu = 64; /* default size */
2121
2122         temp = (u64) DATA_N * pixel_clock;
2123         temp = div_u64(temp, link_clock);
2124         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2125         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2126         m_n->gmch_n = DATA_N;
2127         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2128
2129         temp = (u64) LINK_N * pixel_clock;
2130         m_n->link_m = div_u64(temp, link_clock);
2131         m_n->link_n = LINK_N;
2132         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2133 }
2134
2135
2136 struct intel_watermark_params {
2137         unsigned long fifo_size;
2138         unsigned long max_wm;
2139         unsigned long default_wm;
2140         unsigned long guard_size;
2141         unsigned long cacheline_size;
2142 };
2143
2144 /* Pineview has different values for various configs */
2145 static struct intel_watermark_params pineview_display_wm = {
2146         PINEVIEW_DISPLAY_FIFO,
2147         PINEVIEW_MAX_WM,
2148         PINEVIEW_DFT_WM,
2149         PINEVIEW_GUARD_WM,
2150         PINEVIEW_FIFO_LINE_SIZE
2151 };
2152 static struct intel_watermark_params pineview_display_hplloff_wm = {
2153         PINEVIEW_DISPLAY_FIFO,
2154         PINEVIEW_MAX_WM,
2155         PINEVIEW_DFT_HPLLOFF_WM,
2156         PINEVIEW_GUARD_WM,
2157         PINEVIEW_FIFO_LINE_SIZE
2158 };
2159 static struct intel_watermark_params pineview_cursor_wm = {
2160         PINEVIEW_CURSOR_FIFO,
2161         PINEVIEW_CURSOR_MAX_WM,
2162         PINEVIEW_CURSOR_DFT_WM,
2163         PINEVIEW_CURSOR_GUARD_WM,
2164         PINEVIEW_FIFO_LINE_SIZE,
2165 };
2166 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2167         PINEVIEW_CURSOR_FIFO,
2168         PINEVIEW_CURSOR_MAX_WM,
2169         PINEVIEW_CURSOR_DFT_WM,
2170         PINEVIEW_CURSOR_GUARD_WM,
2171         PINEVIEW_FIFO_LINE_SIZE
2172 };
2173 static struct intel_watermark_params g4x_wm_info = {
2174         G4X_FIFO_SIZE,
2175         G4X_MAX_WM,
2176         G4X_MAX_WM,
2177         2,
2178         G4X_FIFO_LINE_SIZE,
2179 };
2180 static struct intel_watermark_params i945_wm_info = {
2181         I945_FIFO_SIZE,
2182         I915_MAX_WM,
2183         1,
2184         2,
2185         I915_FIFO_LINE_SIZE
2186 };
2187 static struct intel_watermark_params i915_wm_info = {
2188         I915_FIFO_SIZE,
2189         I915_MAX_WM,
2190         1,
2191         2,
2192         I915_FIFO_LINE_SIZE
2193 };
2194 static struct intel_watermark_params i855_wm_info = {
2195         I855GM_FIFO_SIZE,
2196         I915_MAX_WM,
2197         1,
2198         2,
2199         I830_FIFO_LINE_SIZE
2200 };
2201 static struct intel_watermark_params i830_wm_info = {
2202         I830_FIFO_SIZE,
2203         I915_MAX_WM,
2204         1,
2205         2,
2206         I830_FIFO_LINE_SIZE
2207 };
2208
2209 /**
2210  * intel_calculate_wm - calculate watermark level
2211  * @clock_in_khz: pixel clock
2212  * @wm: chip FIFO params
2213  * @pixel_size: display pixel size
2214  * @latency_ns: memory latency for the platform
2215  *
2216  * Calculate the watermark level (the level at which the display plane will
2217  * start fetching from memory again).  Each chip has a different display
2218  * FIFO size and allocation, so the caller needs to figure that out and pass
2219  * in the correct intel_watermark_params structure.
2220  *
2221  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2222  * on the pixel size.  When it reaches the watermark level, it'll start
2223  * fetching FIFO line sized based chunks from memory until the FIFO fills
2224  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2225  * will occur, and a display engine hang could result.
2226  */
2227 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2228                                         struct intel_watermark_params *wm,
2229                                         int pixel_size,
2230                                         unsigned long latency_ns)
2231 {
2232         long entries_required, wm_size;
2233
2234         /*
2235          * Note: we need to make sure we don't overflow for various clock &
2236          * latency values.
2237          * clocks go from a few thousand to several hundred thousand.
2238          * latency is usually a few thousand
2239          */
2240         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2241                 1000;
2242         entries_required /= wm->cacheline_size;
2243
2244         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2245
2246         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2247
2248         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2249
2250         /* Don't promote wm_size to unsigned... */
2251         if (wm_size > (long)wm->max_wm)
2252                 wm_size = wm->max_wm;
2253         if (wm_size <= 0)
2254                 wm_size = wm->default_wm;
2255         return wm_size;
2256 }
2257
2258 struct cxsr_latency {
2259         int is_desktop;
2260         unsigned long fsb_freq;
2261         unsigned long mem_freq;
2262         unsigned long display_sr;
2263         unsigned long display_hpll_disable;
2264         unsigned long cursor_sr;
2265         unsigned long cursor_hpll_disable;
2266 };
2267
2268 static struct cxsr_latency cxsr_latency_table[] = {
2269         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2270         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2271         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2272
2273         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2274         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2275         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2276
2277         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2278         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2279         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2280
2281         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2282         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2283         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2284
2285         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2286         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2287         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2288
2289         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2290         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2291         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2292 };
2293
2294 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2295                                                    int mem)
2296 {
2297         int i;
2298         struct cxsr_latency *latency;
2299
2300         if (fsb == 0 || mem == 0)
2301                 return NULL;
2302
2303         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2304                 latency = &cxsr_latency_table[i];
2305                 if (is_desktop == latency->is_desktop &&
2306                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2307                         return latency;
2308         }
2309
2310         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2311
2312         return NULL;
2313 }
2314
2315 static void pineview_disable_cxsr(struct drm_device *dev)
2316 {
2317         struct drm_i915_private *dev_priv = dev->dev_private;
2318         u32 reg;
2319
2320         /* deactivate cxsr */
2321         reg = I915_READ(DSPFW3);
2322         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2323         I915_WRITE(DSPFW3, reg);
2324         DRM_INFO("Big FIFO is disabled\n");
2325 }
2326
2327 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2328                                  int pixel_size)
2329 {
2330         struct drm_i915_private *dev_priv = dev->dev_private;
2331         u32 reg;
2332         unsigned long wm;
2333         struct cxsr_latency *latency;
2334
2335         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2336                 dev_priv->mem_freq);
2337         if (!latency) {
2338                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2339                 pineview_disable_cxsr(dev);
2340                 return;
2341         }
2342
2343         /* Display SR */
2344         wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2345                                 latency->display_sr);
2346         reg = I915_READ(DSPFW1);
2347         reg &= 0x7fffff;
2348         reg |= wm << 23;
2349         I915_WRITE(DSPFW1, reg);
2350         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2351
2352         /* cursor SR */
2353         wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2354                                 latency->cursor_sr);
2355         reg = I915_READ(DSPFW3);
2356         reg &= ~(0x3f << 24);
2357         reg |= (wm & 0x3f) << 24;
2358         I915_WRITE(DSPFW3, reg);
2359
2360         /* Display HPLL off SR */
2361         wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2362                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2363         reg = I915_READ(DSPFW3);
2364         reg &= 0xfffffe00;
2365         reg |= wm & 0x1ff;
2366         I915_WRITE(DSPFW3, reg);
2367
2368         /* cursor HPLL off SR */
2369         wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2370                                 latency->cursor_hpll_disable);
2371         reg = I915_READ(DSPFW3);
2372         reg &= ~(0x3f << 16);
2373         reg |= (wm & 0x3f) << 16;
2374         I915_WRITE(DSPFW3, reg);
2375         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2376
2377         /* activate cxsr */
2378         reg = I915_READ(DSPFW3);
2379         reg |= PINEVIEW_SELF_REFRESH_EN;
2380         I915_WRITE(DSPFW3, reg);
2381
2382         DRM_INFO("Big FIFO is enabled\n");
2383
2384         return;
2385 }
2386
2387 /*
2388  * Latency for FIFO fetches is dependent on several factors:
2389  *   - memory configuration (speed, channels)
2390  *   - chipset
2391  *   - current MCH state
2392  * It can be fairly high in some situations, so here we assume a fairly
2393  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2394  * set this value too high, the FIFO will fetch frequently to stay full)
2395  * and power consumption (set it too low to save power and we might see
2396  * FIFO underruns and display "flicker").
2397  *
2398  * A value of 5us seems to be a good balance; safe for very low end
2399  * platforms but not overly aggressive on lower latency configs.
2400  */
2401 static const int latency_ns = 5000;
2402
2403 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2404 {
2405         struct drm_i915_private *dev_priv = dev->dev_private;
2406         uint32_t dsparb = I915_READ(DSPARB);
2407         int size;
2408
2409         if (plane == 0)
2410                 size = dsparb & 0x7f;
2411         else
2412                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2413                         (dsparb & 0x7f);
2414
2415         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2416                         plane ? "B" : "A", size);
2417
2418         return size;
2419 }
2420
2421 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2422 {
2423         struct drm_i915_private *dev_priv = dev->dev_private;
2424         uint32_t dsparb = I915_READ(DSPARB);
2425         int size;
2426
2427         if (plane == 0)
2428                 size = dsparb & 0x1ff;
2429         else
2430                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2431                         (dsparb & 0x1ff);
2432         size >>= 1; /* Convert to cachelines */
2433
2434         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2435                         plane ? "B" : "A", size);
2436
2437         return size;
2438 }
2439
2440 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2441 {
2442         struct drm_i915_private *dev_priv = dev->dev_private;
2443         uint32_t dsparb = I915_READ(DSPARB);
2444         int size;
2445
2446         size = dsparb & 0x7f;
2447         size >>= 2; /* Convert to cachelines */
2448
2449         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2450                         plane ? "B" : "A",
2451                   size);
2452
2453         return size;
2454 }
2455
2456 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2457 {
2458         struct drm_i915_private *dev_priv = dev->dev_private;
2459         uint32_t dsparb = I915_READ(DSPARB);
2460         int size;
2461
2462         size = dsparb & 0x7f;
2463         size >>= 1; /* Convert to cachelines */
2464
2465         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2466                         plane ? "B" : "A", size);
2467
2468         return size;
2469 }
2470
2471 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2472                           int planeb_clock, int sr_hdisplay, int pixel_size)
2473 {
2474         struct drm_i915_private *dev_priv = dev->dev_private;
2475         int total_size, cacheline_size;
2476         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2477         struct intel_watermark_params planea_params, planeb_params;
2478         unsigned long line_time_us;
2479         int sr_clock, sr_entries = 0, entries_required;
2480
2481         /* Create copies of the base settings for each pipe */
2482         planea_params = planeb_params = g4x_wm_info;
2483
2484         /* Grab a couple of global values before we overwrite them */
2485         total_size = planea_params.fifo_size;
2486         cacheline_size = planea_params.cacheline_size;
2487
2488         /*
2489          * Note: we need to make sure we don't overflow for various clock &
2490          * latency values.
2491          * clocks go from a few thousand to several hundred thousand.
2492          * latency is usually a few thousand
2493          */
2494         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2495                 1000;
2496         entries_required /= G4X_FIFO_LINE_SIZE;
2497         planea_wm = entries_required + planea_params.guard_size;
2498
2499         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2500                 1000;
2501         entries_required /= G4X_FIFO_LINE_SIZE;
2502         planeb_wm = entries_required + planeb_params.guard_size;
2503
2504         cursora_wm = cursorb_wm = 16;
2505         cursor_sr = 32;
2506
2507         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2508
2509         /* Calc sr entries for one plane configs */
2510         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2511                 /* self-refresh has much higher latency */
2512                 static const int sr_latency_ns = 12000;
2513
2514                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2515                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2516
2517                 /* Use ns/us then divide to preserve precision */
2518                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2519                               pixel_size * sr_hdisplay) / 1000;
2520                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2521                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2522                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2523         }
2524
2525         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2526                   planea_wm, planeb_wm, sr_entries);
2527
2528         planea_wm &= 0x3f;
2529         planeb_wm &= 0x3f;
2530
2531         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2532                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2533                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2534         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2535                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2536         /* HPLL off in SR has some issues on G4x... disable it */
2537         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2538                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2539 }
2540
2541 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2542                            int planeb_clock, int sr_hdisplay, int pixel_size)
2543 {
2544         struct drm_i915_private *dev_priv = dev->dev_private;
2545         unsigned long line_time_us;
2546         int sr_clock, sr_entries, srwm = 1;
2547
2548         /* Calc sr entries for one plane configs */
2549         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2550                 /* self-refresh has much higher latency */
2551                 static const int sr_latency_ns = 12000;
2552
2553                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2554                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2555
2556                 /* Use ns/us then divide to preserve precision */
2557                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2558                               pixel_size * sr_hdisplay) / 1000;
2559                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2560                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2561                 srwm = I945_FIFO_SIZE - sr_entries;
2562                 if (srwm < 0)
2563                         srwm = 1;
2564                 srwm &= 0x3f;
2565                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2566         }
2567
2568         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2569                       srwm);
2570
2571         /* 965 has limitations... */
2572         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2573                    (8 << 0));
2574         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2575 }
2576
2577 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2578                            int planeb_clock, int sr_hdisplay, int pixel_size)
2579 {
2580         struct drm_i915_private *dev_priv = dev->dev_private;
2581         uint32_t fwater_lo;
2582         uint32_t fwater_hi;
2583         int total_size, cacheline_size, cwm, srwm = 1;
2584         int planea_wm, planeb_wm;
2585         struct intel_watermark_params planea_params, planeb_params;
2586         unsigned long line_time_us;
2587         int sr_clock, sr_entries = 0;
2588
2589         /* Create copies of the base settings for each pipe */
2590         if (IS_I965GM(dev) || IS_I945GM(dev))
2591                 planea_params = planeb_params = i945_wm_info;
2592         else if (IS_I9XX(dev))
2593                 planea_params = planeb_params = i915_wm_info;
2594         else
2595                 planea_params = planeb_params = i855_wm_info;
2596
2597         /* Grab a couple of global values before we overwrite them */
2598         total_size = planea_params.fifo_size;
2599         cacheline_size = planea_params.cacheline_size;
2600
2601         /* Update per-plane FIFO sizes */
2602         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2603         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2604
2605         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2606                                        pixel_size, latency_ns);
2607         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2608                                        pixel_size, latency_ns);
2609         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2610
2611         /*
2612          * Overlay gets an aggressive default since video jitter is bad.
2613          */
2614         cwm = 2;
2615
2616         /* Calc sr entries for one plane configs */
2617         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2618             (!planea_clock || !planeb_clock)) {
2619                 /* self-refresh has much higher latency */
2620                 static const int sr_latency_ns = 6000;
2621
2622                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2623                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2624
2625                 /* Use ns/us then divide to preserve precision */
2626                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2627                               pixel_size * sr_hdisplay) / 1000;
2628                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2629                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2630                 srwm = total_size - sr_entries;
2631                 if (srwm < 0)
2632                         srwm = 1;
2633                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2634         }
2635
2636         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2637                   planea_wm, planeb_wm, cwm, srwm);
2638
2639         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2640         fwater_hi = (cwm & 0x1f);
2641
2642         /* Set request length to 8 cachelines per fetch */
2643         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2644         fwater_hi = fwater_hi | (1 << 8);
2645
2646         I915_WRITE(FW_BLC, fwater_lo);
2647         I915_WRITE(FW_BLC2, fwater_hi);
2648 }
2649
2650 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2651                            int unused2, int pixel_size)
2652 {
2653         struct drm_i915_private *dev_priv = dev->dev_private;
2654         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2655         int planea_wm;
2656
2657         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2658
2659         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2660                                        pixel_size, latency_ns);
2661         fwater_lo |= (3<<8) | planea_wm;
2662
2663         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2664
2665         I915_WRITE(FW_BLC, fwater_lo);
2666 }
2667
2668 /**
2669  * intel_update_watermarks - update FIFO watermark values based on current modes
2670  *
2671  * Calculate watermark values for the various WM regs based on current mode
2672  * and plane configuration.
2673  *
2674  * There are several cases to deal with here:
2675  *   - normal (i.e. non-self-refresh)
2676  *   - self-refresh (SR) mode
2677  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2678  *   - lines are small relative to FIFO size (buffer can hold more than 2
2679  *     lines), so need to account for TLB latency
2680  *
2681  *   The normal calculation is:
2682  *     watermark = dotclock * bytes per pixel * latency
2683  *   where latency is platform & configuration dependent (we assume pessimal
2684  *   values here).
2685  *
2686  *   The SR calculation is:
2687  *     watermark = (trunc(latency/line time)+1) * surface width *
2688  *       bytes per pixel
2689  *   where
2690  *     line time = htotal / dotclock
2691  *   and latency is assumed to be high, as above.
2692  *
2693  * The final value programmed to the register should always be rounded up,
2694  * and include an extra 2 entries to account for clock crossings.
2695  *
2696  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2697  * to set the non-SR watermarks to 8.
2698   */
2699 static void intel_update_watermarks(struct drm_device *dev)
2700 {
2701         struct drm_i915_private *dev_priv = dev->dev_private;
2702         struct drm_crtc *crtc;
2703         struct intel_crtc *intel_crtc;
2704         int sr_hdisplay = 0;
2705         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2706         int enabled = 0, pixel_size = 0;
2707
2708         if (!dev_priv->display.update_wm)
2709                 return;
2710
2711         /* Get the clock config from both planes */
2712         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2713                 intel_crtc = to_intel_crtc(crtc);
2714                 if (crtc->enabled) {
2715                         enabled++;
2716                         if (intel_crtc->plane == 0) {
2717                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2718                                           intel_crtc->pipe, crtc->mode.clock);
2719                                 planea_clock = crtc->mode.clock;
2720                         } else {
2721                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2722                                           intel_crtc->pipe, crtc->mode.clock);
2723                                 planeb_clock = crtc->mode.clock;
2724                         }
2725                         sr_hdisplay = crtc->mode.hdisplay;
2726                         sr_clock = crtc->mode.clock;
2727                         if (crtc->fb)
2728                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2729                         else
2730                                 pixel_size = 4; /* by default */
2731                 }
2732         }
2733
2734         if (enabled <= 0)
2735                 return;
2736
2737         /* Single plane configs can enable self refresh */
2738         if (enabled == 1 && IS_PINEVIEW(dev))
2739                 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2740         else if (IS_PINEVIEW(dev))
2741                 pineview_disable_cxsr(dev);
2742
2743         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2744                                     sr_hdisplay, pixel_size);
2745 }
2746
2747 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2748                                struct drm_display_mode *mode,
2749                                struct drm_display_mode *adjusted_mode,
2750                                int x, int y,
2751                                struct drm_framebuffer *old_fb)
2752 {
2753         struct drm_device *dev = crtc->dev;
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756         int pipe = intel_crtc->pipe;
2757         int plane = intel_crtc->plane;
2758         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2759         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2760         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2761         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2762         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2763         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2764         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2765         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2766         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2767         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2768         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2769         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2770         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2771         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2772         int refclk, num_outputs = 0;
2773         intel_clock_t clock, reduced_clock;
2774         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2775         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2776         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2777         bool is_edp = false;
2778         struct drm_mode_config *mode_config = &dev->mode_config;
2779         struct drm_connector *connector;
2780         const intel_limit_t *limit;
2781         int ret;
2782         struct fdi_m_n m_n = {0};
2783         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2784         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2785         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2786         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2787         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2788         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2789         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2790         int lvds_reg = LVDS;
2791         u32 temp;
2792         int sdvo_pixel_multiply;
2793         int target_clock;
2794
2795         drm_vblank_pre_modeset(dev, pipe);
2796
2797         list_for_each_entry(connector, &mode_config->connector_list, head) {
2798                 struct intel_output *intel_output = to_intel_output(connector);
2799
2800                 if (!connector->encoder || connector->encoder->crtc != crtc)
2801                         continue;
2802
2803                 switch (intel_output->type) {
2804                 case INTEL_OUTPUT_LVDS:
2805                         is_lvds = true;
2806                         break;
2807                 case INTEL_OUTPUT_SDVO:
2808                 case INTEL_OUTPUT_HDMI:
2809                         is_sdvo = true;
2810                         if (intel_output->needs_tv_clock)
2811                                 is_tv = true;
2812                         break;
2813                 case INTEL_OUTPUT_DVO:
2814                         is_dvo = true;
2815                         break;
2816                 case INTEL_OUTPUT_TVOUT:
2817                         is_tv = true;
2818                         break;
2819                 case INTEL_OUTPUT_ANALOG:
2820                         is_crt = true;
2821                         break;
2822                 case INTEL_OUTPUT_DISPLAYPORT:
2823                         is_dp = true;
2824                         break;
2825                 case INTEL_OUTPUT_EDP:
2826                         is_edp = true;
2827                         break;
2828                 }
2829
2830                 num_outputs++;
2831         }
2832
2833         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2834                 refclk = dev_priv->lvds_ssc_freq * 1000;
2835                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2836                                         refclk / 1000);
2837         } else if (IS_I9XX(dev)) {
2838                 refclk = 96000;
2839                 if (IS_IRONLAKE(dev))
2840                         refclk = 120000; /* 120Mhz refclk */
2841         } else {
2842                 refclk = 48000;
2843         }
2844
2845
2846         /*
2847          * Returns a set of divisors for the desired target clock with the given
2848          * refclk, or FALSE.  The returned values represent the clock equation:
2849          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2850          */
2851         limit = intel_limit(crtc);
2852         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2853         if (!ok) {
2854                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2855                 drm_vblank_post_modeset(dev, pipe);
2856                 return -EINVAL;
2857         }
2858
2859         if (is_lvds && dev_priv->lvds_downclock_avail) {
2860                 has_reduced_clock = limit->find_pll(limit, crtc,
2861                                                             dev_priv->lvds_downclock,
2862                                                             refclk,
2863                                                             &reduced_clock);
2864                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2865                         /*
2866                          * If the different P is found, it means that we can't
2867                          * switch the display clock by using the FP0/FP1.
2868                          * In such case we will disable the LVDS downclock
2869                          * feature.
2870                          */
2871                         DRM_DEBUG_KMS("Different P is found for "
2872                                                 "LVDS clock/downclock\n");
2873                         has_reduced_clock = 0;
2874                 }
2875         }
2876         /* SDVO TV has fixed PLL values depend on its clock range,
2877            this mirrors vbios setting. */
2878         if (is_sdvo && is_tv) {
2879                 if (adjusted_mode->clock >= 100000
2880                                 && adjusted_mode->clock < 140500) {
2881                         clock.p1 = 2;
2882                         clock.p2 = 10;
2883                         clock.n = 3;
2884                         clock.m1 = 16;
2885                         clock.m2 = 8;
2886                 } else if (adjusted_mode->clock >= 140500
2887                                 && adjusted_mode->clock <= 200000) {
2888                         clock.p1 = 1;
2889                         clock.p2 = 10;
2890                         clock.n = 6;
2891                         clock.m1 = 12;
2892                         clock.m2 = 8;
2893                 }
2894         }
2895
2896         /* FDI link */
2897         if (IS_IRONLAKE(dev)) {
2898                 int lane, link_bw, bpp;
2899                 /* eDP doesn't require FDI link, so just set DP M/N
2900                    according to current link config */
2901                 if (is_edp) {
2902                         struct drm_connector *edp;
2903                         target_clock = mode->clock;
2904                         edp = intel_pipe_get_output(crtc);
2905                         intel_edp_link_config(to_intel_output(edp),
2906                                         &lane, &link_bw);
2907                 } else {
2908                         /* DP over FDI requires target mode clock
2909                            instead of link clock */
2910                         if (is_dp)
2911                                 target_clock = mode->clock;
2912                         else
2913                                 target_clock = adjusted_mode->clock;
2914                         lane = 4;
2915                         link_bw = 270000;
2916                 }
2917
2918                 /* determine panel color depth */
2919                 temp = I915_READ(pipeconf_reg);
2920                 temp &= ~PIPE_BPC_MASK;
2921                 if (is_lvds) {
2922                         int lvds_reg = I915_READ(PCH_LVDS);
2923                         /* the BPC will be 6 if it is 18-bit LVDS panel */
2924                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
2925                                 temp |= PIPE_8BPC;
2926                         else
2927                                 temp |= PIPE_6BPC;
2928                 } else if (is_edp) {
2929                         switch (dev_priv->edp_bpp/3) {
2930                         case 8:
2931                                 temp |= PIPE_8BPC;
2932                                 break;
2933                         case 10:
2934                                 temp |= PIPE_10BPC;
2935                                 break;
2936                         case 6:
2937                                 temp |= PIPE_6BPC;
2938                                 break;
2939                         case 12:
2940                                 temp |= PIPE_12BPC;
2941                                 break;
2942                         }
2943                 } else
2944                         temp |= PIPE_8BPC;
2945                 I915_WRITE(pipeconf_reg, temp);
2946                 I915_READ(pipeconf_reg);
2947
2948                 switch (temp & PIPE_BPC_MASK) {
2949                 case PIPE_8BPC:
2950                         bpp = 24;
2951                         break;
2952                 case PIPE_10BPC:
2953                         bpp = 30;
2954                         break;
2955                 case PIPE_6BPC:
2956                         bpp = 18;
2957                         break;
2958                 case PIPE_12BPC:
2959                         bpp = 36;
2960                         break;
2961                 default:
2962                         DRM_ERROR("unknown pipe bpc value\n");
2963                         bpp = 24;
2964                 }
2965
2966                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
2967         }
2968
2969         /* Ironlake: try to setup display ref clock before DPLL
2970          * enabling. This is only under driver's control after
2971          * PCH B stepping, previous chipset stepping should be
2972          * ignoring this setting.
2973          */
2974         if (IS_IRONLAKE(dev)) {
2975                 temp = I915_READ(PCH_DREF_CONTROL);
2976                 /* Always enable nonspread source */
2977                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2978                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2979                 I915_WRITE(PCH_DREF_CONTROL, temp);
2980                 POSTING_READ(PCH_DREF_CONTROL);
2981
2982                 temp &= ~DREF_SSC_SOURCE_MASK;
2983                 temp |= DREF_SSC_SOURCE_ENABLE;
2984                 I915_WRITE(PCH_DREF_CONTROL, temp);
2985                 POSTING_READ(PCH_DREF_CONTROL);
2986
2987                 udelay(200);
2988
2989                 if (is_edp) {
2990                         if (dev_priv->lvds_use_ssc) {
2991                                 temp |= DREF_SSC1_ENABLE;
2992                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2993                                 POSTING_READ(PCH_DREF_CONTROL);
2994
2995                                 udelay(200);
2996
2997                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2998                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2999                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3000                                 POSTING_READ(PCH_DREF_CONTROL);
3001                         } else {
3002                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3003                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3004                                 POSTING_READ(PCH_DREF_CONTROL);
3005                         }
3006                 }
3007         }
3008
3009         if (IS_PINEVIEW(dev)) {
3010                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3011                 if (has_reduced_clock)
3012                         fp2 = (1 << reduced_clock.n) << 16 |
3013                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3014         } else {
3015                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3016                 if (has_reduced_clock)
3017                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3018                                 reduced_clock.m2;
3019         }
3020
3021         if (!IS_IRONLAKE(dev))
3022                 dpll = DPLL_VGA_MODE_DIS;
3023
3024         if (IS_I9XX(dev)) {
3025                 if (is_lvds)
3026                         dpll |= DPLLB_MODE_LVDS;
3027                 else
3028                         dpll |= DPLLB_MODE_DAC_SERIAL;
3029                 if (is_sdvo) {
3030                         dpll |= DPLL_DVO_HIGH_SPEED;
3031                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3032                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3033                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3034                         else if (IS_IRONLAKE(dev))
3035                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3036                 }
3037                 if (is_dp)
3038                         dpll |= DPLL_DVO_HIGH_SPEED;
3039
3040                 /* compute bitmask from p1 value */
3041                 if (IS_PINEVIEW(dev))
3042                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3043                 else {
3044                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3045                         /* also FPA1 */
3046                         if (IS_IRONLAKE(dev))
3047                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3048                         if (IS_G4X(dev) && has_reduced_clock)
3049                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3050                 }
3051                 switch (clock.p2) {
3052                 case 5:
3053                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3054                         break;
3055                 case 7:
3056                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3057                         break;
3058                 case 10:
3059                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3060                         break;
3061                 case 14:
3062                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3063                         break;
3064                 }
3065                 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
3066                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3067         } else {
3068                 if (is_lvds) {
3069                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3070                 } else {
3071                         if (clock.p1 == 2)
3072                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3073                         else
3074                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3075                         if (clock.p2 == 4)
3076                                 dpll |= PLL_P2_DIVIDE_BY_4;
3077                 }
3078         }
3079
3080         if (is_sdvo && is_tv)
3081                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3082         else if (is_tv)
3083                 /* XXX: just matching BIOS for now */
3084                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3085                 dpll |= 3;
3086         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3087                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3088         else
3089                 dpll |= PLL_REF_INPUT_DREFCLK;
3090
3091         /* setup pipeconf */
3092         pipeconf = I915_READ(pipeconf_reg);
3093
3094         /* Set up the display plane register */
3095         dspcntr = DISPPLANE_GAMMA_ENABLE;
3096
3097         /* Ironlake's plane is forced to pipe, bit 24 is to
3098            enable color space conversion */
3099         if (!IS_IRONLAKE(dev)) {
3100                 if (pipe == 0)
3101                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3102                 else
3103                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3104         }
3105
3106         if (pipe == 0 && !IS_I965G(dev)) {
3107                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3108                  * core speed.
3109                  *
3110                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3111                  * pipe == 0 check?
3112                  */
3113                 if (mode->clock >
3114                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3115                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3116                 else
3117                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3118         }
3119
3120         dspcntr |= DISPLAY_PLANE_ENABLE;
3121         pipeconf |= PIPEACONF_ENABLE;
3122         dpll |= DPLL_VCO_ENABLE;
3123
3124
3125         /* Disable the panel fitter if it was on our pipe */
3126         if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
3127                 I915_WRITE(PFIT_CONTROL, 0);
3128
3129         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3130         drm_mode_debug_printmodeline(mode);
3131
3132         /* assign to Ironlake registers */
3133         if (IS_IRONLAKE(dev)) {
3134                 fp_reg = pch_fp_reg;
3135                 dpll_reg = pch_dpll_reg;
3136         }
3137
3138         if (is_edp) {
3139                 ironlake_disable_pll_edp(crtc);
3140         } else if ((dpll & DPLL_VCO_ENABLE)) {
3141                 I915_WRITE(fp_reg, fp);
3142                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3143                 I915_READ(dpll_reg);
3144                 udelay(150);
3145         }
3146
3147         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3148          * This is an exception to the general rule that mode_set doesn't turn
3149          * things on.
3150          */
3151         if (is_lvds) {
3152                 u32 lvds;
3153
3154                 if (IS_IRONLAKE(dev))
3155                         lvds_reg = PCH_LVDS;
3156
3157                 lvds = I915_READ(lvds_reg);
3158                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3159                 /* set the corresponsding LVDS_BORDER bit */
3160                 lvds |= dev_priv->lvds_border_bits;
3161                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3162                  * set the DPLLs for dual-channel mode or not.
3163                  */
3164                 if (clock.p2 == 7)
3165                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3166                 else
3167                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3168
3169                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3170                  * appropriately here, but we need to look more thoroughly into how
3171                  * panels behave in the two modes.
3172                  */
3173                 /* set the dithering flag */
3174                 if (IS_I965G(dev)) {
3175                         if (dev_priv->lvds_dither) {
3176                                 if (IS_IRONLAKE(dev))
3177                                         pipeconf |= PIPE_ENABLE_DITHER;
3178                                 else
3179                                         lvds |= LVDS_ENABLE_DITHER;
3180                         } else {
3181                                 if (IS_IRONLAKE(dev))
3182                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3183                                 else
3184                                         lvds &= ~LVDS_ENABLE_DITHER;
3185                         }
3186                 }
3187                 I915_WRITE(lvds_reg, lvds);
3188                 I915_READ(lvds_reg);
3189         }
3190         if (is_dp)
3191                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3192
3193         if (!is_edp) {
3194                 I915_WRITE(fp_reg, fp);
3195                 I915_WRITE(dpll_reg, dpll);
3196                 I915_READ(dpll_reg);
3197                 /* Wait for the clocks to stabilize. */
3198                 udelay(150);
3199
3200                 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
3201                         if (is_sdvo) {
3202                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3203                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3204                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3205                         } else
3206                                 I915_WRITE(dpll_md_reg, 0);
3207                 } else {
3208                         /* write it again -- the BIOS does, after all */
3209                         I915_WRITE(dpll_reg, dpll);
3210                 }
3211                 I915_READ(dpll_reg);
3212                 /* Wait for the clocks to stabilize. */
3213                 udelay(150);
3214         }
3215
3216         if (is_lvds && has_reduced_clock && i915_powersave) {
3217                 I915_WRITE(fp_reg + 4, fp2);
3218                 intel_crtc->lowfreq_avail = true;
3219                 if (HAS_PIPE_CXSR(dev)) {
3220                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3221                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3222                 }
3223         } else {
3224                 I915_WRITE(fp_reg + 4, fp);
3225                 intel_crtc->lowfreq_avail = false;
3226                 if (HAS_PIPE_CXSR(dev)) {
3227                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3228                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3229                 }
3230         }
3231
3232         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3233                    ((adjusted_mode->crtc_htotal - 1) << 16));
3234         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3235                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3236         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3237                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3238         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3239                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3240         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3241                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3242         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3243                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3244         /* pipesrc and dspsize control the size that is scaled from, which should
3245          * always be the user's requested size.
3246          */
3247         if (!IS_IRONLAKE(dev)) {
3248                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3249                                 (mode->hdisplay - 1));
3250                 I915_WRITE(dsppos_reg, 0);
3251         }
3252         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3253
3254         if (IS_IRONLAKE(dev)) {
3255                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3256                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3257                 I915_WRITE(link_m1_reg, m_n.link_m);
3258                 I915_WRITE(link_n1_reg, m_n.link_n);
3259
3260                 if (is_edp) {
3261                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3262                 } else {
3263                         /* enable FDI RX PLL too */
3264                         temp = I915_READ(fdi_rx_reg);
3265                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3266                         udelay(200);
3267                 }
3268         }
3269
3270         I915_WRITE(pipeconf_reg, pipeconf);
3271         I915_READ(pipeconf_reg);
3272
3273         intel_wait_for_vblank(dev);
3274
3275         if (IS_IRONLAKE(dev)) {
3276                 /* enable address swizzle for tiling buffer */
3277                 temp = I915_READ(DISP_ARB_CTL);
3278                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3279         }
3280
3281         I915_WRITE(dspcntr_reg, dspcntr);
3282
3283         /* Flush the plane changes */
3284         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3285
3286         if ((IS_I965G(dev) || plane == 0))
3287                 intel_update_fbc(crtc, &crtc->mode);
3288
3289         intel_update_watermarks(dev);
3290
3291         drm_vblank_post_modeset(dev, pipe);
3292
3293         return ret;
3294 }
3295
3296 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3297 void intel_crtc_load_lut(struct drm_crtc *crtc)
3298 {
3299         struct drm_device *dev = crtc->dev;
3300         struct drm_i915_private *dev_priv = dev->dev_private;
3301         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3302         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3303         int i;
3304
3305         /* The clocks have to be on to load the palette. */
3306         if (!crtc->enabled)
3307                 return;
3308
3309         /* use legacy palette for Ironlake */
3310         if (IS_IRONLAKE(dev))
3311                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3312                                                    LGC_PALETTE_B;
3313
3314         for (i = 0; i < 256; i++) {
3315                 I915_WRITE(palreg + 4 * i,
3316                            (intel_crtc->lut_r[i] << 16) |
3317                            (intel_crtc->lut_g[i] << 8) |
3318                            intel_crtc->lut_b[i]);
3319         }
3320 }
3321
3322 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3323                                  struct drm_file *file_priv,
3324                                  uint32_t handle,
3325                                  uint32_t width, uint32_t height)
3326 {
3327         struct drm_device *dev = crtc->dev;
3328         struct drm_i915_private *dev_priv = dev->dev_private;
3329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3330         struct drm_gem_object *bo;
3331         struct drm_i915_gem_object *obj_priv;
3332         int pipe = intel_crtc->pipe;
3333         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3334         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3335         uint32_t temp = I915_READ(control);
3336         size_t addr;
3337         int ret;
3338
3339         DRM_DEBUG_KMS("\n");
3340
3341         /* if we want to turn off the cursor ignore width and height */
3342         if (!handle) {
3343                 DRM_DEBUG_KMS("cursor off\n");
3344                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3345                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3346                         temp |= CURSOR_MODE_DISABLE;
3347                 } else {
3348                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3349                 }
3350                 addr = 0;
3351                 bo = NULL;
3352                 mutex_lock(&dev->struct_mutex);
3353                 goto finish;
3354         }
3355
3356         /* Currently we only support 64x64 cursors */
3357         if (width != 64 || height != 64) {
3358                 DRM_ERROR("we currently only support 64x64 cursors\n");
3359                 return -EINVAL;
3360         }
3361
3362         bo = drm_gem_object_lookup(dev, file_priv, handle);
3363         if (!bo)
3364                 return -ENOENT;
3365
3366         obj_priv = bo->driver_private;
3367
3368         if (bo->size < width * height * 4) {
3369                 DRM_ERROR("buffer is to small\n");
3370                 ret = -ENOMEM;
3371                 goto fail;
3372         }
3373
3374         /* we only need to pin inside GTT if cursor is non-phy */
3375         mutex_lock(&dev->struct_mutex);
3376         if (!dev_priv->info->cursor_needs_physical) {
3377                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3378                 if (ret) {
3379                         DRM_ERROR("failed to pin cursor bo\n");
3380                         goto fail_locked;
3381                 }
3382                 addr = obj_priv->gtt_offset;
3383         } else {
3384                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3385                 if (ret) {
3386                         DRM_ERROR("failed to attach phys object\n");
3387                         goto fail_locked;
3388                 }
3389                 addr = obj_priv->phys_obj->handle->busaddr;
3390         }
3391
3392         if (!IS_I9XX(dev))
3393                 I915_WRITE(CURSIZE, (height << 12) | width);
3394
3395         /* Hooray for CUR*CNTR differences */
3396         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3397                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3398                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3399                 temp |= (pipe << 28); /* Connect to correct pipe */
3400         } else {
3401                 temp &= ~(CURSOR_FORMAT_MASK);
3402                 temp |= CURSOR_ENABLE;
3403                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3404         }
3405
3406  finish:
3407         I915_WRITE(control, temp);
3408         I915_WRITE(base, addr);
3409
3410         if (intel_crtc->cursor_bo) {
3411                 if (dev_priv->info->cursor_needs_physical) {
3412                         if (intel_crtc->cursor_bo != bo)
3413                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3414                 } else
3415                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3416                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3417         }
3418
3419         mutex_unlock(&dev->struct_mutex);
3420
3421         intel_crtc->cursor_addr = addr;
3422         intel_crtc->cursor_bo = bo;
3423
3424         return 0;
3425 fail:
3426         mutex_lock(&dev->struct_mutex);
3427 fail_locked:
3428         drm_gem_object_unreference(bo);
3429         mutex_unlock(&dev->struct_mutex);
3430         return ret;
3431 }
3432
3433 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3434 {
3435         struct drm_device *dev = crtc->dev;
3436         struct drm_i915_private *dev_priv = dev->dev_private;
3437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3438         struct intel_framebuffer *intel_fb;
3439         int pipe = intel_crtc->pipe;
3440         uint32_t temp = 0;
3441         uint32_t adder;
3442
3443         if (crtc->fb) {
3444                 intel_fb = to_intel_framebuffer(crtc->fb);
3445                 intel_mark_busy(dev, intel_fb->obj);
3446         }
3447
3448         if (x < 0) {
3449                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3450                 x = -x;
3451         }
3452         if (y < 0) {
3453                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3454                 y = -y;
3455         }
3456
3457         temp |= x << CURSOR_X_SHIFT;
3458         temp |= y << CURSOR_Y_SHIFT;
3459
3460         adder = intel_crtc->cursor_addr;
3461         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3462         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3463
3464         return 0;
3465 }
3466
3467 /** Sets the color ramps on behalf of RandR */
3468 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3469                                  u16 blue, int regno)
3470 {
3471         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3472
3473         intel_crtc->lut_r[regno] = red >> 8;
3474         intel_crtc->lut_g[regno] = green >> 8;
3475         intel_crtc->lut_b[regno] = blue >> 8;
3476 }
3477
3478 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3479                              u16 *blue, int regno)
3480 {
3481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3482
3483         *red = intel_crtc->lut_r[regno] << 8;
3484         *green = intel_crtc->lut_g[regno] << 8;
3485         *blue = intel_crtc->lut_b[regno] << 8;
3486 }
3487
3488 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3489                                  u16 *blue, uint32_t size)
3490 {
3491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3492         int i;
3493
3494         if (size != 256)
3495                 return;
3496
3497         for (i = 0; i < 256; i++) {
3498                 intel_crtc->lut_r[i] = red[i] >> 8;
3499                 intel_crtc->lut_g[i] = green[i] >> 8;
3500                 intel_crtc->lut_b[i] = blue[i] >> 8;
3501         }
3502
3503         intel_crtc_load_lut(crtc);
3504 }
3505
3506 /**
3507  * Get a pipe with a simple mode set on it for doing load-based monitor
3508  * detection.
3509  *
3510  * It will be up to the load-detect code to adjust the pipe as appropriate for
3511  * its requirements.  The pipe will be connected to no other outputs.
3512  *
3513  * Currently this code will only succeed if there is a pipe with no outputs
3514  * configured for it.  In the future, it could choose to temporarily disable
3515  * some outputs to free up a pipe for its use.
3516  *
3517  * \return crtc, or NULL if no pipes are available.
3518  */
3519
3520 /* VESA 640x480x72Hz mode to set on the pipe */
3521 static struct drm_display_mode load_detect_mode = {
3522         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3523                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3524 };
3525
3526 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3527                                             struct drm_display_mode *mode,
3528                                             int *dpms_mode)
3529 {
3530         struct intel_crtc *intel_crtc;
3531         struct drm_crtc *possible_crtc;
3532         struct drm_crtc *supported_crtc =NULL;
3533         struct drm_encoder *encoder = &intel_output->enc;
3534         struct drm_crtc *crtc = NULL;
3535         struct drm_device *dev = encoder->dev;
3536         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3537         struct drm_crtc_helper_funcs *crtc_funcs;
3538         int i = -1;
3539
3540         /*
3541          * Algorithm gets a little messy:
3542          *   - if the connector already has an assigned crtc, use it (but make
3543          *     sure it's on first)
3544          *   - try to find the first unused crtc that can drive this connector,
3545          *     and use that if we find one
3546          *   - if there are no unused crtcs available, try to use the first
3547          *     one we found that supports the connector
3548          */
3549
3550         /* See if we already have a CRTC for this connector */
3551         if (encoder->crtc) {
3552                 crtc = encoder->crtc;
3553                 /* Make sure the crtc and connector are running */
3554                 intel_crtc = to_intel_crtc(crtc);
3555                 *dpms_mode = intel_crtc->dpms_mode;
3556                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3557                         crtc_funcs = crtc->helper_private;
3558                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3559                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3560                 }
3561                 return crtc;
3562         }
3563
3564         /* Find an unused one (if possible) */
3565         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3566                 i++;
3567                 if (!(encoder->possible_crtcs & (1 << i)))
3568                         continue;
3569                 if (!possible_crtc->enabled) {
3570                         crtc = possible_crtc;
3571                         break;
3572                 }
3573                 if (!supported_crtc)
3574                         supported_crtc = possible_crtc;
3575         }
3576
3577         /*
3578          * If we didn't find an unused CRTC, don't use any.
3579          */
3580         if (!crtc) {
3581                 return NULL;
3582         }
3583
3584         encoder->crtc = crtc;
3585         intel_output->base.encoder = encoder;
3586         intel_output->load_detect_temp = true;
3587
3588         intel_crtc = to_intel_crtc(crtc);
3589         *dpms_mode = intel_crtc->dpms_mode;
3590
3591         if (!crtc->enabled) {
3592                 if (!mode)
3593                         mode = &load_detect_mode;
3594                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3595         } else {
3596                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3597                         crtc_funcs = crtc->helper_private;
3598                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3599                 }
3600
3601                 /* Add this connector to the crtc */
3602                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3603                 encoder_funcs->commit(encoder);
3604         }
3605         /* let the connector get through one full cycle before testing */
3606         intel_wait_for_vblank(dev);
3607
3608         return crtc;
3609 }
3610
3611 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3612 {
3613         struct drm_encoder *encoder = &intel_output->enc;
3614         struct drm_device *dev = encoder->dev;
3615         struct drm_crtc *crtc = encoder->crtc;
3616         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3617         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3618
3619         if (intel_output->load_detect_temp) {
3620                 encoder->crtc = NULL;
3621                 intel_output->base.encoder = NULL;
3622                 intel_output->load_detect_temp = false;
3623                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3624                 drm_helper_disable_unused_functions(dev);
3625         }
3626
3627         /* Switch crtc and output back off if necessary */
3628         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3629                 if (encoder->crtc == crtc)
3630                         encoder_funcs->dpms(encoder, dpms_mode);
3631                 crtc_funcs->dpms(crtc, dpms_mode);
3632         }
3633 }
3634
3635 /* Returns the clock of the currently programmed mode of the given pipe. */
3636 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3637 {
3638         struct drm_i915_private *dev_priv = dev->dev_private;
3639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3640         int pipe = intel_crtc->pipe;
3641         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3642         u32 fp;
3643         intel_clock_t clock;
3644
3645         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3646                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3647         else
3648                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3649
3650         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3651         if (IS_PINEVIEW(dev)) {
3652                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3653                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3654         } else {
3655                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3656                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3657         }
3658
3659         if (IS_I9XX(dev)) {
3660                 if (IS_PINEVIEW(dev))
3661                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3662                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3663                 else
3664                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3665                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3666
3667                 switch (dpll & DPLL_MODE_MASK) {
3668                 case DPLLB_MODE_DAC_SERIAL:
3669                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3670                                 5 : 10;
3671                         break;
3672                 case DPLLB_MODE_LVDS:
3673                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3674                                 7 : 14;
3675                         break;
3676                 default:
3677                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3678                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3679                         return 0;
3680                 }
3681
3682                 /* XXX: Handle the 100Mhz refclk */
3683                 intel_clock(dev, 96000, &clock);
3684         } else {
3685                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3686
3687                 if (is_lvds) {
3688                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3689                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3690                         clock.p2 = 14;
3691
3692                         if ((dpll & PLL_REF_INPUT_MASK) ==
3693                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3694                                 /* XXX: might not be 66MHz */
3695                                 intel_clock(dev, 66000, &clock);
3696                         } else
3697                                 intel_clock(dev, 48000, &clock);
3698                 } else {
3699                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3700                                 clock.p1 = 2;
3701                         else {
3702                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3703                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3704                         }
3705                         if (dpll & PLL_P2_DIVIDE_BY_4)
3706                                 clock.p2 = 4;
3707                         else
3708                                 clock.p2 = 2;
3709
3710                         intel_clock(dev, 48000, &clock);
3711                 }
3712         }
3713
3714         /* XXX: It would be nice to validate the clocks, but we can't reuse
3715          * i830PllIsValid() because it relies on the xf86_config connector
3716          * configuration being accurate, which it isn't necessarily.
3717          */
3718
3719         return clock.dot;
3720 }
3721
3722 /** Returns the currently programmed mode of the given pipe. */
3723 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3724                                              struct drm_crtc *crtc)
3725 {
3726         struct drm_i915_private *dev_priv = dev->dev_private;
3727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3728         int pipe = intel_crtc->pipe;
3729         struct drm_display_mode *mode;
3730         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3731         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3732         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3733         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3734
3735         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3736         if (!mode)
3737                 return NULL;
3738
3739         mode->clock = intel_crtc_clock_get(dev, crtc);
3740         mode->hdisplay = (htot & 0xffff) + 1;
3741         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3742         mode->hsync_start = (hsync & 0xffff) + 1;
3743         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3744         mode->vdisplay = (vtot & 0xffff) + 1;
3745         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3746         mode->vsync_start = (vsync & 0xffff) + 1;
3747         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3748
3749         drm_mode_set_name(mode);
3750         drm_mode_set_crtcinfo(mode, 0);
3751
3752         return mode;
3753 }
3754
3755 #define GPU_IDLE_TIMEOUT 500 /* ms */
3756
3757 /* When this timer fires, we've been idle for awhile */
3758 static void intel_gpu_idle_timer(unsigned long arg)
3759 {
3760         struct drm_device *dev = (struct drm_device *)arg;
3761         drm_i915_private_t *dev_priv = dev->dev_private;
3762
3763         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3764
3765         dev_priv->busy = false;
3766
3767         queue_work(dev_priv->wq, &dev_priv->idle_work);
3768 }
3769
3770 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3771
3772 static void intel_crtc_idle_timer(unsigned long arg)
3773 {
3774         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3775         struct drm_crtc *crtc = &intel_crtc->base;
3776         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3777
3778         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3779
3780         intel_crtc->busy = false;
3781
3782         queue_work(dev_priv->wq, &dev_priv->idle_work);
3783 }
3784
3785 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3786 {
3787         struct drm_device *dev = crtc->dev;
3788         drm_i915_private_t *dev_priv = dev->dev_private;
3789         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3790         int pipe = intel_crtc->pipe;
3791         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3792         int dpll = I915_READ(dpll_reg);
3793
3794         if (IS_IRONLAKE(dev))
3795                 return;
3796
3797         if (!dev_priv->lvds_downclock_avail)
3798                 return;
3799
3800         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3801                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3802
3803                 /* Unlock panel regs */
3804                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3805
3806                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3807                 I915_WRITE(dpll_reg, dpll);
3808                 dpll = I915_READ(dpll_reg);
3809                 intel_wait_for_vblank(dev);
3810                 dpll = I915_READ(dpll_reg);
3811                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3812                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3813
3814                 /* ...and lock them again */
3815                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3816         }
3817
3818         /* Schedule downclock */
3819         if (schedule)
3820                 mod_timer(&intel_crtc->idle_timer, jiffies +
3821                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3822 }
3823
3824 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3825 {
3826         struct drm_device *dev = crtc->dev;
3827         drm_i915_private_t *dev_priv = dev->dev_private;
3828         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3829         int pipe = intel_crtc->pipe;
3830         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3831         int dpll = I915_READ(dpll_reg);
3832
3833         if (IS_IRONLAKE(dev))
3834                 return;
3835
3836         if (!dev_priv->lvds_downclock_avail)
3837                 return;
3838
3839         /*
3840          * Since this is called by a timer, we should never get here in
3841          * the manual case.
3842          */
3843         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3844                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3845
3846                 /* Unlock panel regs */
3847                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3848
3849                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3850                 I915_WRITE(dpll_reg, dpll);
3851                 dpll = I915_READ(dpll_reg);
3852                 intel_wait_for_vblank(dev);
3853                 dpll = I915_READ(dpll_reg);
3854                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3855                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3856
3857                 /* ...and lock them again */
3858                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3859         }
3860
3861 }
3862
3863 /**
3864  * intel_idle_update - adjust clocks for idleness
3865  * @work: work struct
3866  *
3867  * Either the GPU or display (or both) went idle.  Check the busy status
3868  * here and adjust the CRTC and GPU clocks as necessary.
3869  */
3870 static void intel_idle_update(struct work_struct *work)
3871 {
3872         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3873                                                     idle_work);
3874         struct drm_device *dev = dev_priv->dev;
3875         struct drm_crtc *crtc;
3876         struct intel_crtc *intel_crtc;
3877
3878         if (!i915_powersave)
3879                 return;
3880
3881         mutex_lock(&dev->struct_mutex);
3882
3883         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3884                 /* Skip inactive CRTCs */
3885                 if (!crtc->fb)
3886                         continue;
3887
3888                 intel_crtc = to_intel_crtc(crtc);
3889                 if (!intel_crtc->busy)
3890                         intel_decrease_pllclock(crtc);
3891         }
3892
3893         mutex_unlock(&dev->struct_mutex);
3894 }
3895
3896 /**
3897  * intel_mark_busy - mark the GPU and possibly the display busy
3898  * @dev: drm device
3899  * @obj: object we're operating on
3900  *
3901  * Callers can use this function to indicate that the GPU is busy processing
3902  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3903  * buffer), we'll also mark the display as busy, so we know to increase its
3904  * clock frequency.
3905  */
3906 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3907 {
3908         drm_i915_private_t *dev_priv = dev->dev_private;
3909         struct drm_crtc *crtc = NULL;
3910         struct intel_framebuffer *intel_fb;
3911         struct intel_crtc *intel_crtc;
3912
3913         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3914                 return;
3915
3916         if (!dev_priv->busy)
3917                 dev_priv->busy = true;
3918         else
3919                 mod_timer(&dev_priv->idle_timer, jiffies +
3920                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3921
3922         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3923                 if (!crtc->fb)
3924                         continue;
3925
3926                 intel_crtc = to_intel_crtc(crtc);
3927                 intel_fb = to_intel_framebuffer(crtc->fb);
3928                 if (intel_fb->obj == obj) {
3929                         if (!intel_crtc->busy) {
3930                                 /* Non-busy -> busy, upclock */
3931                                 intel_increase_pllclock(crtc, true);
3932                                 intel_crtc->busy = true;
3933                         } else {
3934                                 /* Busy -> busy, put off timer */
3935                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3936                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3937                         }
3938                 }
3939         }
3940 }
3941
3942 static void intel_crtc_destroy(struct drm_crtc *crtc)
3943 {
3944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3945
3946         drm_crtc_cleanup(crtc);
3947         kfree(intel_crtc);
3948 }
3949
3950 struct intel_unpin_work {
3951         struct work_struct work;
3952         struct drm_device *dev;
3953         struct drm_gem_object *obj;
3954         struct drm_pending_vblank_event *event;
3955         int pending;
3956 };
3957
3958 static void intel_unpin_work_fn(struct work_struct *__work)
3959 {
3960         struct intel_unpin_work *work =
3961                 container_of(__work, struct intel_unpin_work, work);
3962
3963         mutex_lock(&work->dev->struct_mutex);
3964         i915_gem_object_unpin(work->obj);
3965         drm_gem_object_unreference(work->obj);
3966         mutex_unlock(&work->dev->struct_mutex);
3967         kfree(work);
3968 }
3969
3970 void intel_finish_page_flip(struct drm_device *dev, int pipe)
3971 {
3972         drm_i915_private_t *dev_priv = dev->dev_private;
3973         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3975         struct intel_unpin_work *work;
3976         struct drm_i915_gem_object *obj_priv;
3977         struct drm_pending_vblank_event *e;
3978         struct timeval now;
3979         unsigned long flags;
3980
3981         /* Ignore early vblank irqs */
3982         if (intel_crtc == NULL)
3983                 return;
3984
3985         spin_lock_irqsave(&dev->event_lock, flags);
3986         work = intel_crtc->unpin_work;
3987         if (work == NULL || !work->pending) {
3988                 spin_unlock_irqrestore(&dev->event_lock, flags);
3989                 return;
3990         }
3991
3992         intel_crtc->unpin_work = NULL;
3993         drm_vblank_put(dev, intel_crtc->pipe);
3994
3995         if (work->event) {
3996                 e = work->event;
3997                 do_gettimeofday(&now);
3998                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
3999                 e->event.tv_sec = now.tv_sec;
4000                 e->event.tv_usec = now.tv_usec;
4001                 list_add_tail(&e->base.link,
4002                               &e->base.file_priv->event_list);
4003                 wake_up_interruptible(&e->base.file_priv->event_wait);
4004         }
4005
4006         spin_unlock_irqrestore(&dev->event_lock, flags);
4007
4008         obj_priv = work->obj->driver_private;
4009         if (atomic_dec_and_test(&obj_priv->pending_flip))
4010                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4011         schedule_work(&work->work);
4012 }
4013
4014 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4015 {
4016         drm_i915_private_t *dev_priv = dev->dev_private;
4017         struct intel_crtc *intel_crtc =
4018                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4019         unsigned long flags;
4020
4021         spin_lock_irqsave(&dev->event_lock, flags);
4022         if (intel_crtc->unpin_work)
4023                 intel_crtc->unpin_work->pending = 1;
4024         spin_unlock_irqrestore(&dev->event_lock, flags);
4025 }
4026
4027 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4028                                 struct drm_framebuffer *fb,
4029                                 struct drm_pending_vblank_event *event)
4030 {
4031         struct drm_device *dev = crtc->dev;
4032         struct drm_i915_private *dev_priv = dev->dev_private;
4033         struct intel_framebuffer *intel_fb;
4034         struct drm_i915_gem_object *obj_priv;
4035         struct drm_gem_object *obj;
4036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4037         struct intel_unpin_work *work;
4038         unsigned long flags;
4039         int ret;
4040         RING_LOCALS;
4041
4042         work = kzalloc(sizeof *work, GFP_KERNEL);
4043         if (work == NULL)
4044                 return -ENOMEM;
4045
4046         mutex_lock(&dev->struct_mutex);
4047
4048         work->event = event;
4049         work->dev = crtc->dev;
4050         intel_fb = to_intel_framebuffer(crtc->fb);
4051         work->obj = intel_fb->obj;
4052         INIT_WORK(&work->work, intel_unpin_work_fn);
4053
4054         /* We borrow the event spin lock for protecting unpin_work */
4055         spin_lock_irqsave(&dev->event_lock, flags);
4056         if (intel_crtc->unpin_work) {
4057                 spin_unlock_irqrestore(&dev->event_lock, flags);
4058                 kfree(work);
4059                 mutex_unlock(&dev->struct_mutex);
4060                 return -EBUSY;
4061         }
4062         intel_crtc->unpin_work = work;
4063         spin_unlock_irqrestore(&dev->event_lock, flags);
4064
4065         intel_fb = to_intel_framebuffer(fb);
4066         obj = intel_fb->obj;
4067
4068         ret = intel_pin_and_fence_fb_obj(dev, obj);
4069         if (ret != 0) {
4070                 kfree(work);
4071                 mutex_unlock(&dev->struct_mutex);
4072                 return ret;
4073         }
4074
4075         /* Reference the old fb object for the scheduled work. */
4076         drm_gem_object_reference(work->obj);
4077
4078         crtc->fb = fb;
4079         i915_gem_object_flush_write_domain(obj);
4080         drm_vblank_get(dev, intel_crtc->pipe);
4081         obj_priv = obj->driver_private;
4082         atomic_inc(&obj_priv->pending_flip);
4083
4084         BEGIN_LP_RING(4);
4085         OUT_RING(MI_DISPLAY_FLIP |
4086                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4087         OUT_RING(fb->pitch);
4088         if (IS_I965G(dev)) {
4089                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4090                 OUT_RING((fb->width << 16) | fb->height);
4091         } else {
4092                 OUT_RING(obj_priv->gtt_offset);
4093                 OUT_RING(MI_NOOP);
4094         }
4095         ADVANCE_LP_RING();
4096
4097         mutex_unlock(&dev->struct_mutex);
4098
4099         return 0;
4100 }
4101
4102 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4103         .dpms = intel_crtc_dpms,
4104         .mode_fixup = intel_crtc_mode_fixup,
4105         .mode_set = intel_crtc_mode_set,
4106         .mode_set_base = intel_pipe_set_base,
4107         .prepare = intel_crtc_prepare,
4108         .commit = intel_crtc_commit,
4109         .load_lut = intel_crtc_load_lut,
4110 };
4111
4112 static const struct drm_crtc_funcs intel_crtc_funcs = {
4113         .cursor_set = intel_crtc_cursor_set,
4114         .cursor_move = intel_crtc_cursor_move,
4115         .gamma_set = intel_crtc_gamma_set,
4116         .set_config = drm_crtc_helper_set_config,
4117         .destroy = intel_crtc_destroy,
4118         .page_flip = intel_crtc_page_flip,
4119 };
4120
4121
4122 static void intel_crtc_init(struct drm_device *dev, int pipe)
4123 {
4124         drm_i915_private_t *dev_priv = dev->dev_private;
4125         struct intel_crtc *intel_crtc;
4126         int i;
4127
4128         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4129         if (intel_crtc == NULL)
4130                 return;
4131
4132         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4133
4134         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4135         intel_crtc->pipe = pipe;
4136         intel_crtc->plane = pipe;
4137         for (i = 0; i < 256; i++) {
4138                 intel_crtc->lut_r[i] = i;
4139                 intel_crtc->lut_g[i] = i;
4140                 intel_crtc->lut_b[i] = i;
4141         }
4142
4143         /* Swap pipes & planes for FBC on pre-965 */
4144         intel_crtc->pipe = pipe;
4145         intel_crtc->plane = pipe;
4146         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4147                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4148                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4149         }
4150
4151         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4152                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4153         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4154         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4155
4156         intel_crtc->cursor_addr = 0;
4157         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4158         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4159
4160         intel_crtc->busy = false;
4161
4162         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4163                     (unsigned long)intel_crtc);
4164 }
4165
4166 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4167                                 struct drm_file *file_priv)
4168 {
4169         drm_i915_private_t *dev_priv = dev->dev_private;
4170         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4171         struct drm_mode_object *drmmode_obj;
4172         struct intel_crtc *crtc;
4173
4174         if (!dev_priv) {
4175                 DRM_ERROR("called with no initialization\n");
4176                 return -EINVAL;
4177         }
4178
4179         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4180                         DRM_MODE_OBJECT_CRTC);
4181
4182         if (!drmmode_obj) {
4183                 DRM_ERROR("no such CRTC id\n");
4184                 return -EINVAL;
4185         }
4186
4187         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4188         pipe_from_crtc_id->pipe = crtc->pipe;
4189
4190         return 0;
4191 }
4192
4193 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4194 {
4195         struct drm_crtc *crtc = NULL;
4196
4197         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4198                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4199                 if (intel_crtc->pipe == pipe)
4200                         break;
4201         }
4202         return crtc;
4203 }
4204
4205 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4206 {
4207         int index_mask = 0;
4208         struct drm_connector *connector;
4209         int entry = 0;
4210
4211         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4212                 struct intel_output *intel_output = to_intel_output(connector);
4213                 if (type_mask & intel_output->clone_mask)
4214                         index_mask |= (1 << entry);
4215                 entry++;
4216         }
4217         return index_mask;
4218 }
4219
4220
4221 static void intel_setup_outputs(struct drm_device *dev)
4222 {
4223         struct drm_i915_private *dev_priv = dev->dev_private;
4224         struct drm_connector *connector;
4225
4226         intel_crt_init(dev);
4227
4228         /* Set up integrated LVDS */
4229         if (IS_MOBILE(dev) && !IS_I830(dev))
4230                 intel_lvds_init(dev);
4231
4232         if (IS_IRONLAKE(dev)) {
4233                 int found;
4234
4235                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4236                         intel_dp_init(dev, DP_A);
4237
4238                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4239                         /* check SDVOB */
4240                         /* found = intel_sdvo_init(dev, HDMIB); */
4241                         found = 0;
4242                         if (!found)
4243                                 intel_hdmi_init(dev, HDMIB);
4244                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4245                                 intel_dp_init(dev, PCH_DP_B);
4246                 }
4247
4248                 if (I915_READ(HDMIC) & PORT_DETECTED)
4249                         intel_hdmi_init(dev, HDMIC);
4250
4251                 if (I915_READ(HDMID) & PORT_DETECTED)
4252                         intel_hdmi_init(dev, HDMID);
4253
4254                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4255                         intel_dp_init(dev, PCH_DP_C);
4256
4257                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4258                         intel_dp_init(dev, PCH_DP_D);
4259
4260         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4261                 bool found = false;
4262
4263                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4264                         DRM_DEBUG_KMS("probing SDVOB\n");
4265                         found = intel_sdvo_init(dev, SDVOB);
4266                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4267                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4268                                 intel_hdmi_init(dev, SDVOB);
4269                         }
4270
4271                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4272                                 DRM_DEBUG_KMS("probing DP_B\n");
4273                                 intel_dp_init(dev, DP_B);
4274                         }
4275                 }
4276
4277                 /* Before G4X SDVOC doesn't have its own detect register */
4278
4279                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4280                         DRM_DEBUG_KMS("probing SDVOC\n");
4281                         found = intel_sdvo_init(dev, SDVOC);
4282                 }
4283
4284                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4285
4286                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4287                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4288                                 intel_hdmi_init(dev, SDVOC);
4289                         }
4290                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4291                                 DRM_DEBUG_KMS("probing DP_C\n");
4292                                 intel_dp_init(dev, DP_C);
4293                         }
4294                 }
4295
4296                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4297                     (I915_READ(DP_D) & DP_DETECTED)) {
4298                         DRM_DEBUG_KMS("probing DP_D\n");
4299                         intel_dp_init(dev, DP_D);
4300                 }
4301         } else if (IS_I8XX(dev))
4302                 intel_dvo_init(dev);
4303
4304         if (SUPPORTS_TV(dev))
4305                 intel_tv_init(dev);
4306
4307         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4308                 struct intel_output *intel_output = to_intel_output(connector);
4309                 struct drm_encoder *encoder = &intel_output->enc;
4310
4311                 encoder->possible_crtcs = intel_output->crtc_mask;
4312                 encoder->possible_clones = intel_connector_clones(dev,
4313                                                 intel_output->clone_mask);
4314         }
4315 }
4316
4317 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4318 {
4319         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4320         struct drm_device *dev = fb->dev;
4321
4322         if (fb->fbdev)
4323                 intelfb_remove(dev, fb);
4324
4325         drm_framebuffer_cleanup(fb);
4326         mutex_lock(&dev->struct_mutex);
4327         drm_gem_object_unreference(intel_fb->obj);
4328         mutex_unlock(&dev->struct_mutex);
4329
4330         kfree(intel_fb);
4331 }
4332
4333 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4334                                                 struct drm_file *file_priv,
4335                                                 unsigned int *handle)
4336 {
4337         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4338         struct drm_gem_object *object = intel_fb->obj;
4339
4340         return drm_gem_handle_create(file_priv, object, handle);
4341 }
4342
4343 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4344         .destroy = intel_user_framebuffer_destroy,
4345         .create_handle = intel_user_framebuffer_create_handle,
4346 };
4347
4348 int intel_framebuffer_create(struct drm_device *dev,
4349                              struct drm_mode_fb_cmd *mode_cmd,
4350                              struct drm_framebuffer **fb,
4351                              struct drm_gem_object *obj)
4352 {
4353         struct intel_framebuffer *intel_fb;
4354         int ret;
4355
4356         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4357         if (!intel_fb)
4358                 return -ENOMEM;
4359
4360         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4361         if (ret) {
4362                 DRM_ERROR("framebuffer init failed %d\n", ret);
4363                 return ret;
4364         }
4365
4366         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4367
4368         intel_fb->obj = obj;
4369
4370         *fb = &intel_fb->base;
4371
4372         return 0;
4373 }
4374
4375
4376 static struct drm_framebuffer *
4377 intel_user_framebuffer_create(struct drm_device *dev,
4378                               struct drm_file *filp,
4379                               struct drm_mode_fb_cmd *mode_cmd)
4380 {
4381         struct drm_gem_object *obj;
4382         struct drm_framebuffer *fb;
4383         int ret;
4384
4385         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4386         if (!obj)
4387                 return NULL;
4388
4389         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4390         if (ret) {
4391                 mutex_lock(&dev->struct_mutex);
4392                 drm_gem_object_unreference(obj);
4393                 mutex_unlock(&dev->struct_mutex);
4394                 return NULL;
4395         }
4396
4397         return fb;
4398 }
4399
4400 static const struct drm_mode_config_funcs intel_mode_funcs = {
4401         .fb_create = intel_user_framebuffer_create,
4402         .fb_changed = intelfb_probe,
4403 };
4404
4405 static struct drm_gem_object *
4406 intel_alloc_power_context(struct drm_device *dev)
4407 {
4408         struct drm_gem_object *pwrctx;
4409         int ret;
4410
4411         pwrctx = drm_gem_object_alloc(dev, 4096);
4412         if (!pwrctx) {
4413                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4414                 return NULL;
4415         }
4416
4417         mutex_lock(&dev->struct_mutex);
4418         ret = i915_gem_object_pin(pwrctx, 4096);
4419         if (ret) {
4420                 DRM_ERROR("failed to pin power context: %d\n", ret);
4421                 goto err_unref;
4422         }
4423
4424         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4425         if (ret) {
4426                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4427                 goto err_unpin;
4428         }
4429         mutex_unlock(&dev->struct_mutex);
4430
4431         return pwrctx;
4432
4433 err_unpin:
4434         i915_gem_object_unpin(pwrctx);
4435 err_unref:
4436         drm_gem_object_unreference(pwrctx);
4437         mutex_unlock(&dev->struct_mutex);
4438         return NULL;
4439 }
4440
4441 void intel_init_clock_gating(struct drm_device *dev)
4442 {
4443         struct drm_i915_private *dev_priv = dev->dev_private;
4444
4445         /*
4446          * Disable clock gating reported to work incorrectly according to the
4447          * specs, but enable as much else as we can.
4448          */
4449         if (IS_IRONLAKE(dev)) {
4450                 return;
4451         } else if (IS_G4X(dev)) {
4452                 uint32_t dspclk_gate;
4453                 I915_WRITE(RENCLK_GATE_D1, 0);
4454                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4455                        GS_UNIT_CLOCK_GATE_DISABLE |
4456                        CL_UNIT_CLOCK_GATE_DISABLE);
4457                 I915_WRITE(RAMCLK_GATE_D, 0);
4458                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4459                         OVRUNIT_CLOCK_GATE_DISABLE |
4460                         OVCUNIT_CLOCK_GATE_DISABLE;
4461                 if (IS_GM45(dev))
4462                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4463                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4464         } else if (IS_I965GM(dev)) {
4465                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4466                 I915_WRITE(RENCLK_GATE_D2, 0);
4467                 I915_WRITE(DSPCLK_GATE_D, 0);
4468                 I915_WRITE(RAMCLK_GATE_D, 0);
4469                 I915_WRITE16(DEUC, 0);
4470         } else if (IS_I965G(dev)) {
4471                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4472                        I965_RCC_CLOCK_GATE_DISABLE |
4473                        I965_RCPB_CLOCK_GATE_DISABLE |
4474                        I965_ISC_CLOCK_GATE_DISABLE |
4475                        I965_FBC_CLOCK_GATE_DISABLE);
4476                 I915_WRITE(RENCLK_GATE_D2, 0);
4477         } else if (IS_I9XX(dev)) {
4478                 u32 dstate = I915_READ(D_STATE);
4479
4480                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4481                         DSTATE_DOT_CLOCK_GATING;
4482                 I915_WRITE(D_STATE, dstate);
4483         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4484                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4485         } else if (IS_I830(dev)) {
4486                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4487         }
4488
4489         /*
4490          * GPU can automatically power down the render unit if given a page
4491          * to save state.
4492          */
4493         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4494                 struct drm_i915_gem_object *obj_priv = NULL;
4495
4496                 if (dev_priv->pwrctx) {
4497                         obj_priv = dev_priv->pwrctx->driver_private;
4498                 } else {
4499                         struct drm_gem_object *pwrctx;
4500
4501                         pwrctx = intel_alloc_power_context(dev);
4502                         if (pwrctx) {
4503                                 dev_priv->pwrctx = pwrctx;
4504                                 obj_priv = pwrctx->driver_private;
4505                         }
4506                 }
4507
4508                 if (obj_priv) {
4509                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4510                         I915_WRITE(MCHBAR_RENDER_STANDBY,
4511                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4512                 }
4513         }
4514 }
4515
4516 /* Set up chip specific display functions */
4517 static void intel_init_display(struct drm_device *dev)
4518 {
4519         struct drm_i915_private *dev_priv = dev->dev_private;
4520
4521         /* We always want a DPMS function */
4522         if (IS_IRONLAKE(dev))
4523                 dev_priv->display.dpms = ironlake_crtc_dpms;
4524         else
4525                 dev_priv->display.dpms = i9xx_crtc_dpms;
4526
4527         /* Only mobile has FBC, leave pointers NULL for other chips */
4528         if (IS_MOBILE(dev)) {
4529                 if (IS_GM45(dev)) {
4530                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4531                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4532                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4533                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4534                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4535                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4536                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4537                 }
4538                 /* 855GM needs testing */
4539         }
4540
4541         /* Returns the core display clock speed */
4542         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4543                 dev_priv->display.get_display_clock_speed =
4544                         i945_get_display_clock_speed;
4545         else if (IS_I915G(dev))
4546                 dev_priv->display.get_display_clock_speed =
4547                         i915_get_display_clock_speed;
4548         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4549                 dev_priv->display.get_display_clock_speed =
4550                         i9xx_misc_get_display_clock_speed;
4551         else if (IS_I915GM(dev))
4552                 dev_priv->display.get_display_clock_speed =
4553                         i915gm_get_display_clock_speed;
4554         else if (IS_I865G(dev))
4555                 dev_priv->display.get_display_clock_speed =
4556                         i865_get_display_clock_speed;
4557         else if (IS_I85X(dev))
4558                 dev_priv->display.get_display_clock_speed =
4559                         i855_get_display_clock_speed;
4560         else /* 852, 830 */
4561                 dev_priv->display.get_display_clock_speed =
4562                         i830_get_display_clock_speed;
4563
4564         /* For FIFO watermark updates */
4565         if (IS_IRONLAKE(dev))
4566                 dev_priv->display.update_wm = NULL;
4567         else if (IS_G4X(dev))
4568                 dev_priv->display.update_wm = g4x_update_wm;
4569         else if (IS_I965G(dev))
4570                 dev_priv->display.update_wm = i965_update_wm;
4571         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4572                 dev_priv->display.update_wm = i9xx_update_wm;
4573                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4574         } else {
4575                 if (IS_I85X(dev))
4576                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4577                 else if (IS_845G(dev))
4578                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4579                 else
4580                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4581                 dev_priv->display.update_wm = i830_update_wm;
4582         }
4583 }
4584
4585 void intel_modeset_init(struct drm_device *dev)
4586 {
4587         struct drm_i915_private *dev_priv = dev->dev_private;
4588         int num_pipe;
4589         int i;
4590
4591         drm_mode_config_init(dev);
4592
4593         dev->mode_config.min_width = 0;
4594         dev->mode_config.min_height = 0;
4595
4596         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4597
4598         intel_init_display(dev);
4599
4600         if (IS_I965G(dev)) {
4601                 dev->mode_config.max_width = 8192;
4602                 dev->mode_config.max_height = 8192;
4603         } else if (IS_I9XX(dev)) {
4604                 dev->mode_config.max_width = 4096;
4605                 dev->mode_config.max_height = 4096;
4606         } else {
4607                 dev->mode_config.max_width = 2048;
4608                 dev->mode_config.max_height = 2048;
4609         }
4610
4611         /* set memory base */
4612         if (IS_I9XX(dev))
4613                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4614         else
4615                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4616
4617         if (IS_MOBILE(dev) || IS_I9XX(dev))
4618                 num_pipe = 2;
4619         else
4620                 num_pipe = 1;
4621         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4622                   num_pipe, num_pipe > 1 ? "s" : "");
4623
4624         if (IS_I85X(dev))
4625                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4626         else if (IS_I9XX(dev) || IS_G4X(dev))
4627                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4628
4629         for (i = 0; i < num_pipe; i++) {
4630                 intel_crtc_init(dev, i);
4631         }
4632
4633         intel_setup_outputs(dev);
4634
4635         intel_init_clock_gating(dev);
4636
4637         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4638         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4639                     (unsigned long)dev);
4640
4641         intel_setup_overlay(dev);
4642
4643         if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4644                                                         dev_priv->fsb_freq,
4645                                                         dev_priv->mem_freq))
4646                 DRM_INFO("failed to find known CxSR latency "
4647                          "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4648                          dev_priv->fsb_freq, dev_priv->mem_freq);
4649 }
4650
4651 void intel_modeset_cleanup(struct drm_device *dev)
4652 {
4653         struct drm_i915_private *dev_priv = dev->dev_private;
4654         struct drm_crtc *crtc;
4655         struct intel_crtc *intel_crtc;
4656
4657         mutex_lock(&dev->struct_mutex);
4658
4659         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4660                 /* Skip inactive CRTCs */
4661                 if (!crtc->fb)
4662                         continue;
4663
4664                 intel_crtc = to_intel_crtc(crtc);
4665                 intel_increase_pllclock(crtc, false);
4666                 del_timer_sync(&intel_crtc->idle_timer);
4667         }
4668
4669         del_timer_sync(&dev_priv->idle_timer);
4670
4671         if (dev_priv->display.disable_fbc)
4672                 dev_priv->display.disable_fbc(dev);
4673
4674         if (dev_priv->pwrctx) {
4675                 struct drm_i915_gem_object *obj_priv;
4676
4677                 obj_priv = dev_priv->pwrctx->driver_private;
4678                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4679                 I915_READ(PWRCTXA);
4680                 i915_gem_object_unpin(dev_priv->pwrctx);
4681                 drm_gem_object_unreference(dev_priv->pwrctx);
4682         }
4683
4684         mutex_unlock(&dev->struct_mutex);
4685
4686         drm_mode_config_cleanup(dev);
4687 }
4688
4689
4690 /* current intel driver doesn't take advantage of encoders
4691    always give back the encoder for the connector
4692 */
4693 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4694 {
4695         struct intel_output *intel_output = to_intel_output(connector);
4696
4697         return &intel_output->enc;
4698 }
4699
4700 /*
4701  * set vga decode state - true == enable VGA decode
4702  */
4703 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4704 {
4705         struct drm_i915_private *dev_priv = dev->dev_private;
4706         u16 gmch_ctrl;
4707
4708         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4709         if (state)
4710                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4711         else
4712                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4713         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4714         return 0;
4715 }