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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "drm_dp_helper.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73 };
  74
  75 #define I8XX_DOT_MIN              25000
  76 #define I8XX_DOT_MAX             350000
  77 #define I8XX_VCO_MIN             930000
  78 #define I8XX_VCO_MAX            1400000
  79 #define I8XX_N_MIN                    3
  80 #define I8XX_N_MAX                   16
  81 #define I8XX_M_MIN                   96
  82 #define I8XX_M_MAX                  140
  83 #define I8XX_M1_MIN                  18
  84 #define I8XX_M1_MAX                  26
  85 #define I8XX_M2_MIN                   6
  86 #define I8XX_M2_MAX                  16
  87 #define I8XX_P_MIN                    4
  88 #define I8XX_P_MAX                  128
  89 #define I8XX_P1_MIN                   2
  90 #define I8XX_P1_MAX                  33
  91 #define I8XX_P1_LVDS_MIN              1
  92 #define I8XX_P1_LVDS_MAX              6
  93 #define I8XX_P2_SLOW                  4
  94 #define I8XX_P2_FAST                  2
  95 #define I8XX_P2_LVDS_SLOW             14
  96 #define I8XX_P2_LVDS_FAST             7
  97 #define I8XX_P2_SLOW_LIMIT       165000
  98
  99 #define I9XX_DOT_MIN              20000
 100 #define I9XX_DOT_MAX             400000
 101 #define I9XX_VCO_MIN            1400000
 102 #define I9XX_VCO_MAX            2800000
 103 #define PINEVIEW_VCO_MIN                1700000
 104 #define PINEVIEW_VCO_MAX                3500000
 105 #define I9XX_N_MIN                    1
 106 #define I9XX_N_MAX                    6
 107 /* Pineview's Ncounter is a ring counter */
 108 #define PINEVIEW_N_MIN                3
 109 #define PINEVIEW_N_MAX                6
 110 #define I9XX_M_MIN                   70
 111 #define I9XX_M_MAX                  120
 112 #define PINEVIEW_M_MIN                2
 113 #define PINEVIEW_M_MAX              256
 114 #define I9XX_M1_MIN                  10
 115 #define I9XX_M1_MAX                  22
 116 #define I9XX_M2_MIN                   5
 117 #define I9XX_M2_MAX                   9
 118 /* Pineview M1 is reserved, and must be 0 */
 119 #define PINEVIEW_M1_MIN               0
 120 #define PINEVIEW_M1_MAX               0
 121 #define PINEVIEW_M2_MIN               0
 122 #define PINEVIEW_M2_MAX               254
 123 #define I9XX_P_SDVO_DAC_MIN           5
 124 #define I9XX_P_SDVO_DAC_MAX          80
 125 #define I9XX_P_LVDS_MIN               7
 126 #define I9XX_P_LVDS_MAX              98
 127 #define PINEVIEW_P_LVDS_MIN                   7
 128 #define PINEVIEW_P_LVDS_MAX                  112
 129 #define I9XX_P1_MIN                   1
 130 #define I9XX_P1_MAX                   8
 131 #define I9XX_P2_SDVO_DAC_SLOW                10
 132 #define I9XX_P2_SDVO_DAC_FAST                 5
 133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 134 #define I9XX_P2_LVDS_SLOW                    14
 135 #define I9XX_P2_LVDS_FAST                     7
 136 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 137
 138 /*The parameter is for SDVO on G4x platform*/
 139 #define G4X_DOT_SDVO_MIN           25000
 140 #define G4X_DOT_SDVO_MAX           270000
 141 #define G4X_VCO_MIN                1750000
 142 #define G4X_VCO_MAX                3500000
 143 #define G4X_N_SDVO_MIN             1
 144 #define G4X_N_SDVO_MAX             4
 145 #define G4X_M_SDVO_MIN             104
 146 #define G4X_M_SDVO_MAX             138
 147 #define G4X_M1_SDVO_MIN            17
 148 #define G4X_M1_SDVO_MAX            23
 149 #define G4X_M2_SDVO_MIN            5
 150 #define G4X_M2_SDVO_MAX            11
 151 #define G4X_P_SDVO_MIN             10
 152 #define G4X_P_SDVO_MAX             30
 153 #define G4X_P1_SDVO_MIN            1
 154 #define G4X_P1_SDVO_MAX            3
 155 #define G4X_P2_SDVO_SLOW           10
 156 #define G4X_P2_SDVO_FAST           10
 157 #define G4X_P2_SDVO_LIMIT          270000
 158
 159 /*The parameter is for HDMI_DAC on G4x platform*/
 160 #define G4X_DOT_HDMI_DAC_MIN           22000
 161 #define G4X_DOT_HDMI_DAC_MAX           400000
 162 #define G4X_N_HDMI_DAC_MIN             1
 163 #define G4X_N_HDMI_DAC_MAX             4
 164 #define G4X_M_HDMI_DAC_MIN             104
 165 #define G4X_M_HDMI_DAC_MAX             138
 166 #define G4X_M1_HDMI_DAC_MIN            16
 167 #define G4X_M1_HDMI_DAC_MAX            23
 168 #define G4X_M2_HDMI_DAC_MIN            5
 169 #define G4X_M2_HDMI_DAC_MAX            11
 170 #define G4X_P_HDMI_DAC_MIN             5
 171 #define G4X_P_HDMI_DAC_MAX             80
 172 #define G4X_P1_HDMI_DAC_MIN            1
 173 #define G4X_P1_HDMI_DAC_MAX            8
 174 #define G4X_P2_HDMI_DAC_SLOW           10
 175 #define G4X_P2_HDMI_DAC_FAST           5
 176 #define G4X_P2_HDMI_DAC_LIMIT          165000
 177
 178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 196
 197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 215
 216 /*The parameter is for DISPLAY PORT on G4x platform*/
 217 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 218 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 219 #define G4X_N_DISPLAY_PORT_MIN             1
 220 #define G4X_N_DISPLAY_PORT_MAX             2
 221 #define G4X_M_DISPLAY_PORT_MIN             97
 222 #define G4X_M_DISPLAY_PORT_MAX             108
 223 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 224 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 225 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 226 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 227 #define G4X_P_DISPLAY_PORT_MIN             10
 228 #define G4X_P_DISPLAY_PORT_MAX             20
 229 #define G4X_P1_DISPLAY_PORT_MIN            1
 230 #define G4X_P1_DISPLAY_PORT_MAX            2
 231 #define G4X_P2_DISPLAY_PORT_SLOW           10
 232 #define G4X_P2_DISPLAY_PORT_FAST           10
 233 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 234
 235 /* Ironlake */
 236 /* as we calculate clock using (register_value + 2) for
 237    N/M1/M2, so here the range value for them is (actual_value-2).
 238  */
 239 #define IRONLAKE_DOT_MIN         25000
 240 #define IRONLAKE_DOT_MAX         350000
 241 #define IRONLAKE_VCO_MIN         1760000
 242 #define IRONLAKE_VCO_MAX         3510000
 243 #define IRONLAKE_M1_MIN          12
 244 #define IRONLAKE_M1_MAX          22
 245 #define IRONLAKE_M2_MIN          5
 246 #define IRONLAKE_M2_MAX          9
 247 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 248
 249 /* We have parameter ranges for different type of outputs. */
 250
 251 /* DAC & HDMI Refclk 120Mhz */
 252 #define IRONLAKE_DAC_N_MIN      1
 253 #define IRONLAKE_DAC_N_MAX      5
 254 #define IRONLAKE_DAC_M_MIN      79
 255 #define IRONLAKE_DAC_M_MAX      127
 256 #define IRONLAKE_DAC_P_MIN      5
 257 #define IRONLAKE_DAC_P_MAX      80
 258 #define IRONLAKE_DAC_P1_MIN     1
 259 #define IRONLAKE_DAC_P1_MAX     8
 260 #define IRONLAKE_DAC_P2_SLOW    10
 261 #define IRONLAKE_DAC_P2_FAST    5
 262
 263 /* LVDS single-channel 120Mhz refclk */
 264 #define IRONLAKE_LVDS_S_N_MIN   1
 265 #define IRONLAKE_LVDS_S_N_MAX   3
 266 #define IRONLAKE_LVDS_S_M_MIN   79
 267 #define IRONLAKE_LVDS_S_M_MAX   118
 268 #define IRONLAKE_LVDS_S_P_MIN   28
 269 #define IRONLAKE_LVDS_S_P_MAX   112
 270 #define IRONLAKE_LVDS_S_P1_MIN  2
 271 #define IRONLAKE_LVDS_S_P1_MAX  8
 272 #define IRONLAKE_LVDS_S_P2_SLOW 14
 273 #define IRONLAKE_LVDS_S_P2_FAST 14
 274
 275 /* LVDS dual-channel 120Mhz refclk */
 276 #define IRONLAKE_LVDS_D_N_MIN   1
 277 #define IRONLAKE_LVDS_D_N_MAX   3
 278 #define IRONLAKE_LVDS_D_M_MIN   79
 279 #define IRONLAKE_LVDS_D_M_MAX   127
 280 #define IRONLAKE_LVDS_D_P_MIN   14
 281 #define IRONLAKE_LVDS_D_P_MAX   56
 282 #define IRONLAKE_LVDS_D_P1_MIN  2
 283 #define IRONLAKE_LVDS_D_P1_MAX  8
 284 #define IRONLAKE_LVDS_D_P2_SLOW 7
 285 #define IRONLAKE_LVDS_D_P2_FAST 7
 286
 287 /* LVDS single-channel 100Mhz refclk */
 288 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 289 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 290 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 291 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 292 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 293 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 294 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 295 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 296 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 297 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 298
 299 /* LVDS dual-channel 100Mhz refclk */
 300 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 301 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 302 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 303 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 304 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 305 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 306 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 307 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 308 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 309 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 310
 311 /* DisplayPort */
 312 #define IRONLAKE_DP_N_MIN               1
 313 #define IRONLAKE_DP_N_MAX               2
 314 #define IRONLAKE_DP_M_MIN               81
 315 #define IRONLAKE_DP_M_MAX               90
 316 #define IRONLAKE_DP_P_MIN               10
 317 #define IRONLAKE_DP_P_MAX               20
 318 #define IRONLAKE_DP_P2_FAST             10
 319 #define IRONLAKE_DP_P2_SLOW             10
 320 #define IRONLAKE_DP_P2_LIMIT            0
 321 #define IRONLAKE_DP_P1_MIN              1
 322 #define IRONLAKE_DP_P1_MAX              2
 323
 324 static bool
 325 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 326                     int target, int refclk, intel_clock_t *best_clock);
 327 static bool
 328 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 329                         int target, int refclk, intel_clock_t *best_clock);
 330
 331 static bool
 332 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 333                       int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 336                            int target, int refclk, intel_clock_t *best_clock);
 337
 338 static const intel_limit_t intel_limits_i8xx_dvo = {
 339         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 340         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 341         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 342         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 343         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 344         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 345         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 346         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 347         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 348                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 349         .find_pll = intel_find_best_PLL,
 350 };
 351
 352 static const intel_limit_t intel_limits_i8xx_lvds = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i9xx_sdvo = {
 367         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 368         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 369         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 370         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 371         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 372         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 373         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 374         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 375         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 376                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_lvds = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         /* The single-channel range is 25-112Mhz, and dual-channel
 390          * is 80-224Mhz.  Prefer single channel as much as possible.
 391          */
 392         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397     /* below parameter and function is for G4X Chipset Family*/
 398 static const intel_limit_t intel_limits_g4x_sdvo = {
 399         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 400         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 401         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 402         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 403         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 404         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 405         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 406         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 407         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 408                  .p2_slow = G4X_P2_SDVO_SLOW,
 409                  .p2_fast = G4X_P2_SDVO_FAST
 410         },
 411         .find_pll = intel_g4x_find_best_PLL,
 412 };
 413
 414 static const intel_limit_t intel_limits_g4x_hdmi = {
 415         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 416         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 417         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 418         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 419         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 420         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 421         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 422         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 423         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 424                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 425                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 426         },
 427         .find_pll = intel_g4x_find_best_PLL,
 428 };
 429
 430 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 431         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 432                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 433         .vco = { .min = G4X_VCO_MIN,
 434                  .max = G4X_VCO_MAX },
 435         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 436                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 437         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 438                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 439         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 440                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 441         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 442                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 443         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 444                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 445         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 447         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 448                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 449                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 450         },
 451         .find_pll = intel_g4x_find_best_PLL,
 452 };
 453
 454 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 455         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 456                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 457         .vco = { .min = G4X_VCO_MIN,
 458                  .max = G4X_VCO_MAX },
 459         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 460                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 461         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 462                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 463         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 464                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 465         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 466                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 467         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 468                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 469         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 471         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 472                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 473                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 474         },
 475         .find_pll = intel_g4x_find_best_PLL,
 476 };
 477
 478 static const intel_limit_t intel_limits_g4x_display_port = {
 479         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 480                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 481         .vco = { .min = G4X_VCO_MIN,
 482                  .max = G4X_VCO_MAX},
 483         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 484                  .max = G4X_N_DISPLAY_PORT_MAX },
 485         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 486                  .max = G4X_M_DISPLAY_PORT_MAX },
 487         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 488                  .max = G4X_M1_DISPLAY_PORT_MAX },
 489         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 490                  .max = G4X_M2_DISPLAY_PORT_MAX },
 491         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 492                  .max = G4X_P_DISPLAY_PORT_MAX },
 493         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 494                  .max = G4X_P1_DISPLAY_PORT_MAX},
 495         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 496                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 497                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 498         .find_pll = intel_find_pll_g4x_dp,
 499 };
 500
 501 static const intel_limit_t intel_limits_pineview_sdvo = {
 502         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 503         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 504         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 505         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 506         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 507         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 508         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 509         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 510         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 511                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 512         .find_pll = intel_find_best_PLL,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_lvds = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         /* Pineview only supports single-channel mode. */
 525         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 526                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 527         .find_pll = intel_find_best_PLL,
 528 };
 529
 530 static const intel_limit_t intel_limits_ironlake_dac = {
 531         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 532         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 533         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 534         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 535         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 536         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 537         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 538         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 539         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 540                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 541                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 542         .find_pll = intel_g4x_find_best_PLL,
 543 };
 544
 545 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 546         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 547         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 548         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 549         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 550         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 551         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 552         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 553         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 554         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 555                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 556                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 557         .find_pll = intel_g4x_find_best_PLL,
 558 };
 559
 560 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 561         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 562         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 563         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 564         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 565         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 566         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 567         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 568         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 569         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 570                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 571                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 572         .find_pll = intel_g4x_find_best_PLL,
 573 };
 574
 575 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 576         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 577         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 578         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 579         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 580         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 581         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 582         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 583         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 584         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 585                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 586                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 587         .find_pll = intel_g4x_find_best_PLL,
 588 };
 589
 590 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 591         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 592         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 593         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 594         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 595         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 596         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 597         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 598         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 599         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 600                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 601                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 602         .find_pll = intel_g4x_find_best_PLL,
 603 };
 604
 605 static const intel_limit_t intel_limits_ironlake_display_port = {
 606         .dot = { .min = IRONLAKE_DOT_MIN,
 607                  .max = IRONLAKE_DOT_MAX },
 608         .vco = { .min = IRONLAKE_VCO_MIN,
 609                  .max = IRONLAKE_VCO_MAX},
 610         .n   = { .min = IRONLAKE_DP_N_MIN,
 611                  .max = IRONLAKE_DP_N_MAX },
 612         .m   = { .min = IRONLAKE_DP_M_MIN,
 613                  .max = IRONLAKE_DP_M_MAX },
 614         .m1  = { .min = IRONLAKE_M1_MIN,
 615                  .max = IRONLAKE_M1_MAX },
 616         .m2  = { .min = IRONLAKE_M2_MIN,
 617                  .max = IRONLAKE_M2_MAX },
 618         .p   = { .min = IRONLAKE_DP_P_MIN,
 619                  .max = IRONLAKE_DP_P_MAX },
 620         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 621                  .max = IRONLAKE_DP_P1_MAX},
 622         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 623                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 624                  .p2_fast = IRONLAKE_DP_P2_FAST },
 625         .find_pll = intel_find_pll_ironlake_dp,
 626 };
 627
 628 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         struct drm_i915_private *dev_priv = dev->dev_private;
 632         const intel_limit_t *limit;
 633         int refclk = 120;
 634
 635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 636                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 637                         refclk = 100;
 638
 639                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 640                     LVDS_CLKB_POWER_UP) {
 641                         /* LVDS dual channel */
 642                         if (refclk == 100)
 643                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 644                         else
 645                                 limit = &intel_limits_ironlake_dual_lvds;
 646                 } else {
 647                         if (refclk == 100)
 648                                 limit = &intel_limits_ironlake_single_lvds_100m;
 649                         else
 650                                 limit = &intel_limits_ironlake_single_lvds;
 651                 }
 652         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 653                         HAS_eDP)
 654                 limit = &intel_limits_ironlake_display_port;
 655         else
 656                 limit = &intel_limits_ironlake_dac;
 657
 658         return limit;
 659 }
 660
 661 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 662 {
 663         struct drm_device *dev = crtc->dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         const intel_limit_t *limit;
 666
 667         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 668                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 669                     LVDS_CLKB_POWER_UP)
 670                         /* LVDS with dual channel */
 671                         limit = &intel_limits_g4x_dual_channel_lvds;
 672                 else
 673                         /* LVDS with dual channel */
 674                         limit = &intel_limits_g4x_single_channel_lvds;
 675         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 676                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 677                 limit = &intel_limits_g4x_hdmi;
 678         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 679                 limit = &intel_limits_g4x_sdvo;
 680         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 681                 limit = &intel_limits_g4x_display_port;
 682         } else /* The option is for other outputs */
 683                 limit = &intel_limits_i9xx_sdvo;
 684
 685         return limit;
 686 }
 687
 688 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         const intel_limit_t *limit;
 692
 693         if (IS_IRONLAKE(dev))
 694                 limit = intel_ironlake_limit(crtc);
 695         else if (IS_G4X(dev)) {
 696                 limit = intel_g4x_limit(crtc);
 697         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 698                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 699                         limit = &intel_limits_i9xx_lvds;
 700                 else
 701                         limit = &intel_limits_i9xx_sdvo;
 702         } else if (IS_PINEVIEW(dev)) {
 703                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 704                         limit = &intel_limits_pineview_lvds;
 705                 else
 706                         limit = &intel_limits_pineview_sdvo;
 707         } else {
 708                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 709                         limit = &intel_limits_i8xx_lvds;
 710                 else
 711                         limit = &intel_limits_i8xx_dvo;
 712         }
 713         return limit;
 714 }
 715
 716 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 717 static void pineview_clock(int refclk, intel_clock_t *clock)
 718 {
 719         clock->m = clock->m2 + 2;
 720         clock->p = clock->p1 * clock->p2;
 721         clock->vco = refclk * clock->m / clock->n;
 722         clock->dot = clock->vco / clock->p;
 723 }
 724
 725 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 726 {
 727         if (IS_PINEVIEW(dev)) {
 728                 pineview_clock(refclk, clock);
 729                 return;
 730         }
 731         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 732         clock->p = clock->p1 * clock->p2;
 733         clock->vco = refclk * clock->m / (clock->n + 2);
 734         clock->dot = clock->vco / clock->p;
 735 }
 736
 737 /**
 738  * Returns whether any output on the specified pipe is of the specified type
 739  */
 740 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 741 {
 742     struct drm_device *dev = crtc->dev;
 743     struct drm_mode_config *mode_config = &dev->mode_config;
 744     struct drm_connector *l_entry;
 745
 746     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 747             if (l_entry->encoder &&
 748                 l_entry->encoder->crtc == crtc) {
 749                     struct intel_output *intel_output = to_intel_output(l_entry);
 750                     if (intel_output->type == type)
 751                             return true;
 752             }
 753     }
 754     return false;
 755 }
 756
 757 struct drm_connector *
 758 intel_pipe_get_output (struct drm_crtc *crtc)
 759 {
 760     struct drm_device *dev = crtc->dev;
 761     struct drm_mode_config *mode_config = &dev->mode_config;
 762     struct drm_connector *l_entry, *ret = NULL;
 763
 764     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 765             if (l_entry->encoder &&
 766                 l_entry->encoder->crtc == crtc) {
 767                     ret = l_entry;
 768                     break;
 769             }
 770     }
 771     return ret;
 772 }
 773
 774 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 775 /**
 776  * Returns whether the given set of divisors are valid for a given refclk with
 777  * the given connectors.
 778  */
 779
 780 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 781 {
 782         const intel_limit_t *limit = intel_limit (crtc);
 783         struct drm_device *dev = crtc->dev;
 784
 785         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 786                 INTELPllInvalid ("p1 out of range\n");
 787         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 788                 INTELPllInvalid ("p out of range\n");
 789         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 790                 INTELPllInvalid ("m2 out of range\n");
 791         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 792                 INTELPllInvalid ("m1 out of range\n");
 793         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 794                 INTELPllInvalid ("m1 <= m2\n");
 795         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 796                 INTELPllInvalid ("m out of range\n");
 797         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 798                 INTELPllInvalid ("n out of range\n");
 799         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 800                 INTELPllInvalid ("vco out of range\n");
 801         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 802          * connector, etc., rather than just a single range.
 803          */
 804         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 805                 INTELPllInvalid ("dot out of range\n");
 806
 807         return true;
 808 }
 809
 810 static bool
 811 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 812                     int target, int refclk, intel_clock_t *best_clock)
 813
 814 {
 815         struct drm_device *dev = crtc->dev;
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         intel_clock_t clock;
 818         int err = target;
 819
 820         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 821             (I915_READ(LVDS)) != 0) {
 822                 /*
 823                  * For LVDS, if the panel is on, just rely on its current
 824                  * settings for dual-channel.  We haven't figured out how to
 825                  * reliably set up different single/dual channel state, if we
 826                  * even can.
 827                  */
 828                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 829                     LVDS_CLKB_POWER_UP)
 830                         clock.p2 = limit->p2.p2_fast;
 831                 else
 832                         clock.p2 = limit->p2.p2_slow;
 833         } else {
 834                 if (target < limit->p2.dot_limit)
 835                         clock.p2 = limit->p2.p2_slow;
 836                 else
 837                         clock.p2 = limit->p2.p2_fast;
 838         }
 839
 840         memset (best_clock, 0, sizeof (*best_clock));
 841
 842         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 843              clock.m1++) {
 844                 for (clock.m2 = limit->m2.min;
 845                      clock.m2 <= limit->m2.max; clock.m2++) {
 846                         /* m1 is always 0 in Pineview */
 847                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 848                                 break;
 849                         for (clock.n = limit->n.min;
 850                              clock.n <= limit->n.max; clock.n++) {
 851                                 for (clock.p1 = limit->p1.min;
 852                                         clock.p1 <= limit->p1.max; clock.p1++) {
 853                                         int this_err;
 854
 855                                         intel_clock(dev, refclk, &clock);
 856
 857                                         if (!intel_PLL_is_valid(crtc, &clock))
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err) {
 862                                                 *best_clock = clock;
 863                                                 err = this_err;
 864                                         }
 865                                 }
 866                         }
 867                 }
 868         }
 869
 870         return (err != target);
 871 }
 872
 873 static bool
 874 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 875                         int target, int refclk, intel_clock_t *best_clock)
 876 {
 877         struct drm_device *dev = crtc->dev;
 878         struct drm_i915_private *dev_priv = dev->dev_private;
 879         intel_clock_t clock;
 880         int max_n;
 881         bool found;
 882         /* approximately equals target * 0.00488 */
 883         int err_most = (target >> 8) + (target >> 10);
 884         found = false;
 885
 886         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 887                 int lvds_reg;
 888
 889                 if (IS_IRONLAKE(dev))
 890                         lvds_reg = PCH_LVDS;
 891                 else
 892                         lvds_reg = LVDS;
 893                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 894                     LVDS_CLKB_POWER_UP)
 895                         clock.p2 = limit->p2.p2_fast;
 896                 else
 897                         clock.p2 = limit->p2.p2_slow;
 898         } else {
 899                 if (target < limit->p2.dot_limit)
 900                         clock.p2 = limit->p2.p2_slow;
 901                 else
 902                         clock.p2 = limit->p2.p2_fast;
 903         }
 904
 905         memset(best_clock, 0, sizeof(*best_clock));
 906         max_n = limit->n.max;
 907         /* based on hardware requriment prefer smaller n to precision */
 908         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 909                 /* based on hardware requirment prefere larger m1,m2 */
 910                 for (clock.m1 = limit->m1.max;
 911                      clock.m1 >= limit->m1.min; clock.m1--) {
 912                         for (clock.m2 = limit->m2.max;
 913                              clock.m2 >= limit->m2.min; clock.m2--) {
 914                                 for (clock.p1 = limit->p1.max;
 915                                      clock.p1 >= limit->p1.min; clock.p1--) {
 916                                         int this_err;
 917
 918                                         intel_clock(dev, refclk, &clock);
 919                                         if (!intel_PLL_is_valid(crtc, &clock))
 920                                                 continue;
 921                                         this_err = abs(clock.dot - target) ;
 922                                         if (this_err < err_most) {
 923                                                 *best_clock = clock;
 924                                                 err_most = this_err;
 925                                                 max_n = clock.n;
 926                                                 found = true;
 927                                         }
 928                                 }
 929                         }
 930                 }
 931         }
 932         return found;
 933 }
 934
 935 static bool
 936 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 937                            int target, int refclk, intel_clock_t *best_clock)
 938 {
 939         struct drm_device *dev = crtc->dev;
 940         intel_clock_t clock;
 941
 942         /* return directly when it is eDP */
 943         if (HAS_eDP)
 944                 return true;
 945
 946         if (target < 200000) {
 947                 clock.n = 1;
 948                 clock.p1 = 2;
 949                 clock.p2 = 10;
 950                 clock.m1 = 12;
 951                 clock.m2 = 9;
 952         } else {
 953                 clock.n = 2;
 954                 clock.p1 = 1;
 955                 clock.p2 = 10;
 956                 clock.m1 = 14;
 957                 clock.m2 = 8;
 958         }
 959         intel_clock(dev, refclk, &clock);
 960         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 961         return true;
 962 }
 963
 964 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 965 static bool
 966 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 967                       int target, int refclk, intel_clock_t *best_clock)
 968 {
 969     intel_clock_t clock;
 970     if (target < 200000) {
 971         clock.p1 = 2;
 972         clock.p2 = 10;
 973         clock.n = 2;
 974         clock.m1 = 23;
 975         clock.m2 = 8;
 976     } else {
 977         clock.p1 = 1;
 978         clock.p2 = 10;
 979         clock.n = 1;
 980         clock.m1 = 14;
 981         clock.m2 = 2;
 982     }
 983     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 984     clock.p = (clock.p1 * clock.p2);
 985     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 986     clock.vco = 0;
 987     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 988     return true;
 989 }
 990
 991 void
 992 intel_wait_for_vblank(struct drm_device *dev)
 993 {
 994         /* Wait for 20ms, i.e. one cycle at 50hz. */
 995         msleep(20);
 996 }
 997
 998 /* Parameters have changed, update FBC info */
 999 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1000 {
1001         struct drm_device *dev = crtc->dev;
1002         struct drm_i915_private *dev_priv = dev->dev_private;
1003         struct drm_framebuffer *fb = crtc->fb;
1004         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1005         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007         int plane, i;
1008         u32 fbc_ctl, fbc_ctl2;
1009
1010         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1011
1012         if (fb->pitch < dev_priv->cfb_pitch)
1013                 dev_priv->cfb_pitch = fb->pitch;
1014
1015         /* FBC_CTL wants 64B units */
1016         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1017         dev_priv->cfb_fence = obj_priv->fence_reg;
1018         dev_priv->cfb_plane = intel_crtc->plane;
1019         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1020
1021         /* Clear old tags */
1022         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1023                 I915_WRITE(FBC_TAG + (i * 4), 0);
1024
1025         /* Set it up... */
1026         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1027         if (obj_priv->tiling_mode != I915_TILING_NONE)
1028                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1029         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1030         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1031
1032         /* enable it... */
1033         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1034         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1035         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1036         if (obj_priv->tiling_mode != I915_TILING_NONE)
1037                 fbc_ctl |= dev_priv->cfb_fence;
1038         I915_WRITE(FBC_CONTROL, fbc_ctl);
1039
1040         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1041                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1042 }
1043
1044 void i8xx_disable_fbc(struct drm_device *dev)
1045 {
1046         struct drm_i915_private *dev_priv = dev->dev_private;
1047         u32 fbc_ctl;
1048
1049         if (!I915_HAS_FBC(dev))
1050                 return;
1051
1052         /* Disable compression */
1053         fbc_ctl = I915_READ(FBC_CONTROL);
1054         fbc_ctl &= ~FBC_CTL_EN;
1055         I915_WRITE(FBC_CONTROL, fbc_ctl);
1056
1057         /* Wait for compressing bit to clear */
1058         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1059                 ; /* nothing */
1060
1061         intel_wait_for_vblank(dev);
1062
1063         DRM_DEBUG_KMS("disabled FBC\n");
1064 }
1065
1066 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1067 {
1068         struct drm_device *dev = crtc->dev;
1069         struct drm_i915_private *dev_priv = dev->dev_private;
1070
1071         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1072 }
1073
1074 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1075 {
1076         struct drm_device *dev = crtc->dev;
1077         struct drm_i915_private *dev_priv = dev->dev_private;
1078         struct drm_framebuffer *fb = crtc->fb;
1079         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1080         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1082         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1083                      DPFC_CTL_PLANEB);
1084         unsigned long stall_watermark = 200;
1085         u32 dpfc_ctl;
1086
1087         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1088         dev_priv->cfb_fence = obj_priv->fence_reg;
1089         dev_priv->cfb_plane = intel_crtc->plane;
1090
1091         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1092         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1093                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1094                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1095         } else {
1096                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1097         }
1098
1099         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1100         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1101                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1102                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1103         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1104
1105         /* enable it... */
1106         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1107
1108         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1109 }
1110
1111 void g4x_disable_fbc(struct drm_device *dev)
1112 {
1113         struct drm_i915_private *dev_priv = dev->dev_private;
1114         u32 dpfc_ctl;
1115
1116         /* Disable compression */
1117         dpfc_ctl = I915_READ(DPFC_CONTROL);
1118         dpfc_ctl &= ~DPFC_CTL_EN;
1119         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1120         intel_wait_for_vblank(dev);
1121
1122         DRM_DEBUG_KMS("disabled FBC\n");
1123 }
1124
1125 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1126 {
1127         struct drm_device *dev = crtc->dev;
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129
1130         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1131 }
1132
1133 /**
1134  * intel_update_fbc - enable/disable FBC as needed
1135  * @crtc: CRTC to point the compressor at
1136  * @mode: mode in use
1137  *
1138  * Set up the framebuffer compression hardware at mode set time.  We
1139  * enable it if possible:
1140  *   - plane A only (on pre-965)
1141  *   - no pixel mulitply/line duplication
1142  *   - no alpha buffer discard
1143  *   - no dual wide
1144  *   - framebuffer <= 2048 in width, 1536 in height
1145  *
1146  * We can't assume that any compression will take place (worst case),
1147  * so the compressed buffer has to be the same size as the uncompressed
1148  * one.  It also must reside (along with the line length buffer) in
1149  * stolen memory.
1150  *
1151  * We need to enable/disable FBC on a global basis.
1152  */
1153 static void intel_update_fbc(struct drm_crtc *crtc,
1154                              struct drm_display_mode *mode)
1155 {
1156         struct drm_device *dev = crtc->dev;
1157         struct drm_i915_private *dev_priv = dev->dev_private;
1158         struct drm_framebuffer *fb = crtc->fb;
1159         struct intel_framebuffer *intel_fb;
1160         struct drm_i915_gem_object *obj_priv;
1161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1162         int plane = intel_crtc->plane;
1163
1164         if (!i915_powersave)
1165                 return;
1166
1167         if (!dev_priv->display.fbc_enabled ||
1168             !dev_priv->display.enable_fbc ||
1169             !dev_priv->display.disable_fbc)
1170                 return;
1171
1172         if (!crtc->fb)
1173                 return;
1174
1175         intel_fb = to_intel_framebuffer(fb);
1176         obj_priv = intel_fb->obj->driver_private;
1177
1178         /*
1179          * If FBC is already on, we just have to verify that we can
1180          * keep it that way...
1181          * Need to disable if:
1182          *   - changing FBC params (stride, fence, mode)
1183          *   - new fb is too large to fit in compressed buffer
1184          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1185          */
1186         if (intel_fb->obj->size > dev_priv->cfb_size) {
1187                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1188                                 "compression\n");
1189                 goto out_disable;
1190         }
1191         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1192             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1193                 DRM_DEBUG_KMS("mode incompatible with compression, "
1194                                 "disabling\n");
1195                 goto out_disable;
1196         }
1197         if ((mode->hdisplay > 2048) ||
1198             (mode->vdisplay > 1536)) {
1199                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1200                 goto out_disable;
1201         }
1202         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1203                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1204                 goto out_disable;
1205         }
1206         if (obj_priv->tiling_mode != I915_TILING_X) {
1207                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1208                 goto out_disable;
1209         }
1210
1211         if (dev_priv->display.fbc_enabled(crtc)) {
1212                 /* We can re-enable it in this case, but need to update pitch */
1213                 if (fb->pitch > dev_priv->cfb_pitch)
1214                         dev_priv->display.disable_fbc(dev);
1215                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1216                         dev_priv->display.disable_fbc(dev);
1217                 if (plane != dev_priv->cfb_plane)
1218                         dev_priv->display.disable_fbc(dev);
1219         }
1220
1221         if (!dev_priv->display.fbc_enabled(crtc)) {
1222                 /* Now try to turn it back on if possible */
1223                 dev_priv->display.enable_fbc(crtc, 500);
1224         }
1225
1226         return;
1227
1228 out_disable:
1229         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1230         /* Multiple disables should be harmless */
1231         if (dev_priv->display.fbc_enabled(crtc))
1232                 dev_priv->display.disable_fbc(dev);
1233 }
1234
1235 static int
1236 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1237 {
1238         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1239         u32 alignment;
1240         int ret;
1241
1242         switch (obj_priv->tiling_mode) {
1243         case I915_TILING_NONE:
1244                 alignment = 64 * 1024;
1245                 break;
1246         case I915_TILING_X:
1247                 /* pin() will align the object as required by fence */
1248                 alignment = 0;
1249                 break;
1250         case I915_TILING_Y:
1251                 /* FIXME: Is this true? */
1252                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1253                 return -EINVAL;
1254         default:
1255                 BUG();
1256         }
1257
1258         ret = i915_gem_object_pin(obj, alignment);
1259         if (ret != 0)
1260                 return ret;
1261
1262         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1263          * fence, whereas 965+ only requires a fence if using
1264          * framebuffer compression.  For simplicity, we always install
1265          * a fence as the cost is not that onerous.
1266          */
1267         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1268             obj_priv->tiling_mode != I915_TILING_NONE) {
1269                 ret = i915_gem_object_get_fence_reg(obj);
1270                 if (ret != 0) {
1271                         i915_gem_object_unpin(obj);
1272                         return ret;
1273                 }
1274         }
1275
1276         return 0;
1277 }
1278
1279 static int
1280 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1281                     struct drm_framebuffer *old_fb)
1282 {
1283         struct drm_device *dev = crtc->dev;
1284         struct drm_i915_private *dev_priv = dev->dev_private;
1285         struct drm_i915_master_private *master_priv;
1286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1287         struct intel_framebuffer *intel_fb;
1288         struct drm_i915_gem_object *obj_priv;
1289         struct drm_gem_object *obj;
1290         int pipe = intel_crtc->pipe;
1291         int plane = intel_crtc->plane;
1292         unsigned long Start, Offset;
1293         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1294         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1295         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1296         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1297         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1298         u32 dspcntr;
1299         int ret;
1300
1301         /* no fb bound */
1302         if (!crtc->fb) {
1303                 DRM_DEBUG_KMS("No FB bound\n");
1304                 return 0;
1305         }
1306
1307         switch (plane) {
1308         case 0:
1309         case 1:
1310                 break;
1311         default:
1312                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1313                 return -EINVAL;
1314         }
1315
1316         intel_fb = to_intel_framebuffer(crtc->fb);
1317         obj = intel_fb->obj;
1318         obj_priv = obj->driver_private;
1319
1320         mutex_lock(&dev->struct_mutex);
1321         ret = intel_pin_and_fence_fb_obj(dev, obj);
1322         if (ret != 0) {
1323                 mutex_unlock(&dev->struct_mutex);
1324                 return ret;
1325         }
1326
1327         ret = i915_gem_object_set_to_display_plane(obj);
1328         if (ret != 0) {
1329                 i915_gem_object_unpin(obj);
1330                 mutex_unlock(&dev->struct_mutex);
1331                 return ret;
1332         }
1333
1334         dspcntr = I915_READ(dspcntr_reg);
1335         /* Mask out pixel format bits in case we change it */
1336         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1337         switch (crtc->fb->bits_per_pixel) {
1338         case 8:
1339                 dspcntr |= DISPPLANE_8BPP;
1340                 break;
1341         case 16:
1342                 if (crtc->fb->depth == 15)
1343                         dspcntr |= DISPPLANE_15_16BPP;
1344                 else
1345                         dspcntr |= DISPPLANE_16BPP;
1346                 break;
1347         case 24:
1348         case 32:
1349                 if (crtc->fb->depth == 30)
1350                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1351                 else
1352                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1353                 break;
1354         default:
1355                 DRM_ERROR("Unknown color depth\n");
1356                 i915_gem_object_unpin(obj);
1357                 mutex_unlock(&dev->struct_mutex);
1358                 return -EINVAL;
1359         }
1360         if (IS_I965G(dev)) {
1361                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1362                         dspcntr |= DISPPLANE_TILED;
1363                 else
1364                         dspcntr &= ~DISPPLANE_TILED;
1365         }
1366
1367         if (IS_IRONLAKE(dev))
1368                 /* must disable */
1369                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1370
1371         I915_WRITE(dspcntr_reg, dspcntr);
1372
1373         Start = obj_priv->gtt_offset;
1374         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1375
1376         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1377         I915_WRITE(dspstride, crtc->fb->pitch);
1378         if (IS_I965G(dev)) {
1379                 I915_WRITE(dspbase, Offset);
1380                 I915_READ(dspbase);
1381                 I915_WRITE(dspsurf, Start);
1382                 I915_READ(dspsurf);
1383                 I915_WRITE(dsptileoff, (y << 16) | x);
1384         } else {
1385                 I915_WRITE(dspbase, Start + Offset);
1386                 I915_READ(dspbase);
1387         }
1388
1389         if ((IS_I965G(dev) || plane == 0))
1390                 intel_update_fbc(crtc, &crtc->mode);
1391
1392         intel_wait_for_vblank(dev);
1393
1394         if (old_fb) {
1395                 intel_fb = to_intel_framebuffer(old_fb);
1396                 obj_priv = intel_fb->obj->driver_private;
1397                 i915_gem_object_unpin(intel_fb->obj);
1398         }
1399         intel_increase_pllclock(crtc, true);
1400
1401         mutex_unlock(&dev->struct_mutex);
1402
1403         if (!dev->primary->master)
1404                 return 0;
1405
1406         master_priv = dev->primary->master->driver_priv;
1407         if (!master_priv->sarea_priv)
1408                 return 0;
1409
1410         if (pipe) {
1411                 master_priv->sarea_priv->pipeB_x = x;
1412                 master_priv->sarea_priv->pipeB_y = y;
1413         } else {
1414                 master_priv->sarea_priv->pipeA_x = x;
1415                 master_priv->sarea_priv->pipeA_y = y;
1416         }
1417
1418         return 0;
1419 }
1420
1421 /* Disable the VGA plane that we never use */
1422 static void i915_disable_vga (struct drm_device *dev)
1423 {
1424         struct drm_i915_private *dev_priv = dev->dev_private;
1425         u8 sr1;
1426         u32 vga_reg;
1427
1428         if (IS_IRONLAKE(dev))
1429                 vga_reg = CPU_VGACNTRL;
1430         else
1431                 vga_reg = VGACNTRL;
1432
1433         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1434                 return;
1435
1436         I915_WRITE8(VGA_SR_INDEX, 1);
1437         sr1 = I915_READ8(VGA_SR_DATA);
1438         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1439         udelay(100);
1440
1441         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1442 }
1443
1444 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1445 {
1446         struct drm_device *dev = crtc->dev;
1447         struct drm_i915_private *dev_priv = dev->dev_private;
1448         u32 dpa_ctl;
1449
1450         DRM_DEBUG_KMS("\n");
1451         dpa_ctl = I915_READ(DP_A);
1452         dpa_ctl &= ~DP_PLL_ENABLE;
1453         I915_WRITE(DP_A, dpa_ctl);
1454 }
1455
1456 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1457 {
1458         struct drm_device *dev = crtc->dev;
1459         struct drm_i915_private *dev_priv = dev->dev_private;
1460         u32 dpa_ctl;
1461
1462         dpa_ctl = I915_READ(DP_A);
1463         dpa_ctl |= DP_PLL_ENABLE;
1464         I915_WRITE(DP_A, dpa_ctl);
1465         udelay(200);
1466 }
1467
1468
1469 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1470 {
1471         struct drm_device *dev = crtc->dev;
1472         struct drm_i915_private *dev_priv = dev->dev_private;
1473         u32 dpa_ctl;
1474
1475         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1476         dpa_ctl = I915_READ(DP_A);
1477         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1478
1479         if (clock < 200000) {
1480                 u32 temp;
1481                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1482                 /* workaround for 160Mhz:
1483                    1) program 0x4600c bits 15:0 = 0x8124
1484                    2) program 0x46010 bit 0 = 1
1485                    3) program 0x46034 bit 24 = 1
1486                    4) program 0x64000 bit 14 = 1
1487                    */
1488                 temp = I915_READ(0x4600c);
1489                 temp &= 0xffff0000;
1490                 I915_WRITE(0x4600c, temp | 0x8124);
1491
1492                 temp = I915_READ(0x46010);
1493                 I915_WRITE(0x46010, temp | 1);
1494
1495                 temp = I915_READ(0x46034);
1496                 I915_WRITE(0x46034, temp | (1 << 24));
1497         } else {
1498                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1499         }
1500         I915_WRITE(DP_A, dpa_ctl);
1501
1502         udelay(500);
1503 }
1504
1505 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1506 {
1507         struct drm_device *dev = crtc->dev;
1508         struct drm_i915_private *dev_priv = dev->dev_private;
1509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1510         int pipe = intel_crtc->pipe;
1511         int plane = intel_crtc->plane;
1512         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1513         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1514         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1515         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1516         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1517         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1518         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1519         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1520         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1521         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1522         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1523         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1524         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1525         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1526         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1527         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1528         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1529         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1530         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1531         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1532         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1533         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1534         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1535         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1536         u32 temp;
1537         int tries = 5, j, n;
1538         u32 pipe_bpc;
1539
1540         temp = I915_READ(pipeconf_reg);
1541         pipe_bpc = temp & PIPE_BPC_MASK;
1542
1543         /* XXX: When our outputs are all unaware of DPMS modes other than off
1544          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1545          */
1546         switch (mode) {
1547         case DRM_MODE_DPMS_ON:
1548         case DRM_MODE_DPMS_STANDBY:
1549         case DRM_MODE_DPMS_SUSPEND:
1550                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1551
1552                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1553                         temp = I915_READ(PCH_LVDS);
1554                         if ((temp & LVDS_PORT_EN) == 0) {
1555                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1556                                 POSTING_READ(PCH_LVDS);
1557                         }
1558                 }
1559
1560                 if (HAS_eDP) {
1561                         /* enable eDP PLL */
1562                         ironlake_enable_pll_edp(crtc);
1563                 } else {
1564                         /* enable PCH DPLL */
1565                         temp = I915_READ(pch_dpll_reg);
1566                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1567                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1568                                 I915_READ(pch_dpll_reg);
1569                         }
1570
1571                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1572                         temp = I915_READ(fdi_rx_reg);
1573                         /*
1574                          * make the BPC in FDI Rx be consistent with that in
1575                          * pipeconf reg.
1576                          */
1577                         temp &= ~(0x7 << 16);
1578                         temp |= (pipe_bpc << 11);
1579                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1580                                         FDI_SEL_PCDCLK |
1581                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1582                         I915_READ(fdi_rx_reg);
1583                         udelay(200);
1584
1585                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1586                         temp = I915_READ(fdi_tx_reg);
1587                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1588                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1589                                 I915_READ(fdi_tx_reg);
1590                                 udelay(100);
1591                         }
1592                 }
1593
1594                 /* Enable panel fitting for LVDS */
1595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1596                         temp = I915_READ(pf_ctl_reg);
1597                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1598
1599                         /* currently full aspect */
1600                         I915_WRITE(pf_win_pos, 0);
1601
1602                         I915_WRITE(pf_win_size,
1603                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1604                                    (dev_priv->panel_fixed_mode->vdisplay));
1605                 }
1606
1607                 /* Enable CPU pipe */
1608                 temp = I915_READ(pipeconf_reg);
1609                 if ((temp & PIPEACONF_ENABLE) == 0) {
1610                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1611                         I915_READ(pipeconf_reg);
1612                         udelay(100);
1613                 }
1614
1615                 /* configure and enable CPU plane */
1616                 temp = I915_READ(dspcntr_reg);
1617                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1618                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1619                         /* Flush the plane changes */
1620                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1621                 }
1622
1623                 if (!HAS_eDP) {
1624                         /* enable CPU FDI TX and PCH FDI RX */
1625                         temp = I915_READ(fdi_tx_reg);
1626                         temp |= FDI_TX_ENABLE;
1627                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1628                         temp &= ~FDI_LINK_TRAIN_NONE;
1629                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1630                         I915_WRITE(fdi_tx_reg, temp);
1631                         I915_READ(fdi_tx_reg);
1632
1633                         temp = I915_READ(fdi_rx_reg);
1634                         temp &= ~FDI_LINK_TRAIN_NONE;
1635                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1636                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1637                         I915_READ(fdi_rx_reg);
1638
1639                         udelay(150);
1640
1641                         /* Train FDI. */
1642                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1643                            for train result */
1644                         temp = I915_READ(fdi_rx_imr_reg);
1645                         temp &= ~FDI_RX_SYMBOL_LOCK;
1646                         temp &= ~FDI_RX_BIT_LOCK;
1647                         I915_WRITE(fdi_rx_imr_reg, temp);
1648                         I915_READ(fdi_rx_imr_reg);
1649                         udelay(150);
1650
1651                         temp = I915_READ(fdi_rx_iir_reg);
1652                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1653
1654                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1655                                 for (j = 0; j < tries; j++) {
1656                                         temp = I915_READ(fdi_rx_iir_reg);
1657                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1658                                                                 temp);
1659                                         if (temp & FDI_RX_BIT_LOCK)
1660                                                 break;
1661                                         udelay(200);
1662                                 }
1663                                 if (j != tries)
1664                                         I915_WRITE(fdi_rx_iir_reg,
1665                                                         temp | FDI_RX_BIT_LOCK);
1666                                 else
1667                                         DRM_DEBUG_KMS("train 1 fail\n");
1668                         } else {
1669                                 I915_WRITE(fdi_rx_iir_reg,
1670                                                 temp | FDI_RX_BIT_LOCK);
1671                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1672                         }
1673                         temp = I915_READ(fdi_tx_reg);
1674                         temp &= ~FDI_LINK_TRAIN_NONE;
1675                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1676                         I915_WRITE(fdi_tx_reg, temp);
1677
1678                         temp = I915_READ(fdi_rx_reg);
1679                         temp &= ~FDI_LINK_TRAIN_NONE;
1680                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1681                         I915_WRITE(fdi_rx_reg, temp);
1682
1683                         udelay(150);
1684
1685                         temp = I915_READ(fdi_rx_iir_reg);
1686                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1687
1688                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1689                                 for (j = 0; j < tries; j++) {
1690                                         temp = I915_READ(fdi_rx_iir_reg);
1691                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1692                                                                 temp);
1693                                         if (temp & FDI_RX_SYMBOL_LOCK)
1694                                                 break;
1695                                         udelay(200);
1696                                 }
1697                                 if (j != tries) {
1698                                         I915_WRITE(fdi_rx_iir_reg,
1699                                                         temp | FDI_RX_SYMBOL_LOCK);
1700                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1701                                 } else
1702                                         DRM_DEBUG_KMS("train 2 fail\n");
1703                         } else {
1704                                 I915_WRITE(fdi_rx_iir_reg,
1705                                                 temp | FDI_RX_SYMBOL_LOCK);
1706                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1707                         }
1708                         DRM_DEBUG_KMS("train done\n");
1709
1710                         /* set transcoder timing */
1711                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1712                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1713                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1714
1715                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1716                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1717                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1718
1719                         /* enable PCH transcoder */
1720                         temp = I915_READ(transconf_reg);
1721                         /*
1722                          * make the BPC in transcoder be consistent with
1723                          * that in pipeconf reg.
1724                          */
1725                         temp &= ~PIPE_BPC_MASK;
1726                         temp |= pipe_bpc;
1727                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1728                         I915_READ(transconf_reg);
1729
1730                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1731                                 ;
1732
1733                         /* enable normal */
1734
1735                         temp = I915_READ(fdi_tx_reg);
1736                         temp &= ~FDI_LINK_TRAIN_NONE;
1737                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1738                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1739                         I915_READ(fdi_tx_reg);
1740
1741                         temp = I915_READ(fdi_rx_reg);
1742                         temp &= ~FDI_LINK_TRAIN_NONE;
1743                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1744                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1745                         I915_READ(fdi_rx_reg);
1746
1747                         /* wait one idle pattern time */
1748                         udelay(100);
1749
1750                 }
1751
1752                 intel_crtc_load_lut(crtc);
1753
1754         break;
1755         case DRM_MODE_DPMS_OFF:
1756                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1757
1758                 drm_vblank_off(dev, pipe);
1759                 /* Disable display plane */
1760                 temp = I915_READ(dspcntr_reg);
1761                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1762                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1763                         /* Flush the plane changes */
1764                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1765                         I915_READ(dspbase_reg);
1766                 }
1767
1768                 i915_disable_vga(dev);
1769
1770                 /* disable cpu pipe, disable after all planes disabled */
1771                 temp = I915_READ(pipeconf_reg);
1772                 if ((temp & PIPEACONF_ENABLE) != 0) {
1773                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1774                         I915_READ(pipeconf_reg);
1775                         n = 0;
1776                         /* wait for cpu pipe off, pipe state */
1777                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1778                                 n++;
1779                                 if (n < 60) {
1780                                         udelay(500);
1781                                         continue;
1782                                 } else {
1783                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1784                                                                 pipe);
1785                                         break;
1786                                 }
1787                         }
1788                 } else
1789                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1790
1791                 udelay(100);
1792
1793                 /* Disable PF */
1794                 temp = I915_READ(pf_ctl_reg);
1795                 if ((temp & PF_ENABLE) != 0) {
1796                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1797                         I915_READ(pf_ctl_reg);
1798                 }
1799                 I915_WRITE(pf_win_size, 0);
1800
1801                 /* disable CPU FDI tx and PCH FDI rx */
1802                 temp = I915_READ(fdi_tx_reg);
1803                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1804                 I915_READ(fdi_tx_reg);
1805
1806                 temp = I915_READ(fdi_rx_reg);
1807                 /* BPC in FDI rx is consistent with that in pipeconf */
1808                 temp &= ~(0x07 << 16);
1809                 temp |= (pipe_bpc << 11);
1810                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1811                 I915_READ(fdi_rx_reg);
1812
1813                 udelay(100);
1814
1815                 /* still set train pattern 1 */
1816                 temp = I915_READ(fdi_tx_reg);
1817                 temp &= ~FDI_LINK_TRAIN_NONE;
1818                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1819                 I915_WRITE(fdi_tx_reg, temp);
1820
1821                 temp = I915_READ(fdi_rx_reg);
1822                 temp &= ~FDI_LINK_TRAIN_NONE;
1823                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1824                 I915_WRITE(fdi_rx_reg, temp);
1825
1826                 udelay(100);
1827
1828                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1829                         temp = I915_READ(PCH_LVDS);
1830                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1831                         I915_READ(PCH_LVDS);
1832                         udelay(100);
1833                 }
1834
1835                 /* disable PCH transcoder */
1836                 temp = I915_READ(transconf_reg);
1837                 if ((temp & TRANS_ENABLE) != 0) {
1838                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1839                         I915_READ(transconf_reg);
1840                         n = 0;
1841                         /* wait for PCH transcoder off, transcoder state */
1842                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1843                                 n++;
1844                                 if (n < 60) {
1845                                         udelay(500);
1846                                         continue;
1847                                 } else {
1848                                         DRM_DEBUG_KMS("transcoder %d off "
1849                                                         "delay\n", pipe);
1850                                         break;
1851                                 }
1852                         }
1853                 }
1854                 temp = I915_READ(transconf_reg);
1855                 /* BPC in transcoder is consistent with that in pipeconf */
1856                 temp &= ~PIPE_BPC_MASK;
1857                 temp |= pipe_bpc;
1858                 I915_WRITE(transconf_reg, temp);
1859                 I915_READ(transconf_reg);
1860                 udelay(100);
1861
1862                 /* disable PCH DPLL */
1863                 temp = I915_READ(pch_dpll_reg);
1864                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1865                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1866                         I915_READ(pch_dpll_reg);
1867                 }
1868
1869                 if (HAS_eDP) {
1870                         ironlake_disable_pll_edp(crtc);
1871                 }
1872
1873                 temp = I915_READ(fdi_rx_reg);
1874                 temp &= ~FDI_SEL_PCDCLK;
1875                 I915_WRITE(fdi_rx_reg, temp);
1876                 I915_READ(fdi_rx_reg);
1877
1878                 temp = I915_READ(fdi_rx_reg);
1879                 temp &= ~FDI_RX_PLL_ENABLE;
1880                 I915_WRITE(fdi_rx_reg, temp);
1881                 I915_READ(fdi_rx_reg);
1882
1883                 /* Disable CPU FDI TX PLL */
1884                 temp = I915_READ(fdi_tx_reg);
1885                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1886                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1887                         I915_READ(fdi_tx_reg);
1888                         udelay(100);
1889                 }
1890
1891                 /* Wait for the clocks to turn off. */
1892                 udelay(100);
1893                 break;
1894         }
1895 }
1896
1897 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1898 {
1899         struct intel_overlay *overlay;
1900         int ret;
1901
1902         if (!enable && intel_crtc->overlay) {
1903                 overlay = intel_crtc->overlay;
1904                 mutex_lock(&overlay->dev->struct_mutex);
1905                 for (;;) {
1906                         ret = intel_overlay_switch_off(overlay);
1907                         if (ret == 0)
1908                                 break;
1909
1910                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1911                         if (ret != 0) {
1912                                 /* overlay doesn't react anymore. Usually
1913                                  * results in a black screen and an unkillable
1914                                  * X server. */
1915                                 BUG();
1916                                 overlay->hw_wedged = HW_WEDGED;
1917                                 break;
1918                         }
1919                 }
1920                 mutex_unlock(&overlay->dev->struct_mutex);
1921         }
1922         /* Let userspace switch the overlay on again. In most cases userspace
1923          * has to recompute where to put it anyway. */
1924
1925         return;
1926 }
1927
1928 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1929 {
1930         struct drm_device *dev = crtc->dev;
1931         struct drm_i915_private *dev_priv = dev->dev_private;
1932         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1933         int pipe = intel_crtc->pipe;
1934         int plane = intel_crtc->plane;
1935         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1936         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1937         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1938         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1939         u32 temp;
1940
1941         /* XXX: When our outputs are all unaware of DPMS modes other than off
1942          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1943          */
1944         switch (mode) {
1945         case DRM_MODE_DPMS_ON:
1946         case DRM_MODE_DPMS_STANDBY:
1947         case DRM_MODE_DPMS_SUSPEND:
1948                 intel_update_watermarks(dev);
1949
1950                 /* Enable the DPLL */
1951                 temp = I915_READ(dpll_reg);
1952                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1953                         I915_WRITE(dpll_reg, temp);
1954                         I915_READ(dpll_reg);
1955                         /* Wait for the clocks to stabilize. */
1956                         udelay(150);
1957                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1958                         I915_READ(dpll_reg);
1959                         /* Wait for the clocks to stabilize. */
1960                         udelay(150);
1961                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1962                         I915_READ(dpll_reg);
1963                         /* Wait for the clocks to stabilize. */
1964                         udelay(150);
1965                 }
1966
1967                 /* Enable the pipe */
1968                 temp = I915_READ(pipeconf_reg);
1969                 if ((temp & PIPEACONF_ENABLE) == 0)
1970                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1971
1972                 /* Enable the plane */
1973                 temp = I915_READ(dspcntr_reg);
1974                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1975                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1976                         /* Flush the plane changes */
1977                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1978                 }
1979
1980                 intel_crtc_load_lut(crtc);
1981
1982                 if ((IS_I965G(dev) || plane == 0))
1983                         intel_update_fbc(crtc, &crtc->mode);
1984
1985                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1986                 intel_crtc_dpms_overlay(intel_crtc, true);
1987         break;
1988         case DRM_MODE_DPMS_OFF:
1989                 intel_update_watermarks(dev);
1990
1991                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1992                 intel_crtc_dpms_overlay(intel_crtc, false);
1993                 drm_vblank_off(dev, pipe);
1994
1995                 if (dev_priv->cfb_plane == plane &&
1996                     dev_priv->display.disable_fbc)
1997                         dev_priv->display.disable_fbc(dev);
1998
1999                 /* Disable the VGA plane that we never use */
2000                 i915_disable_vga(dev);
2001
2002                 /* Disable display plane */
2003                 temp = I915_READ(dspcntr_reg);
2004                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2005                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2006                         /* Flush the plane changes */
2007                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2008                         I915_READ(dspbase_reg);
2009                 }
2010
2011                 if (!IS_I9XX(dev)) {
2012                         /* Wait for vblank for the disable to take effect */
2013                         intel_wait_for_vblank(dev);
2014                 }
2015
2016                 /* Next, disable display pipes */
2017                 temp = I915_READ(pipeconf_reg);
2018                 if ((temp & PIPEACONF_ENABLE) != 0) {
2019                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2020                         I915_READ(pipeconf_reg);
2021                 }
2022
2023                 /* Wait for vblank for the disable to take effect. */
2024                 intel_wait_for_vblank(dev);
2025
2026                 temp = I915_READ(dpll_reg);
2027                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2028                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2029                         I915_READ(dpll_reg);
2030                 }
2031
2032                 /* Wait for the clocks to turn off. */
2033                 udelay(150);
2034                 break;
2035         }
2036 }
2037
2038 /**
2039  * Sets the power management mode of the pipe and plane.
2040  *
2041  * This code should probably grow support for turning the cursor off and back
2042  * on appropriately at the same time as we're turning the pipe off/on.
2043  */
2044 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2045 {
2046         struct drm_device *dev = crtc->dev;
2047         struct drm_i915_private *dev_priv = dev->dev_private;
2048         struct drm_i915_master_private *master_priv;
2049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2050         int pipe = intel_crtc->pipe;
2051         bool enabled;
2052
2053         dev_priv->display.dpms(crtc, mode);
2054
2055         intel_crtc->dpms_mode = mode;
2056
2057         if (!dev->primary->master)
2058                 return;
2059
2060         master_priv = dev->primary->master->driver_priv;
2061         if (!master_priv->sarea_priv)
2062                 return;
2063
2064         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2065
2066         switch (pipe) {
2067         case 0:
2068                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2069                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2070                 break;
2071         case 1:
2072                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2073                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2074                 break;
2075         default:
2076                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2077                 break;
2078         }
2079 }
2080
2081 static void intel_crtc_prepare (struct drm_crtc *crtc)
2082 {
2083         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2084         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2085 }
2086
2087 static void intel_crtc_commit (struct drm_crtc *crtc)
2088 {
2089         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2090         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2091 }
2092
2093 void intel_encoder_prepare (struct drm_encoder *encoder)
2094 {
2095         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2096         /* lvds has its own version of prepare see intel_lvds_prepare */
2097         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2098 }
2099
2100 void intel_encoder_commit (struct drm_encoder *encoder)
2101 {
2102         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2103         /* lvds has its own version of commit see intel_lvds_commit */
2104         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2105 }
2106
2107 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2108                                   struct drm_display_mode *mode,
2109                                   struct drm_display_mode *adjusted_mode)
2110 {
2111         struct drm_device *dev = crtc->dev;
2112         if (IS_IRONLAKE(dev)) {
2113                 /* FDI link clock is fixed at 2.7G */
2114                 if (mode->clock * 3 > 27000 * 4)
2115                         return MODE_CLOCK_HIGH;
2116         }
2117         return true;
2118 }
2119
2120 static int i945_get_display_clock_speed(struct drm_device *dev)
2121 {
2122         return 400000;
2123 }
2124
2125 static int i915_get_display_clock_speed(struct drm_device *dev)
2126 {
2127         return 333000;
2128 }
2129
2130 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2131 {
2132         return 200000;
2133 }
2134
2135 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2136 {
2137         u16 gcfgc = 0;
2138
2139         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2140
2141         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2142                 return 133000;
2143         else {
2144                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2145                 case GC_DISPLAY_CLOCK_333_MHZ:
2146                         return 333000;
2147                 default:
2148                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2149                         return 190000;
2150                 }
2151         }
2152 }
2153
2154 static int i865_get_display_clock_speed(struct drm_device *dev)
2155 {
2156         return 266000;
2157 }
2158
2159 static int i855_get_display_clock_speed(struct drm_device *dev)
2160 {
2161         u16 hpllcc = 0;
2162         /* Assume that the hardware is in the high speed state.  This
2163          * should be the default.
2164          */
2165         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2166         case GC_CLOCK_133_200:
2167         case GC_CLOCK_100_200:
2168                 return 200000;
2169         case GC_CLOCK_166_250:
2170                 return 250000;
2171         case GC_CLOCK_100_133:
2172                 return 133000;
2173         }
2174
2175         /* Shouldn't happen */
2176         return 0;
2177 }
2178
2179 static int i830_get_display_clock_speed(struct drm_device *dev)
2180 {
2181         return 133000;
2182 }
2183
2184 /**
2185  * Return the pipe currently connected to the panel fitter,
2186  * or -1 if the panel fitter is not present or not in use
2187  */
2188 int intel_panel_fitter_pipe (struct drm_device *dev)
2189 {
2190         struct drm_i915_private *dev_priv = dev->dev_private;
2191         u32  pfit_control;
2192
2193         /* i830 doesn't have a panel fitter */
2194         if (IS_I830(dev))
2195                 return -1;
2196
2197         pfit_control = I915_READ(PFIT_CONTROL);
2198
2199         /* See if the panel fitter is in use */
2200         if ((pfit_control & PFIT_ENABLE) == 0)
2201                 return -1;
2202
2203         /* 965 can place panel fitter on either pipe */
2204         if (IS_I965G(dev))
2205                 return (pfit_control >> 29) & 0x3;
2206
2207         /* older chips can only use pipe 1 */
2208         return 1;
2209 }
2210
2211 struct fdi_m_n {
2212         u32        tu;
2213         u32        gmch_m;
2214         u32        gmch_n;
2215         u32        link_m;
2216         u32        link_n;
2217 };
2218
2219 static void
2220 fdi_reduce_ratio(u32 *num, u32 *den)
2221 {
2222         while (*num > 0xffffff || *den > 0xffffff) {
2223                 *num >>= 1;
2224                 *den >>= 1;
2225         }
2226 }
2227
2228 #define DATA_N 0x800000
2229 #define LINK_N 0x80000
2230
2231 static void
2232 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2233                      int link_clock, struct fdi_m_n *m_n)
2234 {
2235         u64 temp;
2236
2237         m_n->tu = 64; /* default size */
2238
2239         temp = (u64) DATA_N * pixel_clock;
2240         temp = div_u64(temp, link_clock);
2241         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2242         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2243         m_n->gmch_n = DATA_N;
2244         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2245
2246         temp = (u64) LINK_N * pixel_clock;
2247         m_n->link_m = div_u64(temp, link_clock);
2248         m_n->link_n = LINK_N;
2249         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2250 }
2251
2252
2253 struct intel_watermark_params {
2254         unsigned long fifo_size;
2255         unsigned long max_wm;
2256         unsigned long default_wm;
2257         unsigned long guard_size;
2258         unsigned long cacheline_size;
2259 };
2260
2261 /* Pineview has different values for various configs */
2262 static struct intel_watermark_params pineview_display_wm = {
2263         PINEVIEW_DISPLAY_FIFO,
2264         PINEVIEW_MAX_WM,
2265         PINEVIEW_DFT_WM,
2266         PINEVIEW_GUARD_WM,
2267         PINEVIEW_FIFO_LINE_SIZE
2268 };
2269 static struct intel_watermark_params pineview_display_hplloff_wm = {
2270         PINEVIEW_DISPLAY_FIFO,
2271         PINEVIEW_MAX_WM,
2272         PINEVIEW_DFT_HPLLOFF_WM,
2273         PINEVIEW_GUARD_WM,
2274         PINEVIEW_FIFO_LINE_SIZE
2275 };
2276 static struct intel_watermark_params pineview_cursor_wm = {
2277         PINEVIEW_CURSOR_FIFO,
2278         PINEVIEW_CURSOR_MAX_WM,
2279         PINEVIEW_CURSOR_DFT_WM,
2280         PINEVIEW_CURSOR_GUARD_WM,
2281         PINEVIEW_FIFO_LINE_SIZE,
2282 };
2283 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2284         PINEVIEW_CURSOR_FIFO,
2285         PINEVIEW_CURSOR_MAX_WM,
2286         PINEVIEW_CURSOR_DFT_WM,
2287         PINEVIEW_CURSOR_GUARD_WM,
2288         PINEVIEW_FIFO_LINE_SIZE
2289 };
2290 static struct intel_watermark_params g4x_wm_info = {
2291         G4X_FIFO_SIZE,
2292         G4X_MAX_WM,
2293         G4X_MAX_WM,
2294         2,
2295         G4X_FIFO_LINE_SIZE,
2296 };
2297 static struct intel_watermark_params i945_wm_info = {
2298         I945_FIFO_SIZE,
2299         I915_MAX_WM,
2300         1,
2301         2,
2302         I915_FIFO_LINE_SIZE
2303 };
2304 static struct intel_watermark_params i915_wm_info = {
2305         I915_FIFO_SIZE,
2306         I915_MAX_WM,
2307         1,
2308         2,
2309         I915_FIFO_LINE_SIZE
2310 };
2311 static struct intel_watermark_params i855_wm_info = {
2312         I855GM_FIFO_SIZE,
2313         I915_MAX_WM,
2314         1,
2315         2,
2316         I830_FIFO_LINE_SIZE
2317 };
2318 static struct intel_watermark_params i830_wm_info = {
2319         I830_FIFO_SIZE,
2320         I915_MAX_WM,
2321         1,
2322         2,
2323         I830_FIFO_LINE_SIZE
2324 };
2325
2326 /**
2327  * intel_calculate_wm - calculate watermark level
2328  * @clock_in_khz: pixel clock
2329  * @wm: chip FIFO params
2330  * @pixel_size: display pixel size
2331  * @latency_ns: memory latency for the platform
2332  *
2333  * Calculate the watermark level (the level at which the display plane will
2334  * start fetching from memory again).  Each chip has a different display
2335  * FIFO size and allocation, so the caller needs to figure that out and pass
2336  * in the correct intel_watermark_params structure.
2337  *
2338  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2339  * on the pixel size.  When it reaches the watermark level, it'll start
2340  * fetching FIFO line sized based chunks from memory until the FIFO fills
2341  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2342  * will occur, and a display engine hang could result.
2343  */
2344 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2345                                         struct intel_watermark_params *wm,
2346                                         int pixel_size,
2347                                         unsigned long latency_ns)
2348 {
2349         long entries_required, wm_size;
2350
2351         /*
2352          * Note: we need to make sure we don't overflow for various clock &
2353          * latency values.
2354          * clocks go from a few thousand to several hundred thousand.
2355          * latency is usually a few thousand
2356          */
2357         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2358                 1000;
2359         entries_required /= wm->cacheline_size;
2360
2361         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2362
2363         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2364
2365         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2366
2367         /* Don't promote wm_size to unsigned... */
2368         if (wm_size > (long)wm->max_wm)
2369                 wm_size = wm->max_wm;
2370         if (wm_size <= 0)
2371                 wm_size = wm->default_wm;
2372         return wm_size;
2373 }
2374
2375 struct cxsr_latency {
2376         int is_desktop;
2377         unsigned long fsb_freq;
2378         unsigned long mem_freq;
2379         unsigned long display_sr;
2380         unsigned long display_hpll_disable;
2381         unsigned long cursor_sr;
2382         unsigned long cursor_hpll_disable;
2383 };
2384
2385 static struct cxsr_latency cxsr_latency_table[] = {
2386         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2387         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2388         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2389
2390         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2391         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2392         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2393
2394         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2395         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2396         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2397
2398         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2399         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2400         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2401
2402         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2403         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2404         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2405
2406         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2407         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2408         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2409 };
2410
2411 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2412                                                    int mem)
2413 {
2414         int i;
2415         struct cxsr_latency *latency;
2416
2417         if (fsb == 0 || mem == 0)
2418                 return NULL;
2419
2420         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2421                 latency = &cxsr_latency_table[i];
2422                 if (is_desktop == latency->is_desktop &&
2423                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2424                         return latency;
2425         }
2426
2427         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2428
2429         return NULL;
2430 }
2431
2432 static void pineview_disable_cxsr(struct drm_device *dev)
2433 {
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         u32 reg;
2436
2437         /* deactivate cxsr */
2438         reg = I915_READ(DSPFW3);
2439         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2440         I915_WRITE(DSPFW3, reg);
2441         DRM_INFO("Big FIFO is disabled\n");
2442 }
2443
2444 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2445                                  int pixel_size)
2446 {
2447         struct drm_i915_private *dev_priv = dev->dev_private;
2448         u32 reg;
2449         unsigned long wm;
2450         struct cxsr_latency *latency;
2451
2452         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2453                 dev_priv->mem_freq);
2454         if (!latency) {
2455                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2456                 pineview_disable_cxsr(dev);
2457                 return;
2458         }
2459
2460         /* Display SR */
2461         wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2462                                 latency->display_sr);
2463         reg = I915_READ(DSPFW1);
2464         reg &= 0x7fffff;
2465         reg |= wm << 23;
2466         I915_WRITE(DSPFW1, reg);
2467         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2468
2469         /* cursor SR */
2470         wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2471                                 latency->cursor_sr);
2472         reg = I915_READ(DSPFW3);
2473         reg &= ~(0x3f << 24);
2474         reg |= (wm & 0x3f) << 24;
2475         I915_WRITE(DSPFW3, reg);
2476
2477         /* Display HPLL off SR */
2478         wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2479                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2480         reg = I915_READ(DSPFW3);
2481         reg &= 0xfffffe00;
2482         reg |= wm & 0x1ff;
2483         I915_WRITE(DSPFW3, reg);
2484
2485         /* cursor HPLL off SR */
2486         wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2487                                 latency->cursor_hpll_disable);
2488         reg = I915_READ(DSPFW3);
2489         reg &= ~(0x3f << 16);
2490         reg |= (wm & 0x3f) << 16;
2491         I915_WRITE(DSPFW3, reg);
2492         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2493
2494         /* activate cxsr */
2495         reg = I915_READ(DSPFW3);
2496         reg |= PINEVIEW_SELF_REFRESH_EN;
2497         I915_WRITE(DSPFW3, reg);
2498
2499         DRM_INFO("Big FIFO is enabled\n");
2500
2501         return;
2502 }
2503
2504 /*
2505  * Latency for FIFO fetches is dependent on several factors:
2506  *   - memory configuration (speed, channels)
2507  *   - chipset
2508  *   - current MCH state
2509  * It can be fairly high in some situations, so here we assume a fairly
2510  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2511  * set this value too high, the FIFO will fetch frequently to stay full)
2512  * and power consumption (set it too low to save power and we might see
2513  * FIFO underruns and display "flicker").
2514  *
2515  * A value of 5us seems to be a good balance; safe for very low end
2516  * platforms but not overly aggressive on lower latency configs.
2517  */
2518 static const int latency_ns = 5000;
2519
2520 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2521 {
2522         struct drm_i915_private *dev_priv = dev->dev_private;
2523         uint32_t dsparb = I915_READ(DSPARB);
2524         int size;
2525
2526         if (plane == 0)
2527                 size = dsparb & 0x7f;
2528         else
2529                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2530                         (dsparb & 0x7f);
2531
2532         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2533                         plane ? "B" : "A", size);
2534
2535         return size;
2536 }
2537
2538 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2539 {
2540         struct drm_i915_private *dev_priv = dev->dev_private;
2541         uint32_t dsparb = I915_READ(DSPARB);
2542         int size;
2543
2544         if (plane == 0)
2545                 size = dsparb & 0x1ff;
2546         else
2547                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2548                         (dsparb & 0x1ff);
2549         size >>= 1; /* Convert to cachelines */
2550
2551         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2552                         plane ? "B" : "A", size);
2553
2554         return size;
2555 }
2556
2557 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2558 {
2559         struct drm_i915_private *dev_priv = dev->dev_private;
2560         uint32_t dsparb = I915_READ(DSPARB);
2561         int size;
2562
2563         size = dsparb & 0x7f;
2564         size >>= 2; /* Convert to cachelines */
2565
2566         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2567                         plane ? "B" : "A",
2568                   size);
2569
2570         return size;
2571 }
2572
2573 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2574 {
2575         struct drm_i915_private *dev_priv = dev->dev_private;
2576         uint32_t dsparb = I915_READ(DSPARB);
2577         int size;
2578
2579         size = dsparb & 0x7f;
2580         size >>= 1; /* Convert to cachelines */
2581
2582         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2583                         plane ? "B" : "A", size);
2584
2585         return size;
2586 }
2587
2588 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2589                           int planeb_clock, int sr_hdisplay, int pixel_size)
2590 {
2591         struct drm_i915_private *dev_priv = dev->dev_private;
2592         int total_size, cacheline_size;
2593         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2594         struct intel_watermark_params planea_params, planeb_params;
2595         unsigned long line_time_us;
2596         int sr_clock, sr_entries = 0, entries_required;
2597
2598         /* Create copies of the base settings for each pipe */
2599         planea_params = planeb_params = g4x_wm_info;
2600
2601         /* Grab a couple of global values before we overwrite them */
2602         total_size = planea_params.fifo_size;
2603         cacheline_size = planea_params.cacheline_size;
2604
2605         /*
2606          * Note: we need to make sure we don't overflow for various clock &
2607          * latency values.
2608          * clocks go from a few thousand to several hundred thousand.
2609          * latency is usually a few thousand
2610          */
2611         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2612                 1000;
2613         entries_required /= G4X_FIFO_LINE_SIZE;
2614         planea_wm = entries_required + planea_params.guard_size;
2615
2616         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2617                 1000;
2618         entries_required /= G4X_FIFO_LINE_SIZE;
2619         planeb_wm = entries_required + planeb_params.guard_size;
2620
2621         cursora_wm = cursorb_wm = 16;
2622         cursor_sr = 32;
2623
2624         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2625
2626         /* Calc sr entries for one plane configs */
2627         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2628                 /* self-refresh has much higher latency */
2629                 static const int sr_latency_ns = 12000;
2630
2631                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2632                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2633
2634                 /* Use ns/us then divide to preserve precision */
2635                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2636                               pixel_size * sr_hdisplay) / 1000;
2637                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2638                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2639                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2640         } else {
2641                 /* Turn off self refresh if both pipes are enabled */
2642                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2643                                         & ~FW_BLC_SELF_EN);
2644         }
2645
2646         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2647                   planea_wm, planeb_wm, sr_entries);
2648
2649         planea_wm &= 0x3f;
2650         planeb_wm &= 0x3f;
2651
2652         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2653                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2654                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2655         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2656                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2657         /* HPLL off in SR has some issues on G4x... disable it */
2658         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2659                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2660 }
2661
2662 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2663                            int planeb_clock, int sr_hdisplay, int pixel_size)
2664 {
2665         struct drm_i915_private *dev_priv = dev->dev_private;
2666         unsigned long line_time_us;
2667         int sr_clock, sr_entries, srwm = 1;
2668
2669         /* Calc sr entries for one plane configs */
2670         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2671                 /* self-refresh has much higher latency */
2672                 static const int sr_latency_ns = 12000;
2673
2674                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2675                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2676
2677                 /* Use ns/us then divide to preserve precision */
2678                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2679                               pixel_size * sr_hdisplay) / 1000;
2680                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2681                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2682                 srwm = I945_FIFO_SIZE - sr_entries;
2683                 if (srwm < 0)
2684                         srwm = 1;
2685                 srwm &= 0x3f;
2686                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2687         } else {
2688                 /* Turn off self refresh if both pipes are enabled */
2689                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2690                                         & ~FW_BLC_SELF_EN);
2691         }
2692
2693         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2694                       srwm);
2695
2696         /* 965 has limitations... */
2697         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2698                    (8 << 0));
2699         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2700 }
2701
2702 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2703                            int planeb_clock, int sr_hdisplay, int pixel_size)
2704 {
2705         struct drm_i915_private *dev_priv = dev->dev_private;
2706         uint32_t fwater_lo;
2707         uint32_t fwater_hi;
2708         int total_size, cacheline_size, cwm, srwm = 1;
2709         int planea_wm, planeb_wm;
2710         struct intel_watermark_params planea_params, planeb_params;
2711         unsigned long line_time_us;
2712         int sr_clock, sr_entries = 0;
2713
2714         /* Create copies of the base settings for each pipe */
2715         if (IS_I965GM(dev) || IS_I945GM(dev))
2716                 planea_params = planeb_params = i945_wm_info;
2717         else if (IS_I9XX(dev))
2718                 planea_params = planeb_params = i915_wm_info;
2719         else
2720                 planea_params = planeb_params = i855_wm_info;
2721
2722         /* Grab a couple of global values before we overwrite them */
2723         total_size = planea_params.fifo_size;
2724         cacheline_size = planea_params.cacheline_size;
2725
2726         /* Update per-plane FIFO sizes */
2727         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2728         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2729
2730         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2731                                        pixel_size, latency_ns);
2732         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2733                                        pixel_size, latency_ns);
2734         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2735
2736         /*
2737          * Overlay gets an aggressive default since video jitter is bad.
2738          */
2739         cwm = 2;
2740
2741         /* Calc sr entries for one plane configs */
2742         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2743             (!planea_clock || !planeb_clock)) {
2744                 /* self-refresh has much higher latency */
2745                 static const int sr_latency_ns = 6000;
2746
2747                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2748                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2749
2750                 /* Use ns/us then divide to preserve precision */
2751                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2752                               pixel_size * sr_hdisplay) / 1000;
2753                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2754                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2755                 srwm = total_size - sr_entries;
2756                 if (srwm < 0)
2757                         srwm = 1;
2758                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2759         } else {
2760                 /* Turn off self refresh if both pipes are enabled */
2761                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2762                                         & ~FW_BLC_SELF_EN);
2763         }
2764
2765         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2766                   planea_wm, planeb_wm, cwm, srwm);
2767
2768         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2769         fwater_hi = (cwm & 0x1f);
2770
2771         /* Set request length to 8 cachelines per fetch */
2772         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2773         fwater_hi = fwater_hi | (1 << 8);
2774
2775         I915_WRITE(FW_BLC, fwater_lo);
2776         I915_WRITE(FW_BLC2, fwater_hi);
2777 }
2778
2779 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2780                            int unused2, int pixel_size)
2781 {
2782         struct drm_i915_private *dev_priv = dev->dev_private;
2783         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2784         int planea_wm;
2785
2786         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2787
2788         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2789                                        pixel_size, latency_ns);
2790         fwater_lo |= (3<<8) | planea_wm;
2791
2792         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2793
2794         I915_WRITE(FW_BLC, fwater_lo);
2795 }
2796
2797 /**
2798  * intel_update_watermarks - update FIFO watermark values based on current modes
2799  *
2800  * Calculate watermark values for the various WM regs based on current mode
2801  * and plane configuration.
2802  *
2803  * There are several cases to deal with here:
2804  *   - normal (i.e. non-self-refresh)
2805  *   - self-refresh (SR) mode
2806  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2807  *   - lines are small relative to FIFO size (buffer can hold more than 2
2808  *     lines), so need to account for TLB latency
2809  *
2810  *   The normal calculation is:
2811  *     watermark = dotclock * bytes per pixel * latency
2812  *   where latency is platform & configuration dependent (we assume pessimal
2813  *   values here).
2814  *
2815  *   The SR calculation is:
2816  *     watermark = (trunc(latency/line time)+1) * surface width *
2817  *       bytes per pixel
2818  *   where
2819  *     line time = htotal / dotclock
2820  *   and latency is assumed to be high, as above.
2821  *
2822  * The final value programmed to the register should always be rounded up,
2823  * and include an extra 2 entries to account for clock crossings.
2824  *
2825  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2826  * to set the non-SR watermarks to 8.
2827   */
2828 static void intel_update_watermarks(struct drm_device *dev)
2829 {
2830         struct drm_i915_private *dev_priv = dev->dev_private;
2831         struct drm_crtc *crtc;
2832         struct intel_crtc *intel_crtc;
2833         int sr_hdisplay = 0;
2834         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2835         int enabled = 0, pixel_size = 0;
2836
2837         if (!dev_priv->display.update_wm)
2838                 return;
2839
2840         /* Get the clock config from both planes */
2841         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2842                 intel_crtc = to_intel_crtc(crtc);
2843                 if (crtc->enabled) {
2844                         enabled++;
2845                         if (intel_crtc->plane == 0) {
2846                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2847                                           intel_crtc->pipe, crtc->mode.clock);
2848                                 planea_clock = crtc->mode.clock;
2849                         } else {
2850                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2851                                           intel_crtc->pipe, crtc->mode.clock);
2852                                 planeb_clock = crtc->mode.clock;
2853                         }
2854                         sr_hdisplay = crtc->mode.hdisplay;
2855                         sr_clock = crtc->mode.clock;
2856                         if (crtc->fb)
2857                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2858                         else
2859                                 pixel_size = 4; /* by default */
2860                 }
2861         }
2862
2863         if (enabled <= 0)
2864                 return;
2865
2866         /* Single plane configs can enable self refresh */
2867         if (enabled == 1 && IS_PINEVIEW(dev))
2868                 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2869         else if (IS_PINEVIEW(dev))
2870                 pineview_disable_cxsr(dev);
2871
2872         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2873                                     sr_hdisplay, pixel_size);
2874 }
2875
2876 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2877                                struct drm_display_mode *mode,
2878                                struct drm_display_mode *adjusted_mode,
2879                                int x, int y,
2880                                struct drm_framebuffer *old_fb)
2881 {
2882         struct drm_device *dev = crtc->dev;
2883         struct drm_i915_private *dev_priv = dev->dev_private;
2884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885         int pipe = intel_crtc->pipe;
2886         int plane = intel_crtc->plane;
2887         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2888         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2889         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2890         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2891         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2892         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2893         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2894         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2895         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2896         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2897         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2898         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2899         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2900         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2901         int refclk, num_outputs = 0;
2902         intel_clock_t clock, reduced_clock;
2903         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2904         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2905         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2906         bool is_edp = false;
2907         struct drm_mode_config *mode_config = &dev->mode_config;
2908         struct drm_connector *connector;
2909         const intel_limit_t *limit;
2910         int ret;
2911         struct fdi_m_n m_n = {0};
2912         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2913         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2914         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2915         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2916         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2917         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2918         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2919         int lvds_reg = LVDS;
2920         u32 temp;
2921         int sdvo_pixel_multiply;
2922         int target_clock;
2923
2924         drm_vblank_pre_modeset(dev, pipe);
2925
2926         list_for_each_entry(connector, &mode_config->connector_list, head) {
2927                 struct intel_output *intel_output = to_intel_output(connector);
2928
2929                 if (!connector->encoder || connector->encoder->crtc != crtc)
2930                         continue;
2931
2932                 switch (intel_output->type) {
2933                 case INTEL_OUTPUT_LVDS:
2934                         is_lvds = true;
2935                         break;
2936                 case INTEL_OUTPUT_SDVO:
2937                 case INTEL_OUTPUT_HDMI:
2938                         is_sdvo = true;
2939                         if (intel_output->needs_tv_clock)
2940                                 is_tv = true;
2941                         break;
2942                 case INTEL_OUTPUT_DVO:
2943                         is_dvo = true;
2944                         break;
2945                 case INTEL_OUTPUT_TVOUT:
2946                         is_tv = true;
2947                         break;
2948                 case INTEL_OUTPUT_ANALOG:
2949                         is_crt = true;
2950                         break;
2951                 case INTEL_OUTPUT_DISPLAYPORT:
2952                         is_dp = true;
2953                         break;
2954                 case INTEL_OUTPUT_EDP:
2955                         is_edp = true;
2956                         break;
2957                 }
2958
2959                 num_outputs++;
2960         }
2961
2962         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2963                 refclk = dev_priv->lvds_ssc_freq * 1000;
2964                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2965                                         refclk / 1000);
2966         } else if (IS_I9XX(dev)) {
2967                 refclk = 96000;
2968                 if (IS_IRONLAKE(dev))
2969                         refclk = 120000; /* 120Mhz refclk */
2970         } else {
2971                 refclk = 48000;
2972         }
2973
2974
2975         /*
2976          * Returns a set of divisors for the desired target clock with the given
2977          * refclk, or FALSE.  The returned values represent the clock equation:
2978          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2979          */
2980         limit = intel_limit(crtc);
2981         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2982         if (!ok) {
2983                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2984                 drm_vblank_post_modeset(dev, pipe);
2985                 return -EINVAL;
2986         }
2987
2988         if (is_lvds && dev_priv->lvds_downclock_avail) {
2989                 has_reduced_clock = limit->find_pll(limit, crtc,
2990                                                             dev_priv->lvds_downclock,
2991                                                             refclk,
2992                                                             &reduced_clock);
2993                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2994                         /*
2995                          * If the different P is found, it means that we can't
2996                          * switch the display clock by using the FP0/FP1.
2997                          * In such case we will disable the LVDS downclock
2998                          * feature.
2999                          */
3000                         DRM_DEBUG_KMS("Different P is found for "
3001                                                 "LVDS clock/downclock\n");
3002                         has_reduced_clock = 0;
3003                 }
3004         }
3005         /* SDVO TV has fixed PLL values depend on its clock range,
3006            this mirrors vbios setting. */
3007         if (is_sdvo && is_tv) {
3008                 if (adjusted_mode->clock >= 100000
3009                                 && adjusted_mode->clock < 140500) {
3010                         clock.p1 = 2;
3011                         clock.p2 = 10;
3012                         clock.n = 3;
3013                         clock.m1 = 16;
3014                         clock.m2 = 8;
3015                 } else if (adjusted_mode->clock >= 140500
3016                                 && adjusted_mode->clock <= 200000) {
3017                         clock.p1 = 1;
3018                         clock.p2 = 10;
3019                         clock.n = 6;
3020                         clock.m1 = 12;
3021                         clock.m2 = 8;
3022                 }
3023         }
3024
3025         /* FDI link */
3026         if (IS_IRONLAKE(dev)) {
3027                 int lane, link_bw, bpp;
3028                 /* eDP doesn't require FDI link, so just set DP M/N
3029                    according to current link config */
3030                 if (is_edp) {
3031                         struct drm_connector *edp;
3032                         target_clock = mode->clock;
3033                         edp = intel_pipe_get_output(crtc);
3034                         intel_edp_link_config(to_intel_output(edp),
3035                                         &lane, &link_bw);
3036                 } else {
3037                         /* DP over FDI requires target mode clock
3038                            instead of link clock */
3039                         if (is_dp)
3040                                 target_clock = mode->clock;
3041                         else
3042                                 target_clock = adjusted_mode->clock;
3043                         lane = 4;
3044                         link_bw = 270000;
3045                 }
3046
3047                 /* determine panel color depth */
3048                 temp = I915_READ(pipeconf_reg);
3049                 temp &= ~PIPE_BPC_MASK;
3050                 if (is_lvds) {
3051                         int lvds_reg = I915_READ(PCH_LVDS);
3052                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3053                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3054                                 temp |= PIPE_8BPC;
3055                         else
3056                                 temp |= PIPE_6BPC;
3057                 } else if (is_edp) {
3058                         switch (dev_priv->edp_bpp/3) {
3059                         case 8:
3060                                 temp |= PIPE_8BPC;
3061                                 break;
3062                         case 10:
3063                                 temp |= PIPE_10BPC;
3064                                 break;
3065                         case 6:
3066                                 temp |= PIPE_6BPC;
3067                                 break;
3068                         case 12:
3069                                 temp |= PIPE_12BPC;
3070                                 break;
3071                         }
3072                 } else
3073                         temp |= PIPE_8BPC;
3074                 I915_WRITE(pipeconf_reg, temp);
3075                 I915_READ(pipeconf_reg);
3076
3077                 switch (temp & PIPE_BPC_MASK) {
3078                 case PIPE_8BPC:
3079                         bpp = 24;
3080                         break;
3081                 case PIPE_10BPC:
3082                         bpp = 30;
3083                         break;
3084                 case PIPE_6BPC:
3085                         bpp = 18;
3086                         break;
3087                 case PIPE_12BPC:
3088                         bpp = 36;
3089                         break;
3090                 default:
3091                         DRM_ERROR("unknown pipe bpc value\n");
3092                         bpp = 24;
3093                 }
3094
3095                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3096         }
3097
3098         /* Ironlake: try to setup display ref clock before DPLL
3099          * enabling. This is only under driver's control after
3100          * PCH B stepping, previous chipset stepping should be
3101          * ignoring this setting.
3102          */
3103         if (IS_IRONLAKE(dev)) {
3104                 temp = I915_READ(PCH_DREF_CONTROL);
3105                 /* Always enable nonspread source */
3106                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3107                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3108                 I915_WRITE(PCH_DREF_CONTROL, temp);
3109                 POSTING_READ(PCH_DREF_CONTROL);
3110
3111                 temp &= ~DREF_SSC_SOURCE_MASK;
3112                 temp |= DREF_SSC_SOURCE_ENABLE;
3113                 I915_WRITE(PCH_DREF_CONTROL, temp);
3114                 POSTING_READ(PCH_DREF_CONTROL);
3115
3116                 udelay(200);
3117
3118                 if (is_edp) {
3119                         if (dev_priv->lvds_use_ssc) {
3120                                 temp |= DREF_SSC1_ENABLE;
3121                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3122                                 POSTING_READ(PCH_DREF_CONTROL);
3123
3124                                 udelay(200);
3125
3126                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3127                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3128                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3129                                 POSTING_READ(PCH_DREF_CONTROL);
3130                         } else {
3131                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3132                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3133                                 POSTING_READ(PCH_DREF_CONTROL);
3134                         }
3135                 }
3136         }
3137
3138         if (IS_PINEVIEW(dev)) {
3139                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3140                 if (has_reduced_clock)
3141                         fp2 = (1 << reduced_clock.n) << 16 |
3142                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3143         } else {
3144                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3145                 if (has_reduced_clock)
3146                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3147                                 reduced_clock.m2;
3148         }
3149
3150         if (!IS_IRONLAKE(dev))
3151                 dpll = DPLL_VGA_MODE_DIS;
3152
3153         if (IS_I9XX(dev)) {
3154                 if (is_lvds)
3155                         dpll |= DPLLB_MODE_LVDS;
3156                 else
3157                         dpll |= DPLLB_MODE_DAC_SERIAL;
3158                 if (is_sdvo) {
3159                         dpll |= DPLL_DVO_HIGH_SPEED;
3160                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3161                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3162                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3163                         else if (IS_IRONLAKE(dev))
3164                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3165                 }
3166                 if (is_dp)
3167                         dpll |= DPLL_DVO_HIGH_SPEED;
3168
3169                 /* compute bitmask from p1 value */
3170                 if (IS_PINEVIEW(dev))
3171                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3172                 else {
3173                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3174                         /* also FPA1 */
3175                         if (IS_IRONLAKE(dev))
3176                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3177                         if (IS_G4X(dev) && has_reduced_clock)
3178                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3179                 }
3180                 switch (clock.p2) {
3181                 case 5:
3182                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3183                         break;
3184                 case 7:
3185                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3186                         break;
3187                 case 10:
3188                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3189                         break;
3190                 case 14:
3191                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3192                         break;
3193                 }
3194                 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
3195                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3196         } else {
3197                 if (is_lvds) {
3198                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3199                 } else {
3200                         if (clock.p1 == 2)
3201                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3202                         else
3203                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3204                         if (clock.p2 == 4)
3205                                 dpll |= PLL_P2_DIVIDE_BY_4;
3206                 }
3207         }
3208
3209         if (is_sdvo && is_tv)
3210                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3211         else if (is_tv)
3212                 /* XXX: just matching BIOS for now */
3213                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3214                 dpll |= 3;
3215         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3216                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3217         else
3218                 dpll |= PLL_REF_INPUT_DREFCLK;
3219
3220         /* setup pipeconf */
3221         pipeconf = I915_READ(pipeconf_reg);
3222
3223         /* Set up the display plane register */
3224         dspcntr = DISPPLANE_GAMMA_ENABLE;
3225
3226         /* Ironlake's plane is forced to pipe, bit 24 is to
3227            enable color space conversion */
3228         if (!IS_IRONLAKE(dev)) {
3229                 if (pipe == 0)
3230                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3231                 else
3232                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3233         }
3234
3235         if (pipe == 0 && !IS_I965G(dev)) {
3236                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3237                  * core speed.
3238                  *
3239                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3240                  * pipe == 0 check?
3241                  */
3242                 if (mode->clock >
3243                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3244                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3245                 else
3246                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3247         }
3248
3249         dspcntr |= DISPLAY_PLANE_ENABLE;
3250         pipeconf |= PIPEACONF_ENABLE;
3251         dpll |= DPLL_VCO_ENABLE;
3252
3253
3254         /* Disable the panel fitter if it was on our pipe */
3255         if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
3256                 I915_WRITE(PFIT_CONTROL, 0);
3257
3258         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3259         drm_mode_debug_printmodeline(mode);
3260
3261         /* assign to Ironlake registers */
3262         if (IS_IRONLAKE(dev)) {
3263                 fp_reg = pch_fp_reg;
3264                 dpll_reg = pch_dpll_reg;
3265         }
3266
3267         if (is_edp) {
3268                 ironlake_disable_pll_edp(crtc);
3269         } else if ((dpll & DPLL_VCO_ENABLE)) {
3270                 I915_WRITE(fp_reg, fp);
3271                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3272                 I915_READ(dpll_reg);
3273                 udelay(150);
3274         }
3275
3276         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3277          * This is an exception to the general rule that mode_set doesn't turn
3278          * things on.
3279          */
3280         if (is_lvds) {
3281                 u32 lvds;
3282
3283                 if (IS_IRONLAKE(dev))
3284                         lvds_reg = PCH_LVDS;
3285
3286                 lvds = I915_READ(lvds_reg);
3287                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3288                 /* set the corresponsding LVDS_BORDER bit */
3289                 lvds |= dev_priv->lvds_border_bits;
3290                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3291                  * set the DPLLs for dual-channel mode or not.
3292                  */
3293                 if (clock.p2 == 7)
3294                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3295                 else
3296                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3297
3298                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3299                  * appropriately here, but we need to look more thoroughly into how
3300                  * panels behave in the two modes.
3301                  */
3302                 /* set the dithering flag */
3303                 if (IS_I965G(dev)) {
3304                         if (dev_priv->lvds_dither) {
3305                                 if (IS_IRONLAKE(dev))
3306                                         pipeconf |= PIPE_ENABLE_DITHER;
3307                                 else
3308                                         lvds |= LVDS_ENABLE_DITHER;
3309                         } else {
3310                                 if (IS_IRONLAKE(dev))
3311                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3312                                 else
3313                                         lvds &= ~LVDS_ENABLE_DITHER;
3314                         }
3315                 }
3316                 I915_WRITE(lvds_reg, lvds);
3317                 I915_READ(lvds_reg);
3318         }
3319         if (is_dp)
3320                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3321
3322         if (!is_edp) {
3323                 I915_WRITE(fp_reg, fp);
3324                 I915_WRITE(dpll_reg, dpll);
3325                 I915_READ(dpll_reg);
3326                 /* Wait for the clocks to stabilize. */
3327                 udelay(150);
3328
3329                 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
3330                         if (is_sdvo) {
3331                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3332                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3333                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3334                         } else
3335                                 I915_WRITE(dpll_md_reg, 0);
3336                 } else {
3337                         /* write it again -- the BIOS does, after all */
3338                         I915_WRITE(dpll_reg, dpll);
3339                 }
3340                 I915_READ(dpll_reg);
3341                 /* Wait for the clocks to stabilize. */
3342                 udelay(150);
3343         }
3344
3345         if (is_lvds && has_reduced_clock && i915_powersave) {
3346                 I915_WRITE(fp_reg + 4, fp2);
3347                 intel_crtc->lowfreq_avail = true;
3348                 if (HAS_PIPE_CXSR(dev)) {
3349                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3350                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3351                 }
3352         } else {
3353                 I915_WRITE(fp_reg + 4, fp);
3354                 intel_crtc->lowfreq_avail = false;
3355                 if (HAS_PIPE_CXSR(dev)) {
3356                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3357                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3358                 }
3359         }
3360
3361         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3362                    ((adjusted_mode->crtc_htotal - 1) << 16));
3363         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3364                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3365         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3366                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3367         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3368                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3369         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3370                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3371         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3372                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3373         /* pipesrc and dspsize control the size that is scaled from, which should
3374          * always be the user's requested size.
3375          */
3376         if (!IS_IRONLAKE(dev)) {
3377                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3378                                 (mode->hdisplay - 1));
3379                 I915_WRITE(dsppos_reg, 0);
3380         }
3381         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3382
3383         if (IS_IRONLAKE(dev)) {
3384                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3385                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3386                 I915_WRITE(link_m1_reg, m_n.link_m);
3387                 I915_WRITE(link_n1_reg, m_n.link_n);
3388
3389                 if (is_edp) {
3390                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3391                 } else {
3392                         /* enable FDI RX PLL too */
3393                         temp = I915_READ(fdi_rx_reg);
3394                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3395                         udelay(200);
3396                 }
3397         }
3398
3399         I915_WRITE(pipeconf_reg, pipeconf);
3400         I915_READ(pipeconf_reg);
3401
3402         intel_wait_for_vblank(dev);
3403
3404         if (IS_IRONLAKE(dev)) {
3405                 /* enable address swizzle for tiling buffer */
3406                 temp = I915_READ(DISP_ARB_CTL);
3407                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3408         }
3409
3410         I915_WRITE(dspcntr_reg, dspcntr);
3411
3412         /* Flush the plane changes */
3413         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3414
3415         if ((IS_I965G(dev) || plane == 0))
3416                 intel_update_fbc(crtc, &crtc->mode);
3417
3418         intel_update_watermarks(dev);
3419
3420         drm_vblank_post_modeset(dev, pipe);
3421
3422         return ret;
3423 }
3424
3425 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3426 void intel_crtc_load_lut(struct drm_crtc *crtc)
3427 {
3428         struct drm_device *dev = crtc->dev;
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3431         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3432         int i;
3433
3434         /* The clocks have to be on to load the palette. */
3435         if (!crtc->enabled)
3436                 return;
3437
3438         /* use legacy palette for Ironlake */
3439         if (IS_IRONLAKE(dev))
3440                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3441                                                    LGC_PALETTE_B;
3442
3443         for (i = 0; i < 256; i++) {
3444                 I915_WRITE(palreg + 4 * i,
3445                            (intel_crtc->lut_r[i] << 16) |
3446                            (intel_crtc->lut_g[i] << 8) |
3447                            intel_crtc->lut_b[i]);
3448         }
3449 }
3450
3451 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3452                                  struct drm_file *file_priv,
3453                                  uint32_t handle,
3454                                  uint32_t width, uint32_t height)
3455 {
3456         struct drm_device *dev = crtc->dev;
3457         struct drm_i915_private *dev_priv = dev->dev_private;
3458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3459         struct drm_gem_object *bo;
3460         struct drm_i915_gem_object *obj_priv;
3461         int pipe = intel_crtc->pipe;
3462         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3463         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3464         uint32_t temp = I915_READ(control);
3465         size_t addr;
3466         int ret;
3467
3468         DRM_DEBUG_KMS("\n");
3469
3470         /* if we want to turn off the cursor ignore width and height */
3471         if (!handle) {
3472                 DRM_DEBUG_KMS("cursor off\n");
3473                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3474                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3475                         temp |= CURSOR_MODE_DISABLE;
3476                 } else {
3477                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3478                 }
3479                 addr = 0;
3480                 bo = NULL;
3481                 mutex_lock(&dev->struct_mutex);
3482                 goto finish;
3483         }
3484
3485         /* Currently we only support 64x64 cursors */
3486         if (width != 64 || height != 64) {
3487                 DRM_ERROR("we currently only support 64x64 cursors\n");
3488                 return -EINVAL;
3489         }
3490
3491         bo = drm_gem_object_lookup(dev, file_priv, handle);
3492         if (!bo)
3493                 return -ENOENT;
3494
3495         obj_priv = bo->driver_private;
3496
3497         if (bo->size < width * height * 4) {
3498                 DRM_ERROR("buffer is to small\n");
3499                 ret = -ENOMEM;
3500                 goto fail;
3501         }
3502
3503         /* we only need to pin inside GTT if cursor is non-phy */
3504         mutex_lock(&dev->struct_mutex);
3505         if (!dev_priv->info->cursor_needs_physical) {
3506                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3507                 if (ret) {
3508                         DRM_ERROR("failed to pin cursor bo\n");
3509                         goto fail_locked;
3510                 }
3511                 addr = obj_priv->gtt_offset;
3512         } else {
3513                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3514                 if (ret) {
3515                         DRM_ERROR("failed to attach phys object\n");
3516                         goto fail_locked;
3517                 }
3518                 addr = obj_priv->phys_obj->handle->busaddr;
3519         }
3520
3521         if (!IS_I9XX(dev))
3522                 I915_WRITE(CURSIZE, (height << 12) | width);
3523
3524         /* Hooray for CUR*CNTR differences */
3525         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3526                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3527                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3528                 temp |= (pipe << 28); /* Connect to correct pipe */
3529         } else {
3530                 temp &= ~(CURSOR_FORMAT_MASK);
3531                 temp |= CURSOR_ENABLE;
3532                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3533         }
3534
3535  finish:
3536         I915_WRITE(control, temp);
3537         I915_WRITE(base, addr);
3538
3539         if (intel_crtc->cursor_bo) {
3540                 if (dev_priv->info->cursor_needs_physical) {
3541                         if (intel_crtc->cursor_bo != bo)
3542                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3543                 } else
3544                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3545                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3546         }
3547
3548         mutex_unlock(&dev->struct_mutex);
3549
3550         intel_crtc->cursor_addr = addr;
3551         intel_crtc->cursor_bo = bo;
3552
3553         return 0;
3554 fail:
3555         mutex_lock(&dev->struct_mutex);
3556 fail_locked:
3557         drm_gem_object_unreference(bo);
3558         mutex_unlock(&dev->struct_mutex);
3559         return ret;
3560 }
3561
3562 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3563 {
3564         struct drm_device *dev = crtc->dev;
3565         struct drm_i915_private *dev_priv = dev->dev_private;
3566         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3567         struct intel_framebuffer *intel_fb;
3568         int pipe = intel_crtc->pipe;
3569         uint32_t temp = 0;
3570         uint32_t adder;
3571
3572         if (crtc->fb) {
3573                 intel_fb = to_intel_framebuffer(crtc->fb);
3574                 intel_mark_busy(dev, intel_fb->obj);
3575         }
3576
3577         if (x < 0) {
3578                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3579                 x = -x;
3580         }
3581         if (y < 0) {
3582                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3583                 y = -y;
3584         }
3585
3586         temp |= x << CURSOR_X_SHIFT;
3587         temp |= y << CURSOR_Y_SHIFT;
3588
3589         adder = intel_crtc->cursor_addr;
3590         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3591         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3592
3593         return 0;
3594 }
3595
3596 /** Sets the color ramps on behalf of RandR */
3597 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3598                                  u16 blue, int regno)
3599 {
3600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3601
3602         intel_crtc->lut_r[regno] = red >> 8;
3603         intel_crtc->lut_g[regno] = green >> 8;
3604         intel_crtc->lut_b[regno] = blue >> 8;
3605 }
3606
3607 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3608                              u16 *blue, int regno)
3609 {
3610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3611
3612         *red = intel_crtc->lut_r[regno] << 8;
3613         *green = intel_crtc->lut_g[regno] << 8;
3614         *blue = intel_crtc->lut_b[regno] << 8;
3615 }
3616
3617 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3618                                  u16 *blue, uint32_t size)
3619 {
3620         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621         int i;
3622
3623         if (size != 256)
3624                 return;
3625
3626         for (i = 0; i < 256; i++) {
3627                 intel_crtc->lut_r[i] = red[i] >> 8;
3628                 intel_crtc->lut_g[i] = green[i] >> 8;
3629                 intel_crtc->lut_b[i] = blue[i] >> 8;
3630         }
3631
3632         intel_crtc_load_lut(crtc);
3633 }
3634
3635 /**
3636  * Get a pipe with a simple mode set on it for doing load-based monitor
3637  * detection.
3638  *
3639  * It will be up to the load-detect code to adjust the pipe as appropriate for
3640  * its requirements.  The pipe will be connected to no other outputs.
3641  *
3642  * Currently this code will only succeed if there is a pipe with no outputs
3643  * configured for it.  In the future, it could choose to temporarily disable
3644  * some outputs to free up a pipe for its use.
3645  *
3646  * \return crtc, or NULL if no pipes are available.
3647  */
3648
3649 /* VESA 640x480x72Hz mode to set on the pipe */
3650 static struct drm_display_mode load_detect_mode = {
3651         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3652                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3653 };
3654
3655 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3656                                             struct drm_display_mode *mode,
3657                                             int *dpms_mode)
3658 {
3659         struct intel_crtc *intel_crtc;
3660         struct drm_crtc *possible_crtc;
3661         struct drm_crtc *supported_crtc =NULL;
3662         struct drm_encoder *encoder = &intel_output->enc;
3663         struct drm_crtc *crtc = NULL;
3664         struct drm_device *dev = encoder->dev;
3665         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3666         struct drm_crtc_helper_funcs *crtc_funcs;
3667         int i = -1;
3668
3669         /*
3670          * Algorithm gets a little messy:
3671          *   - if the connector already has an assigned crtc, use it (but make
3672          *     sure it's on first)
3673          *   - try to find the first unused crtc that can drive this connector,
3674          *     and use that if we find one
3675          *   - if there are no unused crtcs available, try to use the first
3676          *     one we found that supports the connector
3677          */
3678
3679         /* See if we already have a CRTC for this connector */
3680         if (encoder->crtc) {
3681                 crtc = encoder->crtc;
3682                 /* Make sure the crtc and connector are running */
3683                 intel_crtc = to_intel_crtc(crtc);
3684                 *dpms_mode = intel_crtc->dpms_mode;
3685                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3686                         crtc_funcs = crtc->helper_private;
3687                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3688                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3689                 }
3690                 return crtc;
3691         }
3692
3693         /* Find an unused one (if possible) */
3694         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3695                 i++;
3696                 if (!(encoder->possible_crtcs & (1 << i)))
3697                         continue;
3698                 if (!possible_crtc->enabled) {
3699                         crtc = possible_crtc;
3700                         break;
3701                 }
3702                 if (!supported_crtc)
3703                         supported_crtc = possible_crtc;
3704         }
3705
3706         /*
3707          * If we didn't find an unused CRTC, don't use any.
3708          */
3709         if (!crtc) {
3710                 return NULL;
3711         }
3712
3713         encoder->crtc = crtc;
3714         intel_output->base.encoder = encoder;
3715         intel_output->load_detect_temp = true;
3716
3717         intel_crtc = to_intel_crtc(crtc);
3718         *dpms_mode = intel_crtc->dpms_mode;
3719
3720         if (!crtc->enabled) {
3721                 if (!mode)
3722                         mode = &load_detect_mode;
3723                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3724         } else {
3725                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3726                         crtc_funcs = crtc->helper_private;
3727                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3728                 }
3729
3730                 /* Add this connector to the crtc */
3731                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3732                 encoder_funcs->commit(encoder);
3733         }
3734         /* let the connector get through one full cycle before testing */
3735         intel_wait_for_vblank(dev);
3736
3737         return crtc;
3738 }
3739
3740 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3741 {
3742         struct drm_encoder *encoder = &intel_output->enc;
3743         struct drm_device *dev = encoder->dev;
3744         struct drm_crtc *crtc = encoder->crtc;
3745         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3746         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3747
3748         if (intel_output->load_detect_temp) {
3749                 encoder->crtc = NULL;
3750                 intel_output->base.encoder = NULL;
3751                 intel_output->load_detect_temp = false;
3752                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3753                 drm_helper_disable_unused_functions(dev);
3754         }
3755
3756         /* Switch crtc and output back off if necessary */
3757         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3758                 if (encoder->crtc == crtc)
3759                         encoder_funcs->dpms(encoder, dpms_mode);
3760                 crtc_funcs->dpms(crtc, dpms_mode);
3761         }
3762 }
3763
3764 /* Returns the clock of the currently programmed mode of the given pipe. */
3765 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3766 {
3767         struct drm_i915_private *dev_priv = dev->dev_private;
3768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3769         int pipe = intel_crtc->pipe;
3770         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3771         u32 fp;
3772         intel_clock_t clock;
3773
3774         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3775                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3776         else
3777                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3778
3779         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3780         if (IS_PINEVIEW(dev)) {
3781                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3782                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3783         } else {
3784                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3785                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3786         }
3787
3788         if (IS_I9XX(dev)) {
3789                 if (IS_PINEVIEW(dev))
3790                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3791                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3792                 else
3793                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3794                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3795
3796                 switch (dpll & DPLL_MODE_MASK) {
3797                 case DPLLB_MODE_DAC_SERIAL:
3798                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3799                                 5 : 10;
3800                         break;
3801                 case DPLLB_MODE_LVDS:
3802                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3803                                 7 : 14;
3804                         break;
3805                 default:
3806                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3807                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3808                         return 0;
3809                 }
3810
3811                 /* XXX: Handle the 100Mhz refclk */
3812                 intel_clock(dev, 96000, &clock);
3813         } else {
3814                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3815
3816                 if (is_lvds) {
3817                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3818                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3819                         clock.p2 = 14;
3820
3821                         if ((dpll & PLL_REF_INPUT_MASK) ==
3822                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3823                                 /* XXX: might not be 66MHz */
3824                                 intel_clock(dev, 66000, &clock);
3825                         } else
3826                                 intel_clock(dev, 48000, &clock);
3827                 } else {
3828                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3829                                 clock.p1 = 2;
3830                         else {
3831                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3832                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3833                         }
3834                         if (dpll & PLL_P2_DIVIDE_BY_4)
3835                                 clock.p2 = 4;
3836                         else
3837                                 clock.p2 = 2;
3838
3839                         intel_clock(dev, 48000, &clock);
3840                 }
3841         }
3842
3843         /* XXX: It would be nice to validate the clocks, but we can't reuse
3844          * i830PllIsValid() because it relies on the xf86_config connector
3845          * configuration being accurate, which it isn't necessarily.
3846          */
3847
3848         return clock.dot;
3849 }
3850
3851 /** Returns the currently programmed mode of the given pipe. */
3852 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3853                                              struct drm_crtc *crtc)
3854 {
3855         struct drm_i915_private *dev_priv = dev->dev_private;
3856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3857         int pipe = intel_crtc->pipe;
3858         struct drm_display_mode *mode;
3859         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3860         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3861         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3862         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3863
3864         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3865         if (!mode)
3866                 return NULL;
3867
3868         mode->clock = intel_crtc_clock_get(dev, crtc);
3869         mode->hdisplay = (htot & 0xffff) + 1;
3870         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3871         mode->hsync_start = (hsync & 0xffff) + 1;
3872         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3873         mode->vdisplay = (vtot & 0xffff) + 1;
3874         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3875         mode->vsync_start = (vsync & 0xffff) + 1;
3876         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3877
3878         drm_mode_set_name(mode);
3879         drm_mode_set_crtcinfo(mode, 0);
3880
3881         return mode;
3882 }
3883
3884 #define GPU_IDLE_TIMEOUT 500 /* ms */
3885
3886 /* When this timer fires, we've been idle for awhile */
3887 static void intel_gpu_idle_timer(unsigned long arg)
3888 {
3889         struct drm_device *dev = (struct drm_device *)arg;
3890         drm_i915_private_t *dev_priv = dev->dev_private;
3891
3892         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3893
3894         dev_priv->busy = false;
3895
3896         queue_work(dev_priv->wq, &dev_priv->idle_work);
3897 }
3898
3899 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3900
3901 static void intel_crtc_idle_timer(unsigned long arg)
3902 {
3903         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3904         struct drm_crtc *crtc = &intel_crtc->base;
3905         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3906
3907         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3908
3909         intel_crtc->busy = false;
3910
3911         queue_work(dev_priv->wq, &dev_priv->idle_work);
3912 }
3913
3914 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3915 {
3916         struct drm_device *dev = crtc->dev;
3917         drm_i915_private_t *dev_priv = dev->dev_private;
3918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3919         int pipe = intel_crtc->pipe;
3920         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3921         int dpll = I915_READ(dpll_reg);
3922
3923         if (IS_IRONLAKE(dev))
3924                 return;
3925
3926         if (!dev_priv->lvds_downclock_avail)
3927                 return;
3928
3929         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3930                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3931
3932                 /* Unlock panel regs */
3933                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3934
3935                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3936                 I915_WRITE(dpll_reg, dpll);
3937                 dpll = I915_READ(dpll_reg);
3938                 intel_wait_for_vblank(dev);
3939                 dpll = I915_READ(dpll_reg);
3940                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3941                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3942
3943                 /* ...and lock them again */
3944                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3945         }
3946
3947         /* Schedule downclock */
3948         if (schedule)
3949                 mod_timer(&intel_crtc->idle_timer, jiffies +
3950                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3951 }
3952
3953 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3954 {
3955         struct drm_device *dev = crtc->dev;
3956         drm_i915_private_t *dev_priv = dev->dev_private;
3957         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3958         int pipe = intel_crtc->pipe;
3959         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3960         int dpll = I915_READ(dpll_reg);
3961
3962         if (IS_IRONLAKE(dev))
3963                 return;
3964
3965         if (!dev_priv->lvds_downclock_avail)
3966                 return;
3967
3968         /*
3969          * Since this is called by a timer, we should never get here in
3970          * the manual case.
3971          */
3972         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3973                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3974
3975                 /* Unlock panel regs */
3976                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3977
3978                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3979                 I915_WRITE(dpll_reg, dpll);
3980                 dpll = I915_READ(dpll_reg);
3981                 intel_wait_for_vblank(dev);
3982                 dpll = I915_READ(dpll_reg);
3983                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3984                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3985
3986                 /* ...and lock them again */
3987                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3988         }
3989
3990 }
3991
3992 /**
3993  * intel_idle_update - adjust clocks for idleness
3994  * @work: work struct
3995  *
3996  * Either the GPU or display (or both) went idle.  Check the busy status
3997  * here and adjust the CRTC and GPU clocks as necessary.
3998  */
3999 static void intel_idle_update(struct work_struct *work)
4000 {
4001         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4002                                                     idle_work);
4003         struct drm_device *dev = dev_priv->dev;
4004         struct drm_crtc *crtc;
4005         struct intel_crtc *intel_crtc;
4006
4007         if (!i915_powersave)
4008                 return;
4009
4010         mutex_lock(&dev->struct_mutex);
4011
4012         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4013                 /* Skip inactive CRTCs */
4014                 if (!crtc->fb)
4015                         continue;
4016
4017                 intel_crtc = to_intel_crtc(crtc);
4018                 if (!intel_crtc->busy)
4019                         intel_decrease_pllclock(crtc);
4020         }
4021
4022         mutex_unlock(&dev->struct_mutex);
4023 }
4024
4025 /**
4026  * intel_mark_busy - mark the GPU and possibly the display busy
4027  * @dev: drm device
4028  * @obj: object we're operating on
4029  *
4030  * Callers can use this function to indicate that the GPU is busy processing
4031  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4032  * buffer), we'll also mark the display as busy, so we know to increase its
4033  * clock frequency.
4034  */
4035 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4036 {
4037         drm_i915_private_t *dev_priv = dev->dev_private;
4038         struct drm_crtc *crtc = NULL;
4039         struct intel_framebuffer *intel_fb;
4040         struct intel_crtc *intel_crtc;
4041
4042         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4043                 return;
4044
4045         if (!dev_priv->busy)
4046                 dev_priv->busy = true;
4047         else
4048                 mod_timer(&dev_priv->idle_timer, jiffies +
4049                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4050
4051         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4052                 if (!crtc->fb)
4053                         continue;
4054
4055                 intel_crtc = to_intel_crtc(crtc);
4056                 intel_fb = to_intel_framebuffer(crtc->fb);
4057                 if (intel_fb->obj == obj) {
4058                         if (!intel_crtc->busy) {
4059                                 /* Non-busy -> busy, upclock */
4060                                 intel_increase_pllclock(crtc, true);
4061                                 intel_crtc->busy = true;
4062                         } else {
4063                                 /* Busy -> busy, put off timer */
4064                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4065                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4066                         }
4067                 }
4068         }
4069 }
4070
4071 static void intel_crtc_destroy(struct drm_crtc *crtc)
4072 {
4073         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4074
4075         drm_crtc_cleanup(crtc);
4076         kfree(intel_crtc);
4077 }
4078
4079 struct intel_unpin_work {
4080         struct work_struct work;
4081         struct drm_device *dev;
4082         struct drm_gem_object *obj;
4083         struct drm_pending_vblank_event *event;
4084         int pending;
4085 };
4086
4087 static void intel_unpin_work_fn(struct work_struct *__work)
4088 {
4089         struct intel_unpin_work *work =
4090                 container_of(__work, struct intel_unpin_work, work);
4091
4092         mutex_lock(&work->dev->struct_mutex);
4093         i915_gem_object_unpin(work->obj);
4094         drm_gem_object_unreference(work->obj);
4095         mutex_unlock(&work->dev->struct_mutex);
4096         kfree(work);
4097 }
4098
4099 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4100 {
4101         drm_i915_private_t *dev_priv = dev->dev_private;
4102         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104         struct intel_unpin_work *work;
4105         struct drm_i915_gem_object *obj_priv;
4106         struct drm_pending_vblank_event *e;
4107         struct timeval now;
4108         unsigned long flags;
4109
4110         /* Ignore early vblank irqs */
4111         if (intel_crtc == NULL)
4112                 return;
4113
4114         spin_lock_irqsave(&dev->event_lock, flags);
4115         work = intel_crtc->unpin_work;
4116         if (work == NULL || !work->pending) {
4117                 if (work && !work->pending) {
4118                         obj_priv = work->obj->driver_private;
4119                         DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4120                                          obj_priv,
4121                                          atomic_read(&obj_priv->pending_flip));
4122                 }
4123                 spin_unlock_irqrestore(&dev->event_lock, flags);
4124                 return;
4125         }
4126
4127         intel_crtc->unpin_work = NULL;
4128         drm_vblank_put(dev, intel_crtc->pipe);
4129
4130         if (work->event) {
4131                 e = work->event;
4132                 do_gettimeofday(&now);
4133                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4134                 e->event.tv_sec = now.tv_sec;
4135                 e->event.tv_usec = now.tv_usec;
4136                 list_add_tail(&e->base.link,
4137                               &e->base.file_priv->event_list);
4138                 wake_up_interruptible(&e->base.file_priv->event_wait);
4139         }
4140
4141         spin_unlock_irqrestore(&dev->event_lock, flags);
4142
4143         obj_priv = work->obj->driver_private;
4144
4145         /* Initial scanout buffer will have a 0 pending flip count */
4146         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4147             atomic_dec_and_test(&obj_priv->pending_flip))
4148                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4149         schedule_work(&work->work);
4150 }
4151
4152 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4153 {
4154         drm_i915_private_t *dev_priv = dev->dev_private;
4155         struct intel_crtc *intel_crtc =
4156                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4157         unsigned long flags;
4158
4159         spin_lock_irqsave(&dev->event_lock, flags);
4160         if (intel_crtc->unpin_work) {
4161                 intel_crtc->unpin_work->pending = 1;
4162         } else {
4163                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4164         }
4165         spin_unlock_irqrestore(&dev->event_lock, flags);
4166 }
4167
4168 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4169                                 struct drm_framebuffer *fb,
4170                                 struct drm_pending_vblank_event *event)
4171 {
4172         struct drm_device *dev = crtc->dev;
4173         struct drm_i915_private *dev_priv = dev->dev_private;
4174         struct intel_framebuffer *intel_fb;
4175         struct drm_i915_gem_object *obj_priv;
4176         struct drm_gem_object *obj;
4177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178         struct intel_unpin_work *work;
4179         unsigned long flags;
4180         int ret;
4181         RING_LOCALS;
4182
4183         work = kzalloc(sizeof *work, GFP_KERNEL);
4184         if (work == NULL)
4185                 return -ENOMEM;
4186
4187         mutex_lock(&dev->struct_mutex);
4188
4189         work->event = event;
4190         work->dev = crtc->dev;
4191         intel_fb = to_intel_framebuffer(crtc->fb);
4192         work->obj = intel_fb->obj;
4193         INIT_WORK(&work->work, intel_unpin_work_fn);
4194
4195         /* We borrow the event spin lock for protecting unpin_work */
4196         spin_lock_irqsave(&dev->event_lock, flags);
4197         if (intel_crtc->unpin_work) {
4198                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4199                 spin_unlock_irqrestore(&dev->event_lock, flags);
4200                 kfree(work);
4201                 mutex_unlock(&dev->struct_mutex);
4202                 return -EBUSY;
4203         }
4204         intel_crtc->unpin_work = work;
4205         spin_unlock_irqrestore(&dev->event_lock, flags);
4206
4207         intel_fb = to_intel_framebuffer(fb);
4208         obj = intel_fb->obj;
4209
4210         ret = intel_pin_and_fence_fb_obj(dev, obj);
4211         if (ret != 0) {
4212                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4213                           obj->driver_private);
4214                 kfree(work);
4215                 intel_crtc->unpin_work = NULL;
4216                 mutex_unlock(&dev->struct_mutex);
4217                 return ret;
4218         }
4219
4220         /* Reference the old fb object for the scheduled work. */
4221         drm_gem_object_reference(work->obj);
4222
4223         crtc->fb = fb;
4224         i915_gem_object_flush_write_domain(obj);
4225         drm_vblank_get(dev, intel_crtc->pipe);
4226         obj_priv = obj->driver_private;
4227         atomic_inc(&obj_priv->pending_flip);
4228
4229         BEGIN_LP_RING(4);
4230         OUT_RING(MI_DISPLAY_FLIP |
4231                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4232         OUT_RING(fb->pitch);
4233         if (IS_I965G(dev)) {
4234                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4235                 OUT_RING((fb->width << 16) | fb->height);
4236         } else {
4237                 OUT_RING(obj_priv->gtt_offset);
4238                 OUT_RING(MI_NOOP);
4239         }
4240         ADVANCE_LP_RING();
4241
4242         mutex_unlock(&dev->struct_mutex);
4243
4244         return 0;
4245 }
4246
4247 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4248         .dpms = intel_crtc_dpms,
4249         .mode_fixup = intel_crtc_mode_fixup,
4250         .mode_set = intel_crtc_mode_set,
4251         .mode_set_base = intel_pipe_set_base,
4252         .prepare = intel_crtc_prepare,
4253         .commit = intel_crtc_commit,
4254         .load_lut = intel_crtc_load_lut,
4255 };
4256
4257 static const struct drm_crtc_funcs intel_crtc_funcs = {
4258         .cursor_set = intel_crtc_cursor_set,
4259         .cursor_move = intel_crtc_cursor_move,
4260         .gamma_set = intel_crtc_gamma_set,
4261         .set_config = drm_crtc_helper_set_config,
4262         .destroy = intel_crtc_destroy,
4263         .page_flip = intel_crtc_page_flip,
4264 };
4265
4266
4267 static void intel_crtc_init(struct drm_device *dev, int pipe)
4268 {
4269         drm_i915_private_t *dev_priv = dev->dev_private;
4270         struct intel_crtc *intel_crtc;
4271         int i;
4272
4273         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4274         if (intel_crtc == NULL)
4275                 return;
4276
4277         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4278
4279         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4280         intel_crtc->pipe = pipe;
4281         intel_crtc->plane = pipe;
4282         for (i = 0; i < 256; i++) {
4283                 intel_crtc->lut_r[i] = i;
4284                 intel_crtc->lut_g[i] = i;
4285                 intel_crtc->lut_b[i] = i;
4286         }
4287
4288         /* Swap pipes & planes for FBC on pre-965 */
4289         intel_crtc->pipe = pipe;
4290         intel_crtc->plane = pipe;
4291         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4292                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4293                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4294         }
4295
4296         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4297                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4298         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4299         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4300
4301         intel_crtc->cursor_addr = 0;
4302         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4303         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4304
4305         intel_crtc->busy = false;
4306
4307         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4308                     (unsigned long)intel_crtc);
4309 }
4310
4311 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4312                                 struct drm_file *file_priv)
4313 {
4314         drm_i915_private_t *dev_priv = dev->dev_private;
4315         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4316         struct drm_mode_object *drmmode_obj;
4317         struct intel_crtc *crtc;
4318
4319         if (!dev_priv) {
4320                 DRM_ERROR("called with no initialization\n");
4321                 return -EINVAL;
4322         }
4323
4324         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4325                         DRM_MODE_OBJECT_CRTC);
4326
4327         if (!drmmode_obj) {
4328                 DRM_ERROR("no such CRTC id\n");
4329                 return -EINVAL;
4330         }
4331
4332         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4333         pipe_from_crtc_id->pipe = crtc->pipe;
4334
4335         return 0;
4336 }
4337
4338 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4339 {
4340         struct drm_crtc *crtc = NULL;
4341
4342         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4343                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4344                 if (intel_crtc->pipe == pipe)
4345                         break;
4346         }
4347         return crtc;
4348 }
4349
4350 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4351 {
4352         int index_mask = 0;
4353         struct drm_connector *connector;
4354         int entry = 0;
4355
4356         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4357                 struct intel_output *intel_output = to_intel_output(connector);
4358                 if (type_mask & intel_output->clone_mask)
4359                         index_mask |= (1 << entry);
4360                 entry++;
4361         }
4362         return index_mask;
4363 }
4364
4365
4366 static void intel_setup_outputs(struct drm_device *dev)
4367 {
4368         struct drm_i915_private *dev_priv = dev->dev_private;
4369         struct drm_connector *connector;
4370
4371         intel_crt_init(dev);
4372
4373         /* Set up integrated LVDS */
4374         if (IS_MOBILE(dev) && !IS_I830(dev))
4375                 intel_lvds_init(dev);
4376
4377         if (IS_IRONLAKE(dev)) {
4378                 int found;
4379
4380                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4381                         intel_dp_init(dev, DP_A);
4382
4383                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4384                         /* check SDVOB */
4385                         /* found = intel_sdvo_init(dev, HDMIB); */
4386                         found = 0;
4387                         if (!found)
4388                                 intel_hdmi_init(dev, HDMIB);
4389                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4390                                 intel_dp_init(dev, PCH_DP_B);
4391                 }
4392
4393                 if (I915_READ(HDMIC) & PORT_DETECTED)
4394                         intel_hdmi_init(dev, HDMIC);
4395
4396                 if (I915_READ(HDMID) & PORT_DETECTED)
4397                         intel_hdmi_init(dev, HDMID);
4398
4399                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4400                         intel_dp_init(dev, PCH_DP_C);
4401
4402                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4403                         intel_dp_init(dev, PCH_DP_D);
4404
4405         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4406                 bool found = false;
4407
4408                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4409                         DRM_DEBUG_KMS("probing SDVOB\n");
4410                         found = intel_sdvo_init(dev, SDVOB);
4411                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4412                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4413                                 intel_hdmi_init(dev, SDVOB);
4414                         }
4415
4416                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4417                                 DRM_DEBUG_KMS("probing DP_B\n");
4418                                 intel_dp_init(dev, DP_B);
4419                         }
4420                 }
4421
4422                 /* Before G4X SDVOC doesn't have its own detect register */
4423
4424                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4425                         DRM_DEBUG_KMS("probing SDVOC\n");
4426                         found = intel_sdvo_init(dev, SDVOC);
4427                 }
4428
4429                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4430
4431                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4432                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4433                                 intel_hdmi_init(dev, SDVOC);
4434                         }
4435                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4436                                 DRM_DEBUG_KMS("probing DP_C\n");
4437                                 intel_dp_init(dev, DP_C);
4438                         }
4439                 }
4440
4441                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4442                     (I915_READ(DP_D) & DP_DETECTED)) {
4443                         DRM_DEBUG_KMS("probing DP_D\n");
4444                         intel_dp_init(dev, DP_D);
4445                 }
4446         } else if (IS_I8XX(dev))
4447                 intel_dvo_init(dev);
4448
4449         if (SUPPORTS_TV(dev))
4450                 intel_tv_init(dev);
4451
4452         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4453                 struct intel_output *intel_output = to_intel_output(connector);
4454                 struct drm_encoder *encoder = &intel_output->enc;
4455
4456                 encoder->possible_crtcs = intel_output->crtc_mask;
4457                 encoder->possible_clones = intel_connector_clones(dev,
4458                                                 intel_output->clone_mask);
4459         }
4460 }
4461
4462 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4463 {
4464         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4465         struct drm_device *dev = fb->dev;
4466
4467         if (fb->fbdev)
4468                 intelfb_remove(dev, fb);
4469
4470         drm_framebuffer_cleanup(fb);
4471         mutex_lock(&dev->struct_mutex);
4472         drm_gem_object_unreference(intel_fb->obj);
4473         mutex_unlock(&dev->struct_mutex);
4474
4475         kfree(intel_fb);
4476 }
4477
4478 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4479                                                 struct drm_file *file_priv,
4480                                                 unsigned int *handle)
4481 {
4482         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4483         struct drm_gem_object *object = intel_fb->obj;
4484
4485         return drm_gem_handle_create(file_priv, object, handle);
4486 }
4487
4488 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4489         .destroy = intel_user_framebuffer_destroy,
4490         .create_handle = intel_user_framebuffer_create_handle,
4491 };
4492
4493 int intel_framebuffer_create(struct drm_device *dev,
4494                              struct drm_mode_fb_cmd *mode_cmd,
4495                              struct drm_framebuffer **fb,
4496                              struct drm_gem_object *obj)
4497 {
4498         struct intel_framebuffer *intel_fb;
4499         int ret;
4500
4501         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4502         if (!intel_fb)
4503                 return -ENOMEM;
4504
4505         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4506         if (ret) {
4507                 DRM_ERROR("framebuffer init failed %d\n", ret);
4508                 return ret;
4509         }
4510
4511         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4512
4513         intel_fb->obj = obj;
4514
4515         *fb = &intel_fb->base;
4516
4517         return 0;
4518 }
4519
4520
4521 static struct drm_framebuffer *
4522 intel_user_framebuffer_create(struct drm_device *dev,
4523                               struct drm_file *filp,
4524                               struct drm_mode_fb_cmd *mode_cmd)
4525 {
4526         struct drm_gem_object *obj;
4527         struct drm_framebuffer *fb;
4528         int ret;
4529
4530         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4531         if (!obj)
4532                 return NULL;
4533
4534         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4535         if (ret) {
4536                 mutex_lock(&dev->struct_mutex);
4537                 drm_gem_object_unreference(obj);
4538                 mutex_unlock(&dev->struct_mutex);
4539                 return NULL;
4540         }
4541
4542         return fb;
4543 }
4544
4545 static const struct drm_mode_config_funcs intel_mode_funcs = {
4546         .fb_create = intel_user_framebuffer_create,
4547         .fb_changed = intelfb_probe,
4548 };
4549
4550 static struct drm_gem_object *
4551 intel_alloc_power_context(struct drm_device *dev)
4552 {
4553         struct drm_gem_object *pwrctx;
4554         int ret;
4555
4556         pwrctx = drm_gem_object_alloc(dev, 4096);
4557         if (!pwrctx) {
4558                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4559                 return NULL;
4560         }
4561
4562         mutex_lock(&dev->struct_mutex);
4563         ret = i915_gem_object_pin(pwrctx, 4096);
4564         if (ret) {
4565                 DRM_ERROR("failed to pin power context: %d\n", ret);
4566                 goto err_unref;
4567         }
4568
4569         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4570         if (ret) {
4571                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4572                 goto err_unpin;
4573         }
4574         mutex_unlock(&dev->struct_mutex);
4575
4576         return pwrctx;
4577
4578 err_unpin:
4579         i915_gem_object_unpin(pwrctx);
4580 err_unref:
4581         drm_gem_object_unreference(pwrctx);
4582         mutex_unlock(&dev->struct_mutex);
4583         return NULL;
4584 }
4585
4586 void intel_init_clock_gating(struct drm_device *dev)
4587 {
4588         struct drm_i915_private *dev_priv = dev->dev_private;
4589
4590         /*
4591          * Disable clock gating reported to work incorrectly according to the
4592          * specs, but enable as much else as we can.
4593          */
4594         if (IS_IRONLAKE(dev)) {
4595                 return;
4596         } else if (IS_G4X(dev)) {
4597                 uint32_t dspclk_gate;
4598                 I915_WRITE(RENCLK_GATE_D1, 0);
4599                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4600                        GS_UNIT_CLOCK_GATE_DISABLE |
4601                        CL_UNIT_CLOCK_GATE_DISABLE);
4602                 I915_WRITE(RAMCLK_GATE_D, 0);
4603                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4604                         OVRUNIT_CLOCK_GATE_DISABLE |
4605                         OVCUNIT_CLOCK_GATE_DISABLE;
4606                 if (IS_GM45(dev))
4607                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4608                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4609         } else if (IS_I965GM(dev)) {
4610                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4611                 I915_WRITE(RENCLK_GATE_D2, 0);
4612                 I915_WRITE(DSPCLK_GATE_D, 0);
4613                 I915_WRITE(RAMCLK_GATE_D, 0);
4614                 I915_WRITE16(DEUC, 0);
4615         } else if (IS_I965G(dev)) {
4616                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4617                        I965_RCC_CLOCK_GATE_DISABLE |
4618                        I965_RCPB_CLOCK_GATE_DISABLE |
4619                        I965_ISC_CLOCK_GATE_DISABLE |
4620                        I965_FBC_CLOCK_GATE_DISABLE);
4621                 I915_WRITE(RENCLK_GATE_D2, 0);
4622         } else if (IS_I9XX(dev)) {
4623                 u32 dstate = I915_READ(D_STATE);
4624
4625                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4626                         DSTATE_DOT_CLOCK_GATING;
4627                 I915_WRITE(D_STATE, dstate);
4628         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4629                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4630         } else if (IS_I830(dev)) {
4631                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4632         }
4633
4634         /*
4635          * GPU can automatically power down the render unit if given a page
4636          * to save state.
4637          */
4638         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4639                 struct drm_i915_gem_object *obj_priv = NULL;
4640
4641                 if (dev_priv->pwrctx) {
4642                         obj_priv = dev_priv->pwrctx->driver_private;
4643                 } else {
4644                         struct drm_gem_object *pwrctx;
4645
4646                         pwrctx = intel_alloc_power_context(dev);
4647                         if (pwrctx) {
4648                                 dev_priv->pwrctx = pwrctx;
4649                                 obj_priv = pwrctx->driver_private;
4650                         }
4651                 }
4652
4653                 if (obj_priv) {
4654                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4655                         I915_WRITE(MCHBAR_RENDER_STANDBY,
4656                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4657                 }
4658         }
4659 }
4660
4661 /* Set up chip specific display functions */
4662 static void intel_init_display(struct drm_device *dev)
4663 {
4664         struct drm_i915_private *dev_priv = dev->dev_private;
4665
4666         /* We always want a DPMS function */
4667         if (IS_IRONLAKE(dev))
4668                 dev_priv->display.dpms = ironlake_crtc_dpms;
4669         else
4670                 dev_priv->display.dpms = i9xx_crtc_dpms;
4671
4672         /* Only mobile has FBC, leave pointers NULL for other chips */
4673         if (IS_MOBILE(dev)) {
4674                 if (IS_GM45(dev)) {
4675                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4676                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4677                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4678                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4679                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4680                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4681                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4682                 }
4683                 /* 855GM needs testing */
4684         }
4685
4686         /* Returns the core display clock speed */
4687         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4688                 dev_priv->display.get_display_clock_speed =
4689                         i945_get_display_clock_speed;
4690         else if (IS_I915G(dev))
4691                 dev_priv->display.get_display_clock_speed =
4692                         i915_get_display_clock_speed;
4693         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4694                 dev_priv->display.get_display_clock_speed =
4695                         i9xx_misc_get_display_clock_speed;
4696         else if (IS_I915GM(dev))
4697                 dev_priv->display.get_display_clock_speed =
4698                         i915gm_get_display_clock_speed;
4699         else if (IS_I865G(dev))
4700                 dev_priv->display.get_display_clock_speed =
4701                         i865_get_display_clock_speed;
4702         else if (IS_I85X(dev))
4703                 dev_priv->display.get_display_clock_speed =
4704                         i855_get_display_clock_speed;
4705         else /* 852, 830 */
4706                 dev_priv->display.get_display_clock_speed =
4707                         i830_get_display_clock_speed;
4708
4709         /* For FIFO watermark updates */
4710         if (IS_IRONLAKE(dev))
4711                 dev_priv->display.update_wm = NULL;
4712         else if (IS_G4X(dev))
4713                 dev_priv->display.update_wm = g4x_update_wm;
4714         else if (IS_I965G(dev))
4715                 dev_priv->display.update_wm = i965_update_wm;
4716         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4717                 dev_priv->display.update_wm = i9xx_update_wm;
4718                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4719         } else {
4720                 if (IS_I85X(dev))
4721                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4722                 else if (IS_845G(dev))
4723                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4724                 else
4725                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4726                 dev_priv->display.update_wm = i830_update_wm;
4727         }
4728 }
4729
4730 void intel_modeset_init(struct drm_device *dev)
4731 {
4732         struct drm_i915_private *dev_priv = dev->dev_private;
4733         int num_pipe;
4734         int i;
4735
4736         drm_mode_config_init(dev);
4737
4738         dev->mode_config.min_width = 0;
4739         dev->mode_config.min_height = 0;
4740
4741         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4742
4743         intel_init_display(dev);
4744
4745         if (IS_I965G(dev)) {
4746                 dev->mode_config.max_width = 8192;
4747                 dev->mode_config.max_height = 8192;
4748         } else if (IS_I9XX(dev)) {
4749                 dev->mode_config.max_width = 4096;
4750                 dev->mode_config.max_height = 4096;
4751         } else {
4752                 dev->mode_config.max_width = 2048;
4753                 dev->mode_config.max_height = 2048;
4754         }
4755
4756         /* set memory base */
4757         if (IS_I9XX(dev))
4758                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4759         else
4760                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4761
4762         if (IS_MOBILE(dev) || IS_I9XX(dev))
4763                 num_pipe = 2;
4764         else
4765                 num_pipe = 1;
4766         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4767                   num_pipe, num_pipe > 1 ? "s" : "");
4768
4769         if (IS_I85X(dev))
4770                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4771         else if (IS_I9XX(dev) || IS_G4X(dev))
4772                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4773
4774         for (i = 0; i < num_pipe; i++) {
4775                 intel_crtc_init(dev, i);
4776         }
4777
4778         intel_setup_outputs(dev);
4779
4780         intel_init_clock_gating(dev);
4781
4782         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4783         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4784                     (unsigned long)dev);
4785
4786         intel_setup_overlay(dev);
4787
4788         if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4789                                                         dev_priv->fsb_freq,
4790                                                         dev_priv->mem_freq))
4791                 DRM_INFO("failed to find known CxSR latency "
4792                          "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4793                          dev_priv->fsb_freq, dev_priv->mem_freq);
4794 }
4795
4796 void intel_modeset_cleanup(struct drm_device *dev)
4797 {
4798         struct drm_i915_private *dev_priv = dev->dev_private;
4799         struct drm_crtc *crtc;
4800         struct intel_crtc *intel_crtc;
4801
4802         mutex_lock(&dev->struct_mutex);
4803
4804         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4805                 /* Skip inactive CRTCs */
4806                 if (!crtc->fb)
4807                         continue;
4808
4809                 intel_crtc = to_intel_crtc(crtc);
4810                 intel_increase_pllclock(crtc, false);
4811                 del_timer_sync(&intel_crtc->idle_timer);
4812         }
4813
4814         del_timer_sync(&dev_priv->idle_timer);
4815
4816         if (dev_priv->display.disable_fbc)
4817                 dev_priv->display.disable_fbc(dev);
4818
4819         if (dev_priv->pwrctx) {
4820                 struct drm_i915_gem_object *obj_priv;
4821
4822                 obj_priv = dev_priv->pwrctx->driver_private;
4823                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4824                 I915_READ(PWRCTXA);
4825                 i915_gem_object_unpin(dev_priv->pwrctx);
4826                 drm_gem_object_unreference(dev_priv->pwrctx);
4827         }
4828
4829         mutex_unlock(&dev->struct_mutex);
4830
4831         drm_mode_config_cleanup(dev);
4832 }
4833
4834
4835 /* current intel driver doesn't take advantage of encoders
4836    always give back the encoder for the connector
4837 */
4838 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4839 {
4840         struct intel_output *intel_output = to_intel_output(connector);
4841
4842         return &intel_output->enc;
4843 }
4844
4845 /*
4846  * set vga decode state - true == enable VGA decode
4847  */
4848 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4849 {
4850         struct drm_i915_private *dev_priv = dev->dev_private;
4851         u16 gmch_ctrl;
4852
4853         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4854         if (state)
4855                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4856         else
4857                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4858         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4859         return 0;
4860 }