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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "drm_dp_helper.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define PINEVIEW_VCO_MIN                1700000
 106 #define PINEVIEW_VCO_MAX                3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* Pineview's Ncounter is a ring counter */
 110 #define PINEVIEW_N_MIN                3
 111 #define PINEVIEW_N_MAX                6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define PINEVIEW_M_MIN                2
 115 #define PINEVIEW_M_MAX              256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* Pineview M1 is reserved, and must be 0 */
 121 #define PINEVIEW_M1_MIN               0
 122 #define PINEVIEW_M1_MAX               0
 123 #define PINEVIEW_M2_MIN               0
 124 #define PINEVIEW_M2_MAX               254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define PINEVIEW_P_LVDS_MIN                   7
 130 #define PINEVIEW_P_LVDS_MAX                  112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* Ironlake */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IRONLAKE_DOT_MIN         25000
 242 #define IRONLAKE_DOT_MAX         350000
 243 #define IRONLAKE_VCO_MIN         1760000
 244 #define IRONLAKE_VCO_MAX         3510000
 245 #define IRONLAKE_N_MIN           1
 246 #define IRONLAKE_N_MAX           5
 247 #define IRONLAKE_M_MIN           79
 248 #define IRONLAKE_M_MAX           118
 249 #define IRONLAKE_M1_MIN          12
 250 #define IRONLAKE_M1_MAX          23
 251 #define IRONLAKE_M2_MIN          5
 252 #define IRONLAKE_M2_MAX          9
 253 #define IRONLAKE_P_SDVO_DAC_MIN  5
 254 #define IRONLAKE_P_SDVO_DAC_MAX  80
 255 #define IRONLAKE_P_LVDS_MIN      28
 256 #define IRONLAKE_P_LVDS_MAX      112
 257 #define IRONLAKE_P1_MIN          1
 258 #define IRONLAKE_P1_MAX          8
 259 #define IRONLAKE_P2_SDVO_DAC_SLOW 10
 260 #define IRONLAKE_P2_SDVO_DAC_FAST 5
 261 #define IRONLAKE_P2_LVDS_SLOW    14 /* single channel */
 262 #define IRONLAKE_P2_LVDS_FAST    7  /* double channel */
 263 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                              int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                            int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_pineview_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 459         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 460         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 461         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 462         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_pineview_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 474         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 475         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 476         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 477         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 478         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* Pineview only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_ironlake_sdvo = {
 488         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 489         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 490         .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
 491         .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
 492         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 493         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 494         .p   = { .min = IRONLAKE_P_SDVO_DAC_MIN,   .max = IRONLAKE_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IRONLAKE_P1_MIN,           .max = IRONLAKE_P1_MAX },
 496         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 497                  .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_ironlake_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_ironlake_lvds = {
 503         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 504         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 505         .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
 506         .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
 507         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 508         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 509         .p   = { .min = IRONLAKE_P_LVDS_MIN,       .max = IRONLAKE_P_LVDS_MAX },
 510         .p1  = { .min = IRONLAKE_P1_MIN,           .max = IRONLAKE_P1_MAX },
 511         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 512                  .p2_slow = IRONLAKE_P2_LVDS_SLOW,
 513                  .p2_fast = IRONLAKE_P2_LVDS_FAST },
 514         .find_pll = intel_ironlake_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_ironlake_lvds;
 522         else
 523                 limit = &intel_limits_ironlake_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IRONLAKE(dev))
 561                 limit = intel_ironlake_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_PINEVIEW(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_pineview_lvds;
 572                 else
 573                         limit = &intel_limits_pineview_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 584 static void pineview_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_PINEVIEW(dev)) {
 595                 pineview_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 710              clock.m1++) {
 711                 for (clock.m2 = limit->m2.min;
 712                      clock.m2 <= limit->m2.max; clock.m2++) {
 713                         /* m1 is always 0 in Pineview */
 714                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 715                                 break;
 716                         for (clock.n = limit->n.min;
 717                              clock.n <= limit->n.max; clock.n++) {
 718                                 for (clock.p1 = limit->p1.min;
 719                                         clock.p1 <= limit->p1.max; clock.p1++) {
 720                                         int this_err;
 721
 722                                         intel_clock(dev, refclk, &clock);
 723
 724                                         if (!intel_PLL_is_valid(crtc, &clock))
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740
 741 static bool
 742 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 743                             int target, int refclk, intel_clock_t *best_clock)
 744
 745 {
 746         struct drm_device *dev = crtc->dev;
 747         intel_clock_t clock;
 748         int err = target;
 749         bool found = false;
 750
 751         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 752
 753         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 754                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 755                         /* m1 is always 0 in Pineview */
 756                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 757                                 break;
 758                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 759                              clock.n++) {
 760                                 int this_err;
 761
 762                                 intel_clock(dev, refclk, &clock);
 763
 764                                 if (!intel_PLL_is_valid(crtc, &clock))
 765                                         continue;
 766
 767                                 this_err = abs(clock.dot - target);
 768                                 if (this_err < err) {
 769                                         *best_clock = clock;
 770                                         err = this_err;
 771                                         found = true;
 772                                 }
 773                         }
 774                 }
 775         }
 776
 777         return found;
 778 }
 779
 780 static bool
 781 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 782                         int target, int refclk, intel_clock_t *best_clock)
 783 {
 784         struct drm_device *dev = crtc->dev;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         intel_clock_t clock;
 787         int max_n;
 788         bool found;
 789         /* approximately equals target * 0.00488 */
 790         int err_most = (target >> 8) + (target >> 10);
 791         found = false;
 792
 793         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 794                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 795                     LVDS_CLKB_POWER_UP)
 796                         clock.p2 = limit->p2.p2_fast;
 797                 else
 798                         clock.p2 = limit->p2.p2_slow;
 799         } else {
 800                 if (target < limit->p2.dot_limit)
 801                         clock.p2 = limit->p2.p2_slow;
 802                 else
 803                         clock.p2 = limit->p2.p2_fast;
 804         }
 805
 806         memset(best_clock, 0, sizeof(*best_clock));
 807         max_n = limit->n.max;
 808         /* based on hardware requriment prefer smaller n to precision */
 809         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 810                 /* based on hardware requirment prefere larger m1,m2 */
 811                 for (clock.m1 = limit->m1.max;
 812                      clock.m1 >= limit->m1.min; clock.m1--) {
 813                         for (clock.m2 = limit->m2.max;
 814                              clock.m2 >= limit->m2.min; clock.m2--) {
 815                                 for (clock.p1 = limit->p1.max;
 816                                      clock.p1 >= limit->p1.min; clock.p1--) {
 817                                         int this_err;
 818
 819                                         intel_clock(dev, refclk, &clock);
 820                                         if (!intel_PLL_is_valid(crtc, &clock))
 821                                                 continue;
 822                                         this_err = abs(clock.dot - target) ;
 823                                         if (this_err < err_most) {
 824                                                 *best_clock = clock;
 825                                                 err_most = this_err;
 826                                                 max_n = clock.n;
 827                                                 found = true;
 828                                         }
 829                                 }
 830                         }
 831                 }
 832         }
 833         return found;
 834 }
 835
 836 static bool
 837 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 838                            int target, int refclk, intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->dev;
 841         intel_clock_t clock;
 842         if (target < 200000) {
 843                 clock.n = 1;
 844                 clock.p1 = 2;
 845                 clock.p2 = 10;
 846                 clock.m1 = 12;
 847                 clock.m2 = 9;
 848         } else {
 849                 clock.n = 2;
 850                 clock.p1 = 1;
 851                 clock.p2 = 10;
 852                 clock.m1 = 14;
 853                 clock.m2 = 8;
 854         }
 855         intel_clock(dev, refclk, &clock);
 856         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 857         return true;
 858 }
 859
 860 static bool
 861 intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 862                              int target, int refclk, intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc->dev;
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         intel_clock_t clock;
 867         int err_most = 47;
 868         int err_min = 10000;
 869
 870         /* eDP has only 2 clock choice, no n/m/p setting */
 871         if (HAS_eDP)
 872                 return true;
 873
 874         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 875                 return intel_find_pll_ironlake_dp(limit, crtc, target,
 876                                                refclk, best_clock);
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 880                     LVDS_CLKB_POWER_UP)
 881                         clock.p2 = limit->p2.p2_fast;
 882                 else
 883                         clock.p2 = limit->p2.p2_slow;
 884         } else {
 885                 if (target < limit->p2.dot_limit)
 886                         clock.p2 = limit->p2.p2_slow;
 887                 else
 888                         clock.p2 = limit->p2.p2_fast;
 889         }
 890
 891         memset(best_clock, 0, sizeof(*best_clock));
 892         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 893                 /* based on hardware requriment prefer smaller n to precision */
 894                 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
 895                         /* based on hardware requirment prefere larger m1,m2 */
 896                         for (clock.m1 = limit->m1.max;
 897                              clock.m1 >= limit->m1.min; clock.m1--) {
 898                                 for (clock.m2 = limit->m2.max;
 899                                      clock.m2 >= limit->m2.min; clock.m2--) {
 900                                         int this_err;
 901
 902                                         intel_clock(dev, refclk, &clock);
 903                                         if (!intel_PLL_is_valid(crtc, &clock))
 904                                                 continue;
 905                                         this_err = abs((10000 - (target*10000/clock.dot)));
 906                                         if (this_err < err_most) {
 907                                                 *best_clock = clock;
 908                                                 /* found on first matching */
 909                                                 goto out;
 910                                         } else if (this_err < err_min) {
 911                                                 *best_clock = clock;
 912                                                 err_min = this_err;
 913                                         }
 914                                 }
 915                         }
 916                 }
 917         }
 918 out:
 919         return true;
 920 }
 921
 922 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 923 static bool
 924 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 925                       int target, int refclk, intel_clock_t *best_clock)
 926 {
 927     intel_clock_t clock;
 928     if (target < 200000) {
 929         clock.p1 = 2;
 930         clock.p2 = 10;
 931         clock.n = 2;
 932         clock.m1 = 23;
 933         clock.m2 = 8;
 934     } else {
 935         clock.p1 = 1;
 936         clock.p2 = 10;
 937         clock.n = 1;
 938         clock.m1 = 14;
 939         clock.m2 = 2;
 940     }
 941     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 942     clock.p = (clock.p1 * clock.p2);
 943     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 944     clock.vco = 0;
 945     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 946     return true;
 947 }
 948
 949 void
 950 intel_wait_for_vblank(struct drm_device *dev)
 951 {
 952         /* Wait for 20ms, i.e. one cycle at 50hz. */
 953         msleep(20);
 954 }
 955
 956 /* Parameters have changed, update FBC info */
 957 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 958 {
 959         struct drm_device *dev = crtc->dev;
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         struct drm_framebuffer *fb = crtc->fb;
 962         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 963         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 965         int plane, i;
 966         u32 fbc_ctl, fbc_ctl2;
 967
 968         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 969
 970         if (fb->pitch < dev_priv->cfb_pitch)
 971                 dev_priv->cfb_pitch = fb->pitch;
 972
 973         /* FBC_CTL wants 64B units */
 974         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 975         dev_priv->cfb_fence = obj_priv->fence_reg;
 976         dev_priv->cfb_plane = intel_crtc->plane;
 977         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 978
 979         /* Clear old tags */
 980         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 981                 I915_WRITE(FBC_TAG + (i * 4), 0);
 982
 983         /* Set it up... */
 984         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 985         if (obj_priv->tiling_mode != I915_TILING_NONE)
 986                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 987         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 988         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 989
 990         /* enable it... */
 991         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 992         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 993         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 994         if (obj_priv->tiling_mode != I915_TILING_NONE)
 995                 fbc_ctl |= dev_priv->cfb_fence;
 996         I915_WRITE(FBC_CONTROL, fbc_ctl);
 997
 998         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
 999                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1000 }
1001
1002 void i8xx_disable_fbc(struct drm_device *dev)
1003 {
1004         struct drm_i915_private *dev_priv = dev->dev_private;
1005         u32 fbc_ctl;
1006
1007         if (!I915_HAS_FBC(dev))
1008                 return;
1009
1010         /* Disable compression */
1011         fbc_ctl = I915_READ(FBC_CONTROL);
1012         fbc_ctl &= ~FBC_CTL_EN;
1013         I915_WRITE(FBC_CONTROL, fbc_ctl);
1014
1015         /* Wait for compressing bit to clear */
1016         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1017                 ; /* nothing */
1018
1019         intel_wait_for_vblank(dev);
1020
1021         DRM_DEBUG_KMS("disabled FBC\n");
1022 }
1023
1024 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1025 {
1026         struct drm_device *dev = crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028
1029         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1030 }
1031
1032 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1033 {
1034         struct drm_device *dev = crtc->dev;
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         struct drm_framebuffer *fb = crtc->fb;
1037         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1038         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1040         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1041                      DPFC_CTL_PLANEB);
1042         unsigned long stall_watermark = 200;
1043         u32 dpfc_ctl;
1044
1045         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1046         dev_priv->cfb_fence = obj_priv->fence_reg;
1047         dev_priv->cfb_plane = intel_crtc->plane;
1048
1049         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1050         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1051                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1052                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1053         } else {
1054                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1055         }
1056
1057         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1058         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1059                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1060                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1061         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1062
1063         /* enable it... */
1064         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1065
1066         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1067 }
1068
1069 void g4x_disable_fbc(struct drm_device *dev)
1070 {
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         u32 dpfc_ctl;
1073
1074         /* Disable compression */
1075         dpfc_ctl = I915_READ(DPFC_CONTROL);
1076         dpfc_ctl &= ~DPFC_CTL_EN;
1077         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1078         intel_wait_for_vblank(dev);
1079
1080         DRM_DEBUG_KMS("disabled FBC\n");
1081 }
1082
1083 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1084 {
1085         struct drm_device *dev = crtc->dev;
1086         struct drm_i915_private *dev_priv = dev->dev_private;
1087
1088         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1089 }
1090
1091 /**
1092  * intel_update_fbc - enable/disable FBC as needed
1093  * @crtc: CRTC to point the compressor at
1094  * @mode: mode in use
1095  *
1096  * Set up the framebuffer compression hardware at mode set time.  We
1097  * enable it if possible:
1098  *   - plane A only (on pre-965)
1099  *   - no pixel mulitply/line duplication
1100  *   - no alpha buffer discard
1101  *   - no dual wide
1102  *   - framebuffer <= 2048 in width, 1536 in height
1103  *
1104  * We can't assume that any compression will take place (worst case),
1105  * so the compressed buffer has to be the same size as the uncompressed
1106  * one.  It also must reside (along with the line length buffer) in
1107  * stolen memory.
1108  *
1109  * We need to enable/disable FBC on a global basis.
1110  */
1111 static void intel_update_fbc(struct drm_crtc *crtc,
1112                              struct drm_display_mode *mode)
1113 {
1114         struct drm_device *dev = crtc->dev;
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         struct drm_framebuffer *fb = crtc->fb;
1117         struct intel_framebuffer *intel_fb;
1118         struct drm_i915_gem_object *obj_priv;
1119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1120         int plane = intel_crtc->plane;
1121
1122         if (!i915_powersave)
1123                 return;
1124
1125         if (!dev_priv->display.fbc_enabled ||
1126             !dev_priv->display.enable_fbc ||
1127             !dev_priv->display.disable_fbc)
1128                 return;
1129
1130         if (!crtc->fb)
1131                 return;
1132
1133         intel_fb = to_intel_framebuffer(fb);
1134         obj_priv = intel_fb->obj->driver_private;
1135
1136         /*
1137          * If FBC is already on, we just have to verify that we can
1138          * keep it that way...
1139          * Need to disable if:
1140          *   - changing FBC params (stride, fence, mode)
1141          *   - new fb is too large to fit in compressed buffer
1142          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1143          */
1144         if (intel_fb->obj->size > dev_priv->cfb_size) {
1145                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1146                                 "compression\n");
1147                 goto out_disable;
1148         }
1149         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1150             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1151                 DRM_DEBUG_KMS("mode incompatible with compression, "
1152                                 "disabling\n");
1153                 goto out_disable;
1154         }
1155         if ((mode->hdisplay > 2048) ||
1156             (mode->vdisplay > 1536)) {
1157                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1158                 goto out_disable;
1159         }
1160         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1161                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1162                 goto out_disable;
1163         }
1164         if (obj_priv->tiling_mode != I915_TILING_X) {
1165                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1166                 goto out_disable;
1167         }
1168
1169         if (dev_priv->display.fbc_enabled(crtc)) {
1170                 /* We can re-enable it in this case, but need to update pitch */
1171                 if (fb->pitch > dev_priv->cfb_pitch)
1172                         dev_priv->display.disable_fbc(dev);
1173                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1174                         dev_priv->display.disable_fbc(dev);
1175                 if (plane != dev_priv->cfb_plane)
1176                         dev_priv->display.disable_fbc(dev);
1177         }
1178
1179         if (!dev_priv->display.fbc_enabled(crtc)) {
1180                 /* Now try to turn it back on if possible */
1181                 dev_priv->display.enable_fbc(crtc, 500);
1182         }
1183
1184         return;
1185
1186 out_disable:
1187         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1188         /* Multiple disables should be harmless */
1189         if (dev_priv->display.fbc_enabled(crtc))
1190                 dev_priv->display.disable_fbc(dev);
1191 }
1192
1193 static int
1194 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1195 {
1196         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1197         u32 alignment;
1198         int ret;
1199
1200         switch (obj_priv->tiling_mode) {
1201         case I915_TILING_NONE:
1202                 alignment = 64 * 1024;
1203                 break;
1204         case I915_TILING_X:
1205                 /* pin() will align the object as required by fence */
1206                 alignment = 0;
1207                 break;
1208         case I915_TILING_Y:
1209                 /* FIXME: Is this true? */
1210                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1211                 return -EINVAL;
1212         default:
1213                 BUG();
1214         }
1215
1216         ret = i915_gem_object_pin(obj, alignment);
1217         if (ret != 0)
1218                 return ret;
1219
1220         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1221          * fence, whereas 965+ only requires a fence if using
1222          * framebuffer compression.  For simplicity, we always install
1223          * a fence as the cost is not that onerous.
1224          */
1225         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1226             obj_priv->tiling_mode != I915_TILING_NONE) {
1227                 ret = i915_gem_object_get_fence_reg(obj);
1228                 if (ret != 0) {
1229                         i915_gem_object_unpin(obj);
1230                         return ret;
1231                 }
1232         }
1233
1234         return 0;
1235 }
1236
1237 static int
1238 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1239                     struct drm_framebuffer *old_fb)
1240 {
1241         struct drm_device *dev = crtc->dev;
1242         struct drm_i915_private *dev_priv = dev->dev_private;
1243         struct drm_i915_master_private *master_priv;
1244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1245         struct intel_framebuffer *intel_fb;
1246         struct drm_i915_gem_object *obj_priv;
1247         struct drm_gem_object *obj;
1248         int pipe = intel_crtc->pipe;
1249         int plane = intel_crtc->plane;
1250         unsigned long Start, Offset;
1251         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1252         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1253         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1254         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1255         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1256         u32 dspcntr;
1257         int ret;
1258
1259         /* no fb bound */
1260         if (!crtc->fb) {
1261                 DRM_DEBUG_KMS("No FB bound\n");
1262                 return 0;
1263         }
1264
1265         switch (plane) {
1266         case 0:
1267         case 1:
1268                 break;
1269         default:
1270                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1271                 return -EINVAL;
1272         }
1273
1274         intel_fb = to_intel_framebuffer(crtc->fb);
1275         obj = intel_fb->obj;
1276         obj_priv = obj->driver_private;
1277
1278         mutex_lock(&dev->struct_mutex);
1279         ret = intel_pin_and_fence_fb_obj(dev, obj);
1280         if (ret != 0) {
1281                 mutex_unlock(&dev->struct_mutex);
1282                 return ret;
1283         }
1284
1285         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1286         if (ret != 0) {
1287                 i915_gem_object_unpin(obj);
1288                 mutex_unlock(&dev->struct_mutex);
1289                 return ret;
1290         }
1291
1292         dspcntr = I915_READ(dspcntr_reg);
1293         /* Mask out pixel format bits in case we change it */
1294         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1295         switch (crtc->fb->bits_per_pixel) {
1296         case 8:
1297                 dspcntr |= DISPPLANE_8BPP;
1298                 break;
1299         case 16:
1300                 if (crtc->fb->depth == 15)
1301                         dspcntr |= DISPPLANE_15_16BPP;
1302                 else
1303                         dspcntr |= DISPPLANE_16BPP;
1304                 break;
1305         case 24:
1306         case 32:
1307                 if (crtc->fb->depth == 30)
1308                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1309                 else
1310                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1311                 break;
1312         default:
1313                 DRM_ERROR("Unknown color depth\n");
1314                 i915_gem_object_unpin(obj);
1315                 mutex_unlock(&dev->struct_mutex);
1316                 return -EINVAL;
1317         }
1318         if (IS_I965G(dev)) {
1319                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1320                         dspcntr |= DISPPLANE_TILED;
1321                 else
1322                         dspcntr &= ~DISPPLANE_TILED;
1323         }
1324
1325         if (IS_IRONLAKE(dev))
1326                 /* must disable */
1327                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1328
1329         I915_WRITE(dspcntr_reg, dspcntr);
1330
1331         Start = obj_priv->gtt_offset;
1332         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1333
1334         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1335         I915_WRITE(dspstride, crtc->fb->pitch);
1336         if (IS_I965G(dev)) {
1337                 I915_WRITE(dspbase, Offset);
1338                 I915_READ(dspbase);
1339                 I915_WRITE(dspsurf, Start);
1340                 I915_READ(dspsurf);
1341                 I915_WRITE(dsptileoff, (y << 16) | x);
1342         } else {
1343                 I915_WRITE(dspbase, Start + Offset);
1344                 I915_READ(dspbase);
1345         }
1346
1347         if ((IS_I965G(dev) || plane == 0))
1348                 intel_update_fbc(crtc, &crtc->mode);
1349
1350         intel_wait_for_vblank(dev);
1351
1352         if (old_fb) {
1353                 intel_fb = to_intel_framebuffer(old_fb);
1354                 obj_priv = intel_fb->obj->driver_private;
1355                 i915_gem_object_unpin(intel_fb->obj);
1356         }
1357         intel_increase_pllclock(crtc, true);
1358
1359         mutex_unlock(&dev->struct_mutex);
1360
1361         if (!dev->primary->master)
1362                 return 0;
1363
1364         master_priv = dev->primary->master->driver_priv;
1365         if (!master_priv->sarea_priv)
1366                 return 0;
1367
1368         if (pipe) {
1369                 master_priv->sarea_priv->pipeB_x = x;
1370                 master_priv->sarea_priv->pipeB_y = y;
1371         } else {
1372                 master_priv->sarea_priv->pipeA_x = x;
1373                 master_priv->sarea_priv->pipeA_y = y;
1374         }
1375
1376         return 0;
1377 }
1378
1379 /* Disable the VGA plane that we never use */
1380 static void i915_disable_vga (struct drm_device *dev)
1381 {
1382         struct drm_i915_private *dev_priv = dev->dev_private;
1383         u8 sr1;
1384         u32 vga_reg;
1385
1386         if (IS_IRONLAKE(dev))
1387                 vga_reg = CPU_VGACNTRL;
1388         else
1389                 vga_reg = VGACNTRL;
1390
1391         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1392                 return;
1393
1394         I915_WRITE8(VGA_SR_INDEX, 1);
1395         sr1 = I915_READ8(VGA_SR_DATA);
1396         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1397         udelay(100);
1398
1399         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1400 }
1401
1402 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1403 {
1404         struct drm_device *dev = crtc->dev;
1405         struct drm_i915_private *dev_priv = dev->dev_private;
1406         u32 dpa_ctl;
1407
1408         DRM_DEBUG_KMS("\n");
1409         dpa_ctl = I915_READ(DP_A);
1410         dpa_ctl &= ~DP_PLL_ENABLE;
1411         I915_WRITE(DP_A, dpa_ctl);
1412 }
1413
1414 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1415 {
1416         struct drm_device *dev = crtc->dev;
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418         u32 dpa_ctl;
1419
1420         dpa_ctl = I915_READ(DP_A);
1421         dpa_ctl |= DP_PLL_ENABLE;
1422         I915_WRITE(DP_A, dpa_ctl);
1423         udelay(200);
1424 }
1425
1426
1427 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1428 {
1429         struct drm_device *dev = crtc->dev;
1430         struct drm_i915_private *dev_priv = dev->dev_private;
1431         u32 dpa_ctl;
1432
1433         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1434         dpa_ctl = I915_READ(DP_A);
1435         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1436
1437         if (clock < 200000) {
1438                 u32 temp;
1439                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1440                 /* workaround for 160Mhz:
1441                    1) program 0x4600c bits 15:0 = 0x8124
1442                    2) program 0x46010 bit 0 = 1
1443                    3) program 0x46034 bit 24 = 1
1444                    4) program 0x64000 bit 14 = 1
1445                    */
1446                 temp = I915_READ(0x4600c);
1447                 temp &= 0xffff0000;
1448                 I915_WRITE(0x4600c, temp | 0x8124);
1449
1450                 temp = I915_READ(0x46010);
1451                 I915_WRITE(0x46010, temp | 1);
1452
1453                 temp = I915_READ(0x46034);
1454                 I915_WRITE(0x46034, temp | (1 << 24));
1455         } else {
1456                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1457         }
1458         I915_WRITE(DP_A, dpa_ctl);
1459
1460         udelay(500);
1461 }
1462
1463 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1464 {
1465         struct drm_device *dev = crtc->dev;
1466         struct drm_i915_private *dev_priv = dev->dev_private;
1467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1468         int pipe = intel_crtc->pipe;
1469         int plane = intel_crtc->plane;
1470         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1471         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1472         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1473         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1474         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1475         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1476         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1477         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1478         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1479         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1480         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1481         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1482         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1483         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1484         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1485         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1486         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1487         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1488         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1489         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1490         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1491         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1492         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1493         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1494         u32 temp;
1495         int tries = 5, j, n;
1496         u32 pipe_bpc;
1497
1498         temp = I915_READ(pipeconf_reg);
1499         pipe_bpc = temp & PIPE_BPC_MASK;
1500
1501         /* XXX: When our outputs are all unaware of DPMS modes other than off
1502          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1503          */
1504         switch (mode) {
1505         case DRM_MODE_DPMS_ON:
1506         case DRM_MODE_DPMS_STANDBY:
1507         case DRM_MODE_DPMS_SUSPEND:
1508                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1509
1510                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1511                         temp = I915_READ(PCH_LVDS);
1512                         if ((temp & LVDS_PORT_EN) == 0) {
1513                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1514                                 POSTING_READ(PCH_LVDS);
1515                         }
1516                 }
1517
1518                 if (HAS_eDP) {
1519                         /* enable eDP PLL */
1520                         ironlake_enable_pll_edp(crtc);
1521                 } else {
1522                         /* enable PCH DPLL */
1523                         temp = I915_READ(pch_dpll_reg);
1524                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1525                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1526                                 I915_READ(pch_dpll_reg);
1527                         }
1528
1529                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1530                         temp = I915_READ(fdi_rx_reg);
1531                         /*
1532                          * make the BPC in FDI Rx be consistent with that in
1533                          * pipeconf reg.
1534                          */
1535                         temp &= ~(0x7 << 16);
1536                         temp |= (pipe_bpc << 11);
1537                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1538                                         FDI_SEL_PCDCLK |
1539                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1540                         I915_READ(fdi_rx_reg);
1541                         udelay(200);
1542
1543                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1544                         temp = I915_READ(fdi_tx_reg);
1545                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1546                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1547                                 I915_READ(fdi_tx_reg);
1548                                 udelay(100);
1549                         }
1550                 }
1551
1552                 /* Enable panel fitting for LVDS */
1553                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1554                         temp = I915_READ(pf_ctl_reg);
1555                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1556
1557                         /* currently full aspect */
1558                         I915_WRITE(pf_win_pos, 0);
1559
1560                         I915_WRITE(pf_win_size,
1561                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1562                                    (dev_priv->panel_fixed_mode->vdisplay));
1563                 }
1564
1565                 /* Enable CPU pipe */
1566                 temp = I915_READ(pipeconf_reg);
1567                 if ((temp & PIPEACONF_ENABLE) == 0) {
1568                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1569                         I915_READ(pipeconf_reg);
1570                         udelay(100);
1571                 }
1572
1573                 /* configure and enable CPU plane */
1574                 temp = I915_READ(dspcntr_reg);
1575                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1576                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1577                         /* Flush the plane changes */
1578                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1579                 }
1580
1581                 if (!HAS_eDP) {
1582                         /* enable CPU FDI TX and PCH FDI RX */
1583                         temp = I915_READ(fdi_tx_reg);
1584                         temp |= FDI_TX_ENABLE;
1585                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1586                         temp &= ~FDI_LINK_TRAIN_NONE;
1587                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1588                         I915_WRITE(fdi_tx_reg, temp);
1589                         I915_READ(fdi_tx_reg);
1590
1591                         temp = I915_READ(fdi_rx_reg);
1592                         temp &= ~FDI_LINK_TRAIN_NONE;
1593                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1594                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1595                         I915_READ(fdi_rx_reg);
1596
1597                         udelay(150);
1598
1599                         /* Train FDI. */
1600                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1601                            for train result */
1602                         temp = I915_READ(fdi_rx_imr_reg);
1603                         temp &= ~FDI_RX_SYMBOL_LOCK;
1604                         temp &= ~FDI_RX_BIT_LOCK;
1605                         I915_WRITE(fdi_rx_imr_reg, temp);
1606                         I915_READ(fdi_rx_imr_reg);
1607                         udelay(150);
1608
1609                         temp = I915_READ(fdi_rx_iir_reg);
1610                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1611
1612                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1613                                 for (j = 0; j < tries; j++) {
1614                                         temp = I915_READ(fdi_rx_iir_reg);
1615                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1616                                                                 temp);
1617                                         if (temp & FDI_RX_BIT_LOCK)
1618                                                 break;
1619                                         udelay(200);
1620                                 }
1621                                 if (j != tries)
1622                                         I915_WRITE(fdi_rx_iir_reg,
1623                                                         temp | FDI_RX_BIT_LOCK);
1624                                 else
1625                                         DRM_DEBUG_KMS("train 1 fail\n");
1626                         } else {
1627                                 I915_WRITE(fdi_rx_iir_reg,
1628                                                 temp | FDI_RX_BIT_LOCK);
1629                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1630                         }
1631                         temp = I915_READ(fdi_tx_reg);
1632                         temp &= ~FDI_LINK_TRAIN_NONE;
1633                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1634                         I915_WRITE(fdi_tx_reg, temp);
1635
1636                         temp = I915_READ(fdi_rx_reg);
1637                         temp &= ~FDI_LINK_TRAIN_NONE;
1638                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1639                         I915_WRITE(fdi_rx_reg, temp);
1640
1641                         udelay(150);
1642
1643                         temp = I915_READ(fdi_rx_iir_reg);
1644                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1645
1646                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1647                                 for (j = 0; j < tries; j++) {
1648                                         temp = I915_READ(fdi_rx_iir_reg);
1649                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1650                                                                 temp);
1651                                         if (temp & FDI_RX_SYMBOL_LOCK)
1652                                                 break;
1653                                         udelay(200);
1654                                 }
1655                                 if (j != tries) {
1656                                         I915_WRITE(fdi_rx_iir_reg,
1657                                                         temp | FDI_RX_SYMBOL_LOCK);
1658                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1659                                 } else
1660                                         DRM_DEBUG_KMS("train 2 fail\n");
1661                         } else {
1662                                 I915_WRITE(fdi_rx_iir_reg,
1663                                                 temp | FDI_RX_SYMBOL_LOCK);
1664                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1665                         }
1666                         DRM_DEBUG_KMS("train done\n");
1667
1668                         /* set transcoder timing */
1669                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1670                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1671                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1672
1673                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1674                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1675                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1676
1677                         /* enable PCH transcoder */
1678                         temp = I915_READ(transconf_reg);
1679                         /*
1680                          * make the BPC in transcoder be consistent with
1681                          * that in pipeconf reg.
1682                          */
1683                         temp &= ~PIPE_BPC_MASK;
1684                         temp |= pipe_bpc;
1685                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1686                         I915_READ(transconf_reg);
1687
1688                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1689                                 ;
1690
1691                         /* enable normal */
1692
1693                         temp = I915_READ(fdi_tx_reg);
1694                         temp &= ~FDI_LINK_TRAIN_NONE;
1695                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1696                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1697                         I915_READ(fdi_tx_reg);
1698
1699                         temp = I915_READ(fdi_rx_reg);
1700                         temp &= ~FDI_LINK_TRAIN_NONE;
1701                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1702                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1703                         I915_READ(fdi_rx_reg);
1704
1705                         /* wait one idle pattern time */
1706                         udelay(100);
1707
1708                 }
1709
1710                 intel_crtc_load_lut(crtc);
1711
1712         break;
1713         case DRM_MODE_DPMS_OFF:
1714                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1715
1716                 /* Disable display plane */
1717                 temp = I915_READ(dspcntr_reg);
1718                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1719                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1720                         /* Flush the plane changes */
1721                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1722                         I915_READ(dspbase_reg);
1723                 }
1724
1725                 i915_disable_vga(dev);
1726
1727                 /* disable cpu pipe, disable after all planes disabled */
1728                 temp = I915_READ(pipeconf_reg);
1729                 if ((temp & PIPEACONF_ENABLE) != 0) {
1730                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1731                         I915_READ(pipeconf_reg);
1732                         n = 0;
1733                         /* wait for cpu pipe off, pipe state */
1734                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1735                                 n++;
1736                                 if (n < 60) {
1737                                         udelay(500);
1738                                         continue;
1739                                 } else {
1740                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1741                                                                 pipe);
1742                                         break;
1743                                 }
1744                         }
1745                 } else
1746                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1747
1748                 udelay(100);
1749
1750                 /* Disable PF */
1751                 temp = I915_READ(pf_ctl_reg);
1752                 if ((temp & PF_ENABLE) != 0) {
1753                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1754                         I915_READ(pf_ctl_reg);
1755                 }
1756                 I915_WRITE(pf_win_size, 0);
1757
1758                 /* disable CPU FDI tx and PCH FDI rx */
1759                 temp = I915_READ(fdi_tx_reg);
1760                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1761                 I915_READ(fdi_tx_reg);
1762
1763                 temp = I915_READ(fdi_rx_reg);
1764                 /* BPC in FDI rx is consistent with that in pipeconf */
1765                 temp &= ~(0x07 << 16);
1766                 temp |= (pipe_bpc << 11);
1767                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1768                 I915_READ(fdi_rx_reg);
1769
1770                 udelay(100);
1771
1772                 /* still set train pattern 1 */
1773                 temp = I915_READ(fdi_tx_reg);
1774                 temp &= ~FDI_LINK_TRAIN_NONE;
1775                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1776                 I915_WRITE(fdi_tx_reg, temp);
1777
1778                 temp = I915_READ(fdi_rx_reg);
1779                 temp &= ~FDI_LINK_TRAIN_NONE;
1780                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1781                 I915_WRITE(fdi_rx_reg, temp);
1782
1783                 udelay(100);
1784
1785                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1786                         temp = I915_READ(PCH_LVDS);
1787                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1788                         I915_READ(PCH_LVDS);
1789                         udelay(100);
1790                 }
1791
1792                 /* disable PCH transcoder */
1793                 temp = I915_READ(transconf_reg);
1794                 if ((temp & TRANS_ENABLE) != 0) {
1795                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1796                         I915_READ(transconf_reg);
1797                         n = 0;
1798                         /* wait for PCH transcoder off, transcoder state */
1799                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1800                                 n++;
1801                                 if (n < 60) {
1802                                         udelay(500);
1803                                         continue;
1804                                 } else {
1805                                         DRM_DEBUG_KMS("transcoder %d off "
1806                                                         "delay\n", pipe);
1807                                         break;
1808                                 }
1809                         }
1810                 }
1811                 temp = I915_READ(transconf_reg);
1812                 /* BPC in transcoder is consistent with that in pipeconf */
1813                 temp &= ~PIPE_BPC_MASK;
1814                 temp |= pipe_bpc;
1815                 I915_WRITE(transconf_reg, temp);
1816                 I915_READ(transconf_reg);
1817                 udelay(100);
1818
1819                 /* disable PCH DPLL */
1820                 temp = I915_READ(pch_dpll_reg);
1821                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1822                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1823                         I915_READ(pch_dpll_reg);
1824                 }
1825
1826                 if (HAS_eDP) {
1827                         ironlake_disable_pll_edp(crtc);
1828                 }
1829
1830                 temp = I915_READ(fdi_rx_reg);
1831                 temp &= ~FDI_SEL_PCDCLK;
1832                 I915_WRITE(fdi_rx_reg, temp);
1833                 I915_READ(fdi_rx_reg);
1834
1835                 temp = I915_READ(fdi_rx_reg);
1836                 temp &= ~FDI_RX_PLL_ENABLE;
1837                 I915_WRITE(fdi_rx_reg, temp);
1838                 I915_READ(fdi_rx_reg);
1839
1840                 /* Disable CPU FDI TX PLL */
1841                 temp = I915_READ(fdi_tx_reg);
1842                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1843                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1844                         I915_READ(fdi_tx_reg);
1845                         udelay(100);
1846                 }
1847
1848                 /* Wait for the clocks to turn off. */
1849                 udelay(100);
1850                 break;
1851         }
1852 }
1853
1854 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1855 {
1856         struct intel_overlay *overlay;
1857         int ret;
1858
1859         if (!enable && intel_crtc->overlay) {
1860                 overlay = intel_crtc->overlay;
1861                 mutex_lock(&overlay->dev->struct_mutex);
1862                 for (;;) {
1863                         ret = intel_overlay_switch_off(overlay);
1864                         if (ret == 0)
1865                                 break;
1866
1867                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1868                         if (ret != 0) {
1869                                 /* overlay doesn't react anymore. Usually
1870                                  * results in a black screen and an unkillable
1871                                  * X server. */
1872                                 BUG();
1873                                 overlay->hw_wedged = HW_WEDGED;
1874                                 break;
1875                         }
1876                 }
1877                 mutex_unlock(&overlay->dev->struct_mutex);
1878         }
1879         /* Let userspace switch the overlay on again. In most cases userspace
1880          * has to recompute where to put it anyway. */
1881
1882         return;
1883 }
1884
1885 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1886 {
1887         struct drm_device *dev = crtc->dev;
1888         struct drm_i915_private *dev_priv = dev->dev_private;
1889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1890         int pipe = intel_crtc->pipe;
1891         int plane = intel_crtc->plane;
1892         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1893         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1894         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1895         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1896         u32 temp;
1897
1898         /* XXX: When our outputs are all unaware of DPMS modes other than off
1899          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1900          */
1901         switch (mode) {
1902         case DRM_MODE_DPMS_ON:
1903         case DRM_MODE_DPMS_STANDBY:
1904         case DRM_MODE_DPMS_SUSPEND:
1905                 intel_update_watermarks(dev);
1906
1907                 /* Enable the DPLL */
1908                 temp = I915_READ(dpll_reg);
1909                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1910                         I915_WRITE(dpll_reg, temp);
1911                         I915_READ(dpll_reg);
1912                         /* Wait for the clocks to stabilize. */
1913                         udelay(150);
1914                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1915                         I915_READ(dpll_reg);
1916                         /* Wait for the clocks to stabilize. */
1917                         udelay(150);
1918                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1919                         I915_READ(dpll_reg);
1920                         /* Wait for the clocks to stabilize. */
1921                         udelay(150);
1922                 }
1923
1924                 /* Enable the pipe */
1925                 temp = I915_READ(pipeconf_reg);
1926                 if ((temp & PIPEACONF_ENABLE) == 0)
1927                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1928
1929                 /* Enable the plane */
1930                 temp = I915_READ(dspcntr_reg);
1931                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1932                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1933                         /* Flush the plane changes */
1934                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1935                 }
1936
1937                 intel_crtc_load_lut(crtc);
1938
1939                 if ((IS_I965G(dev) || plane == 0))
1940                         intel_update_fbc(crtc, &crtc->mode);
1941
1942                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1943                 intel_crtc_dpms_overlay(intel_crtc, true);
1944         break;
1945         case DRM_MODE_DPMS_OFF:
1946                 intel_update_watermarks(dev);
1947
1948                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1949                 intel_crtc_dpms_overlay(intel_crtc, false);
1950                 drm_vblank_off(dev, pipe);
1951
1952                 if (dev_priv->cfb_plane == plane &&
1953                     dev_priv->display.disable_fbc)
1954                         dev_priv->display.disable_fbc(dev);
1955
1956                 /* Disable the VGA plane that we never use */
1957                 i915_disable_vga(dev);
1958
1959                 /* Disable display plane */
1960                 temp = I915_READ(dspcntr_reg);
1961                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1962                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1963                         /* Flush the plane changes */
1964                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1965                         I915_READ(dspbase_reg);
1966                 }
1967
1968                 if (!IS_I9XX(dev)) {
1969                         /* Wait for vblank for the disable to take effect */
1970                         intel_wait_for_vblank(dev);
1971                 }
1972
1973                 /* Next, disable display pipes */
1974                 temp = I915_READ(pipeconf_reg);
1975                 if ((temp & PIPEACONF_ENABLE) != 0) {
1976                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1977                         I915_READ(pipeconf_reg);
1978                 }
1979
1980                 /* Wait for vblank for the disable to take effect. */
1981                 intel_wait_for_vblank(dev);
1982
1983                 temp = I915_READ(dpll_reg);
1984                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1985                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1986                         I915_READ(dpll_reg);
1987                 }
1988
1989                 /* Wait for the clocks to turn off. */
1990                 udelay(150);
1991                 break;
1992         }
1993 }
1994
1995 /**
1996  * Sets the power management mode of the pipe and plane.
1997  *
1998  * This code should probably grow support for turning the cursor off and back
1999  * on appropriately at the same time as we're turning the pipe off/on.
2000  */
2001 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2002 {
2003         struct drm_device *dev = crtc->dev;
2004         struct drm_i915_private *dev_priv = dev->dev_private;
2005         struct drm_i915_master_private *master_priv;
2006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2007         int pipe = intel_crtc->pipe;
2008         bool enabled;
2009
2010         dev_priv->display.dpms(crtc, mode);
2011
2012         intel_crtc->dpms_mode = mode;
2013
2014         if (!dev->primary->master)
2015                 return;
2016
2017         master_priv = dev->primary->master->driver_priv;
2018         if (!master_priv->sarea_priv)
2019                 return;
2020
2021         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2022
2023         switch (pipe) {
2024         case 0:
2025                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2026                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2027                 break;
2028         case 1:
2029                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2030                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2031                 break;
2032         default:
2033                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2034                 break;
2035         }
2036 }
2037
2038 static void intel_crtc_prepare (struct drm_crtc *crtc)
2039 {
2040         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2041         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2042 }
2043
2044 static void intel_crtc_commit (struct drm_crtc *crtc)
2045 {
2046         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2047         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2048 }
2049
2050 void intel_encoder_prepare (struct drm_encoder *encoder)
2051 {
2052         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2053         /* lvds has its own version of prepare see intel_lvds_prepare */
2054         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2055 }
2056
2057 void intel_encoder_commit (struct drm_encoder *encoder)
2058 {
2059         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2060         /* lvds has its own version of commit see intel_lvds_commit */
2061         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2062 }
2063
2064 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2065                                   struct drm_display_mode *mode,
2066                                   struct drm_display_mode *adjusted_mode)
2067 {
2068         struct drm_device *dev = crtc->dev;
2069         if (IS_IRONLAKE(dev)) {
2070                 /* FDI link clock is fixed at 2.7G */
2071                 if (mode->clock * 3 > 27000 * 4)
2072                         return MODE_CLOCK_HIGH;
2073         }
2074         return true;
2075 }
2076
2077 static int i945_get_display_clock_speed(struct drm_device *dev)
2078 {
2079         return 400000;
2080 }
2081
2082 static int i915_get_display_clock_speed(struct drm_device *dev)
2083 {
2084         return 333000;
2085 }
2086
2087 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2088 {
2089         return 200000;
2090 }
2091
2092 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2093 {
2094         u16 gcfgc = 0;
2095
2096         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2097
2098         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2099                 return 133000;
2100         else {
2101                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2102                 case GC_DISPLAY_CLOCK_333_MHZ:
2103                         return 333000;
2104                 default:
2105                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2106                         return 190000;
2107                 }
2108         }
2109 }
2110
2111 static int i865_get_display_clock_speed(struct drm_device *dev)
2112 {
2113         return 266000;
2114 }
2115
2116 static int i855_get_display_clock_speed(struct drm_device *dev)
2117 {
2118         u16 hpllcc = 0;
2119         /* Assume that the hardware is in the high speed state.  This
2120          * should be the default.
2121          */
2122         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2123         case GC_CLOCK_133_200:
2124         case GC_CLOCK_100_200:
2125                 return 200000;
2126         case GC_CLOCK_166_250:
2127                 return 250000;
2128         case GC_CLOCK_100_133:
2129                 return 133000;
2130         }
2131
2132         /* Shouldn't happen */
2133         return 0;
2134 }
2135
2136 static int i830_get_display_clock_speed(struct drm_device *dev)
2137 {
2138         return 133000;
2139 }
2140
2141 /**
2142  * Return the pipe currently connected to the panel fitter,
2143  * or -1 if the panel fitter is not present or not in use
2144  */
2145 int intel_panel_fitter_pipe (struct drm_device *dev)
2146 {
2147         struct drm_i915_private *dev_priv = dev->dev_private;
2148         u32  pfit_control;
2149
2150         /* i830 doesn't have a panel fitter */
2151         if (IS_I830(dev))
2152                 return -1;
2153
2154         pfit_control = I915_READ(PFIT_CONTROL);
2155
2156         /* See if the panel fitter is in use */
2157         if ((pfit_control & PFIT_ENABLE) == 0)
2158                 return -1;
2159
2160         /* 965 can place panel fitter on either pipe */
2161         if (IS_I965G(dev))
2162                 return (pfit_control >> 29) & 0x3;
2163
2164         /* older chips can only use pipe 1 */
2165         return 1;
2166 }
2167
2168 struct fdi_m_n {
2169         u32        tu;
2170         u32        gmch_m;
2171         u32        gmch_n;
2172         u32        link_m;
2173         u32        link_n;
2174 };
2175
2176 static void
2177 fdi_reduce_ratio(u32 *num, u32 *den)
2178 {
2179         while (*num > 0xffffff || *den > 0xffffff) {
2180                 *num >>= 1;
2181                 *den >>= 1;
2182         }
2183 }
2184
2185 #define DATA_N 0x800000
2186 #define LINK_N 0x80000
2187
2188 static void
2189 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2190                      int link_clock, struct fdi_m_n *m_n)
2191 {
2192         u64 temp;
2193
2194         m_n->tu = 64; /* default size */
2195
2196         temp = (u64) DATA_N * pixel_clock;
2197         temp = div_u64(temp, link_clock);
2198         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2199         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2200         m_n->gmch_n = DATA_N;
2201         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2202
2203         temp = (u64) LINK_N * pixel_clock;
2204         m_n->link_m = div_u64(temp, link_clock);
2205         m_n->link_n = LINK_N;
2206         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2207 }
2208
2209
2210 struct intel_watermark_params {
2211         unsigned long fifo_size;
2212         unsigned long max_wm;
2213         unsigned long default_wm;
2214         unsigned long guard_size;
2215         unsigned long cacheline_size;
2216 };
2217
2218 /* Pineview has different values for various configs */
2219 static struct intel_watermark_params pineview_display_wm = {
2220         PINEVIEW_DISPLAY_FIFO,
2221         PINEVIEW_MAX_WM,
2222         PINEVIEW_DFT_WM,
2223         PINEVIEW_GUARD_WM,
2224         PINEVIEW_FIFO_LINE_SIZE
2225 };
2226 static struct intel_watermark_params pineview_display_hplloff_wm = {
2227         PINEVIEW_DISPLAY_FIFO,
2228         PINEVIEW_MAX_WM,
2229         PINEVIEW_DFT_HPLLOFF_WM,
2230         PINEVIEW_GUARD_WM,
2231         PINEVIEW_FIFO_LINE_SIZE
2232 };
2233 static struct intel_watermark_params pineview_cursor_wm = {
2234         PINEVIEW_CURSOR_FIFO,
2235         PINEVIEW_CURSOR_MAX_WM,
2236         PINEVIEW_CURSOR_DFT_WM,
2237         PINEVIEW_CURSOR_GUARD_WM,
2238         PINEVIEW_FIFO_LINE_SIZE,
2239 };
2240 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2241         PINEVIEW_CURSOR_FIFO,
2242         PINEVIEW_CURSOR_MAX_WM,
2243         PINEVIEW_CURSOR_DFT_WM,
2244         PINEVIEW_CURSOR_GUARD_WM,
2245         PINEVIEW_FIFO_LINE_SIZE
2246 };
2247 static struct intel_watermark_params g4x_wm_info = {
2248         G4X_FIFO_SIZE,
2249         G4X_MAX_WM,
2250         G4X_MAX_WM,
2251         2,
2252         G4X_FIFO_LINE_SIZE,
2253 };
2254 static struct intel_watermark_params i945_wm_info = {
2255         I945_FIFO_SIZE,
2256         I915_MAX_WM,
2257         1,
2258         2,
2259         I915_FIFO_LINE_SIZE
2260 };
2261 static struct intel_watermark_params i915_wm_info = {
2262         I915_FIFO_SIZE,
2263         I915_MAX_WM,
2264         1,
2265         2,
2266         I915_FIFO_LINE_SIZE
2267 };
2268 static struct intel_watermark_params i855_wm_info = {
2269         I855GM_FIFO_SIZE,
2270         I915_MAX_WM,
2271         1,
2272         2,
2273         I830_FIFO_LINE_SIZE
2274 };
2275 static struct intel_watermark_params i830_wm_info = {
2276         I830_FIFO_SIZE,
2277         I915_MAX_WM,
2278         1,
2279         2,
2280         I830_FIFO_LINE_SIZE
2281 };
2282
2283 /**
2284  * intel_calculate_wm - calculate watermark level
2285  * @clock_in_khz: pixel clock
2286  * @wm: chip FIFO params
2287  * @pixel_size: display pixel size
2288  * @latency_ns: memory latency for the platform
2289  *
2290  * Calculate the watermark level (the level at which the display plane will
2291  * start fetching from memory again).  Each chip has a different display
2292  * FIFO size and allocation, so the caller needs to figure that out and pass
2293  * in the correct intel_watermark_params structure.
2294  *
2295  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2296  * on the pixel size.  When it reaches the watermark level, it'll start
2297  * fetching FIFO line sized based chunks from memory until the FIFO fills
2298  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2299  * will occur, and a display engine hang could result.
2300  */
2301 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2302                                         struct intel_watermark_params *wm,
2303                                         int pixel_size,
2304                                         unsigned long latency_ns)
2305 {
2306         long entries_required, wm_size;
2307
2308         /*
2309          * Note: we need to make sure we don't overflow for various clock &
2310          * latency values.
2311          * clocks go from a few thousand to several hundred thousand.
2312          * latency is usually a few thousand
2313          */
2314         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2315                 1000;
2316         entries_required /= wm->cacheline_size;
2317
2318         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2319
2320         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2321
2322         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2323
2324         /* Don't promote wm_size to unsigned... */
2325         if (wm_size > (long)wm->max_wm)
2326                 wm_size = wm->max_wm;
2327         if (wm_size <= 0)
2328                 wm_size = wm->default_wm;
2329         return wm_size;
2330 }
2331
2332 struct cxsr_latency {
2333         int is_desktop;
2334         unsigned long fsb_freq;
2335         unsigned long mem_freq;
2336         unsigned long display_sr;
2337         unsigned long display_hpll_disable;
2338         unsigned long cursor_sr;
2339         unsigned long cursor_hpll_disable;
2340 };
2341
2342 static struct cxsr_latency cxsr_latency_table[] = {
2343         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2344         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2345         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2346
2347         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2348         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2349         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2350
2351         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2352         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2353         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2354
2355         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2356         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2357         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2358
2359         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2360         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2361         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2362
2363         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2364         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2365         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2366 };
2367
2368 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2369                                                    int mem)
2370 {
2371         int i;
2372         struct cxsr_latency *latency;
2373
2374         if (fsb == 0 || mem == 0)
2375                 return NULL;
2376
2377         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2378                 latency = &cxsr_latency_table[i];
2379                 if (is_desktop == latency->is_desktop &&
2380                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2381                         return latency;
2382         }
2383
2384         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2385
2386         return NULL;
2387 }
2388
2389 static void pineview_disable_cxsr(struct drm_device *dev)
2390 {
2391         struct drm_i915_private *dev_priv = dev->dev_private;
2392         u32 reg;
2393
2394         /* deactivate cxsr */
2395         reg = I915_READ(DSPFW3);
2396         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2397         I915_WRITE(DSPFW3, reg);
2398         DRM_INFO("Big FIFO is disabled\n");
2399 }
2400
2401 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2402                                  int pixel_size)
2403 {
2404         struct drm_i915_private *dev_priv = dev->dev_private;
2405         u32 reg;
2406         unsigned long wm;
2407         struct cxsr_latency *latency;
2408
2409         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2410                 dev_priv->mem_freq);
2411         if (!latency) {
2412                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2413                 pineview_disable_cxsr(dev);
2414                 return;
2415         }
2416
2417         /* Display SR */
2418         wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2419                                 latency->display_sr);
2420         reg = I915_READ(DSPFW1);
2421         reg &= 0x7fffff;
2422         reg |= wm << 23;
2423         I915_WRITE(DSPFW1, reg);
2424         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2425
2426         /* cursor SR */
2427         wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2428                                 latency->cursor_sr);
2429         reg = I915_READ(DSPFW3);
2430         reg &= ~(0x3f << 24);
2431         reg |= (wm & 0x3f) << 24;
2432         I915_WRITE(DSPFW3, reg);
2433
2434         /* Display HPLL off SR */
2435         wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2436                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2437         reg = I915_READ(DSPFW3);
2438         reg &= 0xfffffe00;
2439         reg |= wm & 0x1ff;
2440         I915_WRITE(DSPFW3, reg);
2441
2442         /* cursor HPLL off SR */
2443         wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2444                                 latency->cursor_hpll_disable);
2445         reg = I915_READ(DSPFW3);
2446         reg &= ~(0x3f << 16);
2447         reg |= (wm & 0x3f) << 16;
2448         I915_WRITE(DSPFW3, reg);
2449         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2450
2451         /* activate cxsr */
2452         reg = I915_READ(DSPFW3);
2453         reg |= PINEVIEW_SELF_REFRESH_EN;
2454         I915_WRITE(DSPFW3, reg);
2455
2456         DRM_INFO("Big FIFO is enabled\n");
2457
2458         return;
2459 }
2460
2461 /*
2462  * Latency for FIFO fetches is dependent on several factors:
2463  *   - memory configuration (speed, channels)
2464  *   - chipset
2465  *   - current MCH state
2466  * It can be fairly high in some situations, so here we assume a fairly
2467  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2468  * set this value too high, the FIFO will fetch frequently to stay full)
2469  * and power consumption (set it too low to save power and we might see
2470  * FIFO underruns and display "flicker").
2471  *
2472  * A value of 5us seems to be a good balance; safe for very low end
2473  * platforms but not overly aggressive on lower latency configs.
2474  */
2475 static const int latency_ns = 5000;
2476
2477 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2478 {
2479         struct drm_i915_private *dev_priv = dev->dev_private;
2480         uint32_t dsparb = I915_READ(DSPARB);
2481         int size;
2482
2483         if (plane == 0)
2484                 size = dsparb & 0x7f;
2485         else
2486                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2487                         (dsparb & 0x7f);
2488
2489         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2490                         plane ? "B" : "A", size);
2491
2492         return size;
2493 }
2494
2495 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2496 {
2497         struct drm_i915_private *dev_priv = dev->dev_private;
2498         uint32_t dsparb = I915_READ(DSPARB);
2499         int size;
2500
2501         if (plane == 0)
2502                 size = dsparb & 0x1ff;
2503         else
2504                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2505                         (dsparb & 0x1ff);
2506         size >>= 1; /* Convert to cachelines */
2507
2508         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2509                         plane ? "B" : "A", size);
2510
2511         return size;
2512 }
2513
2514 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2515 {
2516         struct drm_i915_private *dev_priv = dev->dev_private;
2517         uint32_t dsparb = I915_READ(DSPARB);
2518         int size;
2519
2520         size = dsparb & 0x7f;
2521         size >>= 2; /* Convert to cachelines */
2522
2523         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2524                         plane ? "B" : "A",
2525                   size);
2526
2527         return size;
2528 }
2529
2530 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2531 {
2532         struct drm_i915_private *dev_priv = dev->dev_private;
2533         uint32_t dsparb = I915_READ(DSPARB);
2534         int size;
2535
2536         size = dsparb & 0x7f;
2537         size >>= 1; /* Convert to cachelines */
2538
2539         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2540                         plane ? "B" : "A", size);
2541
2542         return size;
2543 }
2544
2545 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2546                           int planeb_clock, int sr_hdisplay, int pixel_size)
2547 {
2548         struct drm_i915_private *dev_priv = dev->dev_private;
2549         int total_size, cacheline_size;
2550         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2551         struct intel_watermark_params planea_params, planeb_params;
2552         unsigned long line_time_us;
2553         int sr_clock, sr_entries = 0, entries_required;
2554
2555         /* Create copies of the base settings for each pipe */
2556         planea_params = planeb_params = g4x_wm_info;
2557
2558         /* Grab a couple of global values before we overwrite them */
2559         total_size = planea_params.fifo_size;
2560         cacheline_size = planea_params.cacheline_size;
2561
2562         /*
2563          * Note: we need to make sure we don't overflow for various clock &
2564          * latency values.
2565          * clocks go from a few thousand to several hundred thousand.
2566          * latency is usually a few thousand
2567          */
2568         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2569                 1000;
2570         entries_required /= G4X_FIFO_LINE_SIZE;
2571         planea_wm = entries_required + planea_params.guard_size;
2572
2573         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2574                 1000;
2575         entries_required /= G4X_FIFO_LINE_SIZE;
2576         planeb_wm = entries_required + planeb_params.guard_size;
2577
2578         cursora_wm = cursorb_wm = 16;
2579         cursor_sr = 32;
2580
2581         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2582
2583         /* Calc sr entries for one plane configs */
2584         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2585                 /* self-refresh has much higher latency */
2586                 static const int sr_latency_ns = 12000;
2587
2588                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2589                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2590
2591                 /* Use ns/us then divide to preserve precision */
2592                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2593                               pixel_size * sr_hdisplay) / 1000;
2594                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2595                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2596                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2597         }
2598
2599         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2600                   planea_wm, planeb_wm, sr_entries);
2601
2602         planea_wm &= 0x3f;
2603         planeb_wm &= 0x3f;
2604
2605         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2606                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2607                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2608         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2609                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2610         /* HPLL off in SR has some issues on G4x... disable it */
2611         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2612                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2613 }
2614
2615 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2616                            int planeb_clock, int sr_hdisplay, int pixel_size)
2617 {
2618         struct drm_i915_private *dev_priv = dev->dev_private;
2619         unsigned long line_time_us;
2620         int sr_clock, sr_entries, srwm = 1;
2621
2622         /* Calc sr entries for one plane configs */
2623         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2624                 /* self-refresh has much higher latency */
2625                 static const int sr_latency_ns = 12000;
2626
2627                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2628                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2629
2630                 /* Use ns/us then divide to preserve precision */
2631                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2632                               pixel_size * sr_hdisplay) / 1000;
2633                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2634                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2635                 srwm = I945_FIFO_SIZE - sr_entries;
2636                 if (srwm < 0)
2637                         srwm = 1;
2638                 srwm &= 0x3f;
2639                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2640         }
2641
2642         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2643                       srwm);
2644
2645         /* 965 has limitations... */
2646         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2647                    (8 << 0));
2648         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2649 }
2650
2651 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2652                            int planeb_clock, int sr_hdisplay, int pixel_size)
2653 {
2654         struct drm_i915_private *dev_priv = dev->dev_private;
2655         uint32_t fwater_lo;
2656         uint32_t fwater_hi;
2657         int total_size, cacheline_size, cwm, srwm = 1;
2658         int planea_wm, planeb_wm;
2659         struct intel_watermark_params planea_params, planeb_params;
2660         unsigned long line_time_us;
2661         int sr_clock, sr_entries = 0;
2662
2663         /* Create copies of the base settings for each pipe */
2664         if (IS_I965GM(dev) || IS_I945GM(dev))
2665                 planea_params = planeb_params = i945_wm_info;
2666         else if (IS_I9XX(dev))
2667                 planea_params = planeb_params = i915_wm_info;
2668         else
2669                 planea_params = planeb_params = i855_wm_info;
2670
2671         /* Grab a couple of global values before we overwrite them */
2672         total_size = planea_params.fifo_size;
2673         cacheline_size = planea_params.cacheline_size;
2674
2675         /* Update per-plane FIFO sizes */
2676         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2677         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2678
2679         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2680                                        pixel_size, latency_ns);
2681         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2682                                        pixel_size, latency_ns);
2683         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2684
2685         /*
2686          * Overlay gets an aggressive default since video jitter is bad.
2687          */
2688         cwm = 2;
2689
2690         /* Calc sr entries for one plane configs */
2691         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2692             (!planea_clock || !planeb_clock)) {
2693                 /* self-refresh has much higher latency */
2694                 static const int sr_latency_ns = 6000;
2695
2696                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2697                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2698
2699                 /* Use ns/us then divide to preserve precision */
2700                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2701                               pixel_size * sr_hdisplay) / 1000;
2702                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2703                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2704                 srwm = total_size - sr_entries;
2705                 if (srwm < 0)
2706                         srwm = 1;
2707                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2708         }
2709
2710         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2711                   planea_wm, planeb_wm, cwm, srwm);
2712
2713         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2714         fwater_hi = (cwm & 0x1f);
2715
2716         /* Set request length to 8 cachelines per fetch */
2717         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2718         fwater_hi = fwater_hi | (1 << 8);
2719
2720         I915_WRITE(FW_BLC, fwater_lo);
2721         I915_WRITE(FW_BLC2, fwater_hi);
2722 }
2723
2724 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2725                            int unused2, int pixel_size)
2726 {
2727         struct drm_i915_private *dev_priv = dev->dev_private;
2728         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2729         int planea_wm;
2730
2731         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2732
2733         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2734                                        pixel_size, latency_ns);
2735         fwater_lo |= (3<<8) | planea_wm;
2736
2737         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2738
2739         I915_WRITE(FW_BLC, fwater_lo);
2740 }
2741
2742 /**
2743  * intel_update_watermarks - update FIFO watermark values based on current modes
2744  *
2745  * Calculate watermark values for the various WM regs based on current mode
2746  * and plane configuration.
2747  *
2748  * There are several cases to deal with here:
2749  *   - normal (i.e. non-self-refresh)
2750  *   - self-refresh (SR) mode
2751  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2752  *   - lines are small relative to FIFO size (buffer can hold more than 2
2753  *     lines), so need to account for TLB latency
2754  *
2755  *   The normal calculation is:
2756  *     watermark = dotclock * bytes per pixel * latency
2757  *   where latency is platform & configuration dependent (we assume pessimal
2758  *   values here).
2759  *
2760  *   The SR calculation is:
2761  *     watermark = (trunc(latency/line time)+1) * surface width *
2762  *       bytes per pixel
2763  *   where
2764  *     line time = htotal / dotclock
2765  *   and latency is assumed to be high, as above.
2766  *
2767  * The final value programmed to the register should always be rounded up,
2768  * and include an extra 2 entries to account for clock crossings.
2769  *
2770  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2771  * to set the non-SR watermarks to 8.
2772   */
2773 static void intel_update_watermarks(struct drm_device *dev)
2774 {
2775         struct drm_i915_private *dev_priv = dev->dev_private;
2776         struct drm_crtc *crtc;
2777         struct intel_crtc *intel_crtc;
2778         int sr_hdisplay = 0;
2779         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2780         int enabled = 0, pixel_size = 0;
2781
2782         if (!dev_priv->display.update_wm)
2783                 return;
2784
2785         /* Get the clock config from both planes */
2786         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2787                 intel_crtc = to_intel_crtc(crtc);
2788                 if (crtc->enabled) {
2789                         enabled++;
2790                         if (intel_crtc->plane == 0) {
2791                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2792                                           intel_crtc->pipe, crtc->mode.clock);
2793                                 planea_clock = crtc->mode.clock;
2794                         } else {
2795                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2796                                           intel_crtc->pipe, crtc->mode.clock);
2797                                 planeb_clock = crtc->mode.clock;
2798                         }
2799                         sr_hdisplay = crtc->mode.hdisplay;
2800                         sr_clock = crtc->mode.clock;
2801                         if (crtc->fb)
2802                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2803                         else
2804                                 pixel_size = 4; /* by default */
2805                 }
2806         }
2807
2808         if (enabled <= 0)
2809                 return;
2810
2811         /* Single plane configs can enable self refresh */
2812         if (enabled == 1 && IS_PINEVIEW(dev))
2813                 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2814         else if (IS_PINEVIEW(dev))
2815                 pineview_disable_cxsr(dev);
2816
2817         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2818                                     sr_hdisplay, pixel_size);
2819 }
2820
2821 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2822                                struct drm_display_mode *mode,
2823                                struct drm_display_mode *adjusted_mode,
2824                                int x, int y,
2825                                struct drm_framebuffer *old_fb)
2826 {
2827         struct drm_device *dev = crtc->dev;
2828         struct drm_i915_private *dev_priv = dev->dev_private;
2829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2830         int pipe = intel_crtc->pipe;
2831         int plane = intel_crtc->plane;
2832         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2833         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2834         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2835         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2836         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2837         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2838         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2839         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2840         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2841         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2842         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2843         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2844         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2845         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2846         int refclk, num_outputs = 0;
2847         intel_clock_t clock, reduced_clock;
2848         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2849         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2850         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2851         bool is_edp = false;
2852         struct drm_mode_config *mode_config = &dev->mode_config;
2853         struct drm_connector *connector;
2854         const intel_limit_t *limit;
2855         int ret;
2856         struct fdi_m_n m_n = {0};
2857         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2858         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2859         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2860         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2861         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2862         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2863         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2864         int lvds_reg = LVDS;
2865         u32 temp;
2866         int sdvo_pixel_multiply;
2867         int target_clock;
2868
2869         drm_vblank_pre_modeset(dev, pipe);
2870
2871         list_for_each_entry(connector, &mode_config->connector_list, head) {
2872                 struct intel_output *intel_output = to_intel_output(connector);
2873
2874                 if (!connector->encoder || connector->encoder->crtc != crtc)
2875                         continue;
2876
2877                 switch (intel_output->type) {
2878                 case INTEL_OUTPUT_LVDS:
2879                         is_lvds = true;
2880                         break;
2881                 case INTEL_OUTPUT_SDVO:
2882                 case INTEL_OUTPUT_HDMI:
2883                         is_sdvo = true;
2884                         if (intel_output->needs_tv_clock)
2885                                 is_tv = true;
2886                         break;
2887                 case INTEL_OUTPUT_DVO:
2888                         is_dvo = true;
2889                         break;
2890                 case INTEL_OUTPUT_TVOUT:
2891                         is_tv = true;
2892                         break;
2893                 case INTEL_OUTPUT_ANALOG:
2894                         is_crt = true;
2895                         break;
2896                 case INTEL_OUTPUT_DISPLAYPORT:
2897                         is_dp = true;
2898                         break;
2899                 case INTEL_OUTPUT_EDP:
2900                         is_edp = true;
2901                         break;
2902                 }
2903
2904                 num_outputs++;
2905         }
2906
2907         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2908                 refclk = dev_priv->lvds_ssc_freq * 1000;
2909                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2910                                         refclk / 1000);
2911         } else if (IS_I9XX(dev)) {
2912                 refclk = 96000;
2913                 if (IS_IRONLAKE(dev))
2914                         refclk = 120000; /* 120Mhz refclk */
2915         } else {
2916                 refclk = 48000;
2917         }
2918
2919
2920         /*
2921          * Returns a set of divisors for the desired target clock with the given
2922          * refclk, or FALSE.  The returned values represent the clock equation:
2923          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2924          */
2925         limit = intel_limit(crtc);
2926         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2927         if (!ok) {
2928                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2929                 drm_vblank_post_modeset(dev, pipe);
2930                 return -EINVAL;
2931         }
2932
2933         if (is_lvds && limit->find_reduced_pll &&
2934                         dev_priv->lvds_downclock_avail) {
2935                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2936                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2937                                                             dev_priv->lvds_downclock,
2938                                                             refclk,
2939                                                             &reduced_clock);
2940                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2941                         /*
2942                          * If the different P is found, it means that we can't
2943                          * switch the display clock by using the FP0/FP1.
2944                          * In such case we will disable the LVDS downclock
2945                          * feature.
2946                          */
2947                         DRM_DEBUG_KMS("Different P is found for "
2948                                                 "LVDS clock/downclock\n");
2949                         has_reduced_clock = 0;
2950                 }
2951         }
2952         /* SDVO TV has fixed PLL values depend on its clock range,
2953            this mirrors vbios setting. */
2954         if (is_sdvo && is_tv) {
2955                 if (adjusted_mode->clock >= 100000
2956                                 && adjusted_mode->clock < 140500) {
2957                         clock.p1 = 2;
2958                         clock.p2 = 10;
2959                         clock.n = 3;
2960                         clock.m1 = 16;
2961                         clock.m2 = 8;
2962                 } else if (adjusted_mode->clock >= 140500
2963                                 && adjusted_mode->clock <= 200000) {
2964                         clock.p1 = 1;
2965                         clock.p2 = 10;
2966                         clock.n = 6;
2967                         clock.m1 = 12;
2968                         clock.m2 = 8;
2969                 }
2970         }
2971
2972         /* FDI link */
2973         if (IS_IRONLAKE(dev)) {
2974                 int lane, link_bw, bpp;
2975                 /* eDP doesn't require FDI link, so just set DP M/N
2976                    according to current link config */
2977                 if (is_edp) {
2978                         struct drm_connector *edp;
2979                         target_clock = mode->clock;
2980                         edp = intel_pipe_get_output(crtc);
2981                         intel_edp_link_config(to_intel_output(edp),
2982                                         &lane, &link_bw);
2983                 } else {
2984                         /* DP over FDI requires target mode clock
2985                            instead of link clock */
2986                         if (is_dp)
2987                                 target_clock = mode->clock;
2988                         else
2989                                 target_clock = adjusted_mode->clock;
2990                         lane = 4;
2991                         link_bw = 270000;
2992                 }
2993
2994                 /* determine panel color depth */
2995                 temp = I915_READ(pipeconf_reg);
2996
2997                 switch (temp & PIPE_BPC_MASK) {
2998                 case PIPE_8BPC:
2999                         bpp = 24;
3000                         break;
3001                 case PIPE_10BPC:
3002                         bpp = 30;
3003                         break;
3004                 case PIPE_6BPC:
3005                         bpp = 18;
3006                         break;
3007                 case PIPE_12BPC:
3008                         bpp = 36;
3009                         break;
3010                 default:
3011                         DRM_ERROR("unknown pipe bpc value\n");
3012                         bpp = 24;
3013                 }
3014
3015                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3016         }
3017
3018         /* Ironlake: try to setup display ref clock before DPLL
3019          * enabling. This is only under driver's control after
3020          * PCH B stepping, previous chipset stepping should be
3021          * ignoring this setting.
3022          */
3023         if (IS_IRONLAKE(dev)) {
3024                 temp = I915_READ(PCH_DREF_CONTROL);
3025                 /* Always enable nonspread source */
3026                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3027                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3028                 I915_WRITE(PCH_DREF_CONTROL, temp);
3029                 POSTING_READ(PCH_DREF_CONTROL);
3030
3031                 temp &= ~DREF_SSC_SOURCE_MASK;
3032                 temp |= DREF_SSC_SOURCE_ENABLE;
3033                 I915_WRITE(PCH_DREF_CONTROL, temp);
3034                 POSTING_READ(PCH_DREF_CONTROL);
3035
3036                 udelay(200);
3037
3038                 if (is_edp) {
3039                         if (dev_priv->lvds_use_ssc) {
3040                                 temp |= DREF_SSC1_ENABLE;
3041                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3042                                 POSTING_READ(PCH_DREF_CONTROL);
3043
3044                                 udelay(200);
3045
3046                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3047                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3048                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3049                                 POSTING_READ(PCH_DREF_CONTROL);
3050                         } else {
3051                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3052                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3053                                 POSTING_READ(PCH_DREF_CONTROL);
3054                         }
3055                 }
3056         }
3057
3058         if (IS_PINEVIEW(dev)) {
3059                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3060                 if (has_reduced_clock)
3061                         fp2 = (1 << reduced_clock.n) << 16 |
3062                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3063         } else {
3064                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3065                 if (has_reduced_clock)
3066                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3067                                 reduced_clock.m2;
3068         }
3069
3070         if (!IS_IRONLAKE(dev))
3071                 dpll = DPLL_VGA_MODE_DIS;
3072
3073         if (IS_I9XX(dev)) {
3074                 if (is_lvds)
3075                         dpll |= DPLLB_MODE_LVDS;
3076                 else
3077                         dpll |= DPLLB_MODE_DAC_SERIAL;
3078                 if (is_sdvo) {
3079                         dpll |= DPLL_DVO_HIGH_SPEED;
3080                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3081                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3082                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3083                         else if (IS_IRONLAKE(dev))
3084                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3085                 }
3086                 if (is_dp)
3087                         dpll |= DPLL_DVO_HIGH_SPEED;
3088
3089                 /* compute bitmask from p1 value */
3090                 if (IS_PINEVIEW(dev))
3091                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3092                 else {
3093                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3094                         /* also FPA1 */
3095                         if (IS_IRONLAKE(dev))
3096                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3097                         if (IS_G4X(dev) && has_reduced_clock)
3098                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3099                 }
3100                 switch (clock.p2) {
3101                 case 5:
3102                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3103                         break;
3104                 case 7:
3105                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3106                         break;
3107                 case 10:
3108                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3109                         break;
3110                 case 14:
3111                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3112                         break;
3113                 }
3114                 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
3115                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3116         } else {
3117                 if (is_lvds) {
3118                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3119                 } else {
3120                         if (clock.p1 == 2)
3121                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3122                         else
3123                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3124                         if (clock.p2 == 4)
3125                                 dpll |= PLL_P2_DIVIDE_BY_4;
3126                 }
3127         }
3128
3129         if (is_sdvo && is_tv)
3130                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3131         else if (is_tv)
3132                 /* XXX: just matching BIOS for now */
3133                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3134                 dpll |= 3;
3135         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3136                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3137         else
3138                 dpll |= PLL_REF_INPUT_DREFCLK;
3139
3140         /* setup pipeconf */
3141         pipeconf = I915_READ(pipeconf_reg);
3142
3143         /* Set up the display plane register */
3144         dspcntr = DISPPLANE_GAMMA_ENABLE;
3145
3146         /* Ironlake's plane is forced to pipe, bit 24 is to
3147            enable color space conversion */
3148         if (!IS_IRONLAKE(dev)) {
3149                 if (pipe == 0)
3150                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3151                 else
3152                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3153         }
3154
3155         if (pipe == 0 && !IS_I965G(dev)) {
3156                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3157                  * core speed.
3158                  *
3159                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3160                  * pipe == 0 check?
3161                  */
3162                 if (mode->clock >
3163                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3164                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3165                 else
3166                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3167         }
3168
3169         dspcntr |= DISPLAY_PLANE_ENABLE;
3170         pipeconf |= PIPEACONF_ENABLE;
3171         dpll |= DPLL_VCO_ENABLE;
3172
3173
3174         /* Disable the panel fitter if it was on our pipe */
3175         if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
3176                 I915_WRITE(PFIT_CONTROL, 0);
3177
3178         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3179         drm_mode_debug_printmodeline(mode);
3180
3181         /* assign to Ironlake registers */
3182         if (IS_IRONLAKE(dev)) {
3183                 fp_reg = pch_fp_reg;
3184                 dpll_reg = pch_dpll_reg;
3185         }
3186
3187         if (is_edp) {
3188                 ironlake_disable_pll_edp(crtc);
3189         } else if ((dpll & DPLL_VCO_ENABLE)) {
3190                 I915_WRITE(fp_reg, fp);
3191                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3192                 I915_READ(dpll_reg);
3193                 udelay(150);
3194         }
3195
3196         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3197          * This is an exception to the general rule that mode_set doesn't turn
3198          * things on.
3199          */
3200         if (is_lvds) {
3201                 u32 lvds;
3202
3203                 if (IS_IRONLAKE(dev))
3204                         lvds_reg = PCH_LVDS;
3205
3206                 lvds = I915_READ(lvds_reg);
3207                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3208                 /* set the corresponsding LVDS_BORDER bit */
3209                 lvds |= dev_priv->lvds_border_bits;
3210                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3211                  * set the DPLLs for dual-channel mode or not.
3212                  */
3213                 if (clock.p2 == 7)
3214                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3215                 else
3216                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3217
3218                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3219                  * appropriately here, but we need to look more thoroughly into how
3220                  * panels behave in the two modes.
3221                  */
3222                 /* set the dithering flag */
3223                 if (IS_I965G(dev)) {
3224                         if (dev_priv->lvds_dither) {
3225                                 if (IS_IRONLAKE(dev))
3226                                         pipeconf |= PIPE_ENABLE_DITHER;
3227                                 else
3228                                         lvds |= LVDS_ENABLE_DITHER;
3229                         } else {
3230                                 if (IS_IRONLAKE(dev))
3231                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3232                                 else
3233                                         lvds &= ~LVDS_ENABLE_DITHER;
3234                         }
3235                 }
3236                 I915_WRITE(lvds_reg, lvds);
3237                 I915_READ(lvds_reg);
3238         }
3239         if (is_dp)
3240                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3241
3242         if (!is_edp) {
3243                 I915_WRITE(fp_reg, fp);
3244                 I915_WRITE(dpll_reg, dpll);
3245                 I915_READ(dpll_reg);
3246                 /* Wait for the clocks to stabilize. */
3247                 udelay(150);
3248
3249                 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
3250                         if (is_sdvo) {
3251                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3252                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3253                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3254                         } else
3255                                 I915_WRITE(dpll_md_reg, 0);
3256                 } else {
3257                         /* write it again -- the BIOS does, after all */
3258                         I915_WRITE(dpll_reg, dpll);
3259                 }
3260                 I915_READ(dpll_reg);
3261                 /* Wait for the clocks to stabilize. */
3262                 udelay(150);
3263         }
3264
3265         if (is_lvds && has_reduced_clock && i915_powersave) {
3266                 I915_WRITE(fp_reg + 4, fp2);
3267                 intel_crtc->lowfreq_avail = true;
3268                 if (HAS_PIPE_CXSR(dev)) {
3269                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3270                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3271                 }
3272         } else {
3273                 I915_WRITE(fp_reg + 4, fp);
3274                 intel_crtc->lowfreq_avail = false;
3275                 if (HAS_PIPE_CXSR(dev)) {
3276                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3277                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3278                 }
3279         }
3280
3281         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3282                    ((adjusted_mode->crtc_htotal - 1) << 16));
3283         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3284                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3285         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3286                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3287         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3288                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3289         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3290                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3291         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3292                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3293         /* pipesrc and dspsize control the size that is scaled from, which should
3294          * always be the user's requested size.
3295          */
3296         if (!IS_IRONLAKE(dev)) {
3297                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3298                                 (mode->hdisplay - 1));
3299                 I915_WRITE(dsppos_reg, 0);
3300         }
3301         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3302
3303         if (IS_IRONLAKE(dev)) {
3304                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3305                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3306                 I915_WRITE(link_m1_reg, m_n.link_m);
3307                 I915_WRITE(link_n1_reg, m_n.link_n);
3308
3309                 if (is_edp) {
3310                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3311                 } else {
3312                         /* enable FDI RX PLL too */
3313                         temp = I915_READ(fdi_rx_reg);
3314                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3315                         udelay(200);
3316                 }
3317         }
3318
3319         I915_WRITE(pipeconf_reg, pipeconf);
3320         I915_READ(pipeconf_reg);
3321
3322         intel_wait_for_vblank(dev);
3323
3324         if (IS_IRONLAKE(dev)) {
3325                 /* enable address swizzle for tiling buffer */
3326                 temp = I915_READ(DISP_ARB_CTL);
3327                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3328         }
3329
3330         I915_WRITE(dspcntr_reg, dspcntr);
3331
3332         /* Flush the plane changes */
3333         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3334
3335         if ((IS_I965G(dev) || plane == 0))
3336                 intel_update_fbc(crtc, &crtc->mode);
3337
3338         intel_update_watermarks(dev);
3339
3340         drm_vblank_post_modeset(dev, pipe);
3341
3342         return ret;
3343 }
3344
3345 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3346 void intel_crtc_load_lut(struct drm_crtc *crtc)
3347 {
3348         struct drm_device *dev = crtc->dev;
3349         struct drm_i915_private *dev_priv = dev->dev_private;
3350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3352         int i;
3353
3354         /* The clocks have to be on to load the palette. */
3355         if (!crtc->enabled)
3356                 return;
3357
3358         /* use legacy palette for Ironlake */
3359         if (IS_IRONLAKE(dev))
3360                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3361                                                    LGC_PALETTE_B;
3362
3363         for (i = 0; i < 256; i++) {
3364                 I915_WRITE(palreg + 4 * i,
3365                            (intel_crtc->lut_r[i] << 16) |
3366                            (intel_crtc->lut_g[i] << 8) |
3367                            intel_crtc->lut_b[i]);
3368         }
3369 }
3370
3371 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3372                                  struct drm_file *file_priv,
3373                                  uint32_t handle,
3374                                  uint32_t width, uint32_t height)
3375 {
3376         struct drm_device *dev = crtc->dev;
3377         struct drm_i915_private *dev_priv = dev->dev_private;
3378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3379         struct drm_gem_object *bo;
3380         struct drm_i915_gem_object *obj_priv;
3381         int pipe = intel_crtc->pipe;
3382         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3383         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3384         uint32_t temp = I915_READ(control);
3385         size_t addr;
3386         int ret;
3387
3388         DRM_DEBUG_KMS("\n");
3389
3390         /* if we want to turn off the cursor ignore width and height */
3391         if (!handle) {
3392                 DRM_DEBUG_KMS("cursor off\n");
3393                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3394                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3395                         temp |= CURSOR_MODE_DISABLE;
3396                 } else {
3397                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3398                 }
3399                 addr = 0;
3400                 bo = NULL;
3401                 mutex_lock(&dev->struct_mutex);
3402                 goto finish;
3403         }
3404
3405         /* Currently we only support 64x64 cursors */
3406         if (width != 64 || height != 64) {
3407                 DRM_ERROR("we currently only support 64x64 cursors\n");
3408                 return -EINVAL;
3409         }
3410
3411         bo = drm_gem_object_lookup(dev, file_priv, handle);
3412         if (!bo)
3413                 return -ENOENT;
3414
3415         obj_priv = bo->driver_private;
3416
3417         if (bo->size < width * height * 4) {
3418                 DRM_ERROR("buffer is to small\n");
3419                 ret = -ENOMEM;
3420                 goto fail;
3421         }
3422
3423         /* we only need to pin inside GTT if cursor is non-phy */
3424         mutex_lock(&dev->struct_mutex);
3425         if (!dev_priv->info->cursor_needs_physical) {
3426                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3427                 if (ret) {
3428                         DRM_ERROR("failed to pin cursor bo\n");
3429                         goto fail_locked;
3430                 }
3431                 addr = obj_priv->gtt_offset;
3432         } else {
3433                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3434                 if (ret) {
3435                         DRM_ERROR("failed to attach phys object\n");
3436                         goto fail_locked;
3437                 }
3438                 addr = obj_priv->phys_obj->handle->busaddr;
3439         }
3440
3441         if (!IS_I9XX(dev))
3442                 I915_WRITE(CURSIZE, (height << 12) | width);
3443
3444         /* Hooray for CUR*CNTR differences */
3445         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3446                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3447                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3448                 temp |= (pipe << 28); /* Connect to correct pipe */
3449         } else {
3450                 temp &= ~(CURSOR_FORMAT_MASK);
3451                 temp |= CURSOR_ENABLE;
3452                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3453         }
3454
3455  finish:
3456         I915_WRITE(control, temp);
3457         I915_WRITE(base, addr);
3458
3459         if (intel_crtc->cursor_bo) {
3460                 if (dev_priv->info->cursor_needs_physical) {
3461                         if (intel_crtc->cursor_bo != bo)
3462                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3463                 } else
3464                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3465                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3466         }
3467
3468         mutex_unlock(&dev->struct_mutex);
3469
3470         intel_crtc->cursor_addr = addr;
3471         intel_crtc->cursor_bo = bo;
3472
3473         return 0;
3474 fail:
3475         mutex_lock(&dev->struct_mutex);
3476 fail_locked:
3477         drm_gem_object_unreference(bo);
3478         mutex_unlock(&dev->struct_mutex);
3479         return ret;
3480 }
3481
3482 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3483 {
3484         struct drm_device *dev = crtc->dev;
3485         struct drm_i915_private *dev_priv = dev->dev_private;
3486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3487         struct intel_framebuffer *intel_fb;
3488         int pipe = intel_crtc->pipe;
3489         uint32_t temp = 0;
3490         uint32_t adder;
3491
3492         if (crtc->fb) {
3493                 intel_fb = to_intel_framebuffer(crtc->fb);
3494                 intel_mark_busy(dev, intel_fb->obj);
3495         }
3496
3497         if (x < 0) {
3498                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3499                 x = -x;
3500         }
3501         if (y < 0) {
3502                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3503                 y = -y;
3504         }
3505
3506         temp |= x << CURSOR_X_SHIFT;
3507         temp |= y << CURSOR_Y_SHIFT;
3508
3509         adder = intel_crtc->cursor_addr;
3510         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3511         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3512
3513         return 0;
3514 }
3515
3516 /** Sets the color ramps on behalf of RandR */
3517 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3518                                  u16 blue, int regno)
3519 {
3520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3521
3522         intel_crtc->lut_r[regno] = red >> 8;
3523         intel_crtc->lut_g[regno] = green >> 8;
3524         intel_crtc->lut_b[regno] = blue >> 8;
3525 }
3526
3527 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3528                              u16 *blue, int regno)
3529 {
3530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3531
3532         *red = intel_crtc->lut_r[regno] << 8;
3533         *green = intel_crtc->lut_g[regno] << 8;
3534         *blue = intel_crtc->lut_b[regno] << 8;
3535 }
3536
3537 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3538                                  u16 *blue, uint32_t size)
3539 {
3540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3541         int i;
3542
3543         if (size != 256)
3544                 return;
3545
3546         for (i = 0; i < 256; i++) {
3547                 intel_crtc->lut_r[i] = red[i] >> 8;
3548                 intel_crtc->lut_g[i] = green[i] >> 8;
3549                 intel_crtc->lut_b[i] = blue[i] >> 8;
3550         }
3551
3552         intel_crtc_load_lut(crtc);
3553 }
3554
3555 /**
3556  * Get a pipe with a simple mode set on it for doing load-based monitor
3557  * detection.
3558  *
3559  * It will be up to the load-detect code to adjust the pipe as appropriate for
3560  * its requirements.  The pipe will be connected to no other outputs.
3561  *
3562  * Currently this code will only succeed if there is a pipe with no outputs
3563  * configured for it.  In the future, it could choose to temporarily disable
3564  * some outputs to free up a pipe for its use.
3565  *
3566  * \return crtc, or NULL if no pipes are available.
3567  */
3568
3569 /* VESA 640x480x72Hz mode to set on the pipe */
3570 static struct drm_display_mode load_detect_mode = {
3571         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3572                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3573 };
3574
3575 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3576                                             struct drm_display_mode *mode,
3577                                             int *dpms_mode)
3578 {
3579         struct intel_crtc *intel_crtc;
3580         struct drm_crtc *possible_crtc;
3581         struct drm_crtc *supported_crtc =NULL;
3582         struct drm_encoder *encoder = &intel_output->enc;
3583         struct drm_crtc *crtc = NULL;
3584         struct drm_device *dev = encoder->dev;
3585         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3586         struct drm_crtc_helper_funcs *crtc_funcs;
3587         int i = -1;
3588
3589         /*
3590          * Algorithm gets a little messy:
3591          *   - if the connector already has an assigned crtc, use it (but make
3592          *     sure it's on first)
3593          *   - try to find the first unused crtc that can drive this connector,
3594          *     and use that if we find one
3595          *   - if there are no unused crtcs available, try to use the first
3596          *     one we found that supports the connector
3597          */
3598
3599         /* See if we already have a CRTC for this connector */
3600         if (encoder->crtc) {
3601                 crtc = encoder->crtc;
3602                 /* Make sure the crtc and connector are running */
3603                 intel_crtc = to_intel_crtc(crtc);
3604                 *dpms_mode = intel_crtc->dpms_mode;
3605                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3606                         crtc_funcs = crtc->helper_private;
3607                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3608                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3609                 }
3610                 return crtc;
3611         }
3612
3613         /* Find an unused one (if possible) */
3614         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3615                 i++;
3616                 if (!(encoder->possible_crtcs & (1 << i)))
3617                         continue;
3618                 if (!possible_crtc->enabled) {
3619                         crtc = possible_crtc;
3620                         break;
3621                 }
3622                 if (!supported_crtc)
3623                         supported_crtc = possible_crtc;
3624         }
3625
3626         /*
3627          * If we didn't find an unused CRTC, don't use any.
3628          */
3629         if (!crtc) {
3630                 return NULL;
3631         }
3632
3633         encoder->crtc = crtc;
3634         intel_output->base.encoder = encoder;
3635         intel_output->load_detect_temp = true;
3636
3637         intel_crtc = to_intel_crtc(crtc);
3638         *dpms_mode = intel_crtc->dpms_mode;
3639
3640         if (!crtc->enabled) {
3641                 if (!mode)
3642                         mode = &load_detect_mode;
3643                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3644         } else {
3645                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3646                         crtc_funcs = crtc->helper_private;
3647                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3648                 }
3649
3650                 /* Add this connector to the crtc */
3651                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3652                 encoder_funcs->commit(encoder);
3653         }
3654         /* let the connector get through one full cycle before testing */
3655         intel_wait_for_vblank(dev);
3656
3657         return crtc;
3658 }
3659
3660 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3661 {
3662         struct drm_encoder *encoder = &intel_output->enc;
3663         struct drm_device *dev = encoder->dev;
3664         struct drm_crtc *crtc = encoder->crtc;
3665         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3666         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3667
3668         if (intel_output->load_detect_temp) {
3669                 encoder->crtc = NULL;
3670                 intel_output->base.encoder = NULL;
3671                 intel_output->load_detect_temp = false;
3672                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3673                 drm_helper_disable_unused_functions(dev);
3674         }
3675
3676         /* Switch crtc and output back off if necessary */
3677         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3678                 if (encoder->crtc == crtc)
3679                         encoder_funcs->dpms(encoder, dpms_mode);
3680                 crtc_funcs->dpms(crtc, dpms_mode);
3681         }
3682 }
3683
3684 /* Returns the clock of the currently programmed mode of the given pipe. */
3685 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3686 {
3687         struct drm_i915_private *dev_priv = dev->dev_private;
3688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3689         int pipe = intel_crtc->pipe;
3690         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3691         u32 fp;
3692         intel_clock_t clock;
3693
3694         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3695                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3696         else
3697                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3698
3699         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3700         if (IS_PINEVIEW(dev)) {
3701                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3702                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3703         } else {
3704                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3705                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3706         }
3707
3708         if (IS_I9XX(dev)) {
3709                 if (IS_PINEVIEW(dev))
3710                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3711                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3712                 else
3713                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3714                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3715
3716                 switch (dpll & DPLL_MODE_MASK) {
3717                 case DPLLB_MODE_DAC_SERIAL:
3718                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3719                                 5 : 10;
3720                         break;
3721                 case DPLLB_MODE_LVDS:
3722                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3723                                 7 : 14;
3724                         break;
3725                 default:
3726                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3727                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3728                         return 0;
3729                 }
3730
3731                 /* XXX: Handle the 100Mhz refclk */
3732                 intel_clock(dev, 96000, &clock);
3733         } else {
3734                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3735
3736                 if (is_lvds) {
3737                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3738                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3739                         clock.p2 = 14;
3740
3741                         if ((dpll & PLL_REF_INPUT_MASK) ==
3742                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3743                                 /* XXX: might not be 66MHz */
3744                                 intel_clock(dev, 66000, &clock);
3745                         } else
3746                                 intel_clock(dev, 48000, &clock);
3747                 } else {
3748                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3749                                 clock.p1 = 2;
3750                         else {
3751                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3752                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3753                         }
3754                         if (dpll & PLL_P2_DIVIDE_BY_4)
3755                                 clock.p2 = 4;
3756                         else
3757                                 clock.p2 = 2;
3758
3759                         intel_clock(dev, 48000, &clock);
3760                 }
3761         }
3762
3763         /* XXX: It would be nice to validate the clocks, but we can't reuse
3764          * i830PllIsValid() because it relies on the xf86_config connector
3765          * configuration being accurate, which it isn't necessarily.
3766          */
3767
3768         return clock.dot;
3769 }
3770
3771 /** Returns the currently programmed mode of the given pipe. */
3772 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3773                                              struct drm_crtc *crtc)
3774 {
3775         struct drm_i915_private *dev_priv = dev->dev_private;
3776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777         int pipe = intel_crtc->pipe;
3778         struct drm_display_mode *mode;
3779         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3780         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3781         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3782         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3783
3784         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3785         if (!mode)
3786                 return NULL;
3787
3788         mode->clock = intel_crtc_clock_get(dev, crtc);
3789         mode->hdisplay = (htot & 0xffff) + 1;
3790         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3791         mode->hsync_start = (hsync & 0xffff) + 1;
3792         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3793         mode->vdisplay = (vtot & 0xffff) + 1;
3794         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3795         mode->vsync_start = (vsync & 0xffff) + 1;
3796         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3797
3798         drm_mode_set_name(mode);
3799         drm_mode_set_crtcinfo(mode, 0);
3800
3801         return mode;
3802 }
3803
3804 #define GPU_IDLE_TIMEOUT 500 /* ms */
3805
3806 /* When this timer fires, we've been idle for awhile */
3807 static void intel_gpu_idle_timer(unsigned long arg)
3808 {
3809         struct drm_device *dev = (struct drm_device *)arg;
3810         drm_i915_private_t *dev_priv = dev->dev_private;
3811
3812         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3813
3814         dev_priv->busy = false;
3815
3816         queue_work(dev_priv->wq, &dev_priv->idle_work);
3817 }
3818
3819 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3820
3821 static void intel_crtc_idle_timer(unsigned long arg)
3822 {
3823         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3824         struct drm_crtc *crtc = &intel_crtc->base;
3825         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3826
3827         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3828
3829         intel_crtc->busy = false;
3830
3831         queue_work(dev_priv->wq, &dev_priv->idle_work);
3832 }
3833
3834 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3835 {
3836         struct drm_device *dev = crtc->dev;
3837         drm_i915_private_t *dev_priv = dev->dev_private;
3838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3839         int pipe = intel_crtc->pipe;
3840         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3841         int dpll = I915_READ(dpll_reg);
3842
3843         if (IS_IRONLAKE(dev))
3844                 return;
3845
3846         if (!dev_priv->lvds_downclock_avail)
3847                 return;
3848
3849         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3850                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3851
3852                 /* Unlock panel regs */
3853                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3854
3855                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3856                 I915_WRITE(dpll_reg, dpll);
3857                 dpll = I915_READ(dpll_reg);
3858                 intel_wait_for_vblank(dev);
3859                 dpll = I915_READ(dpll_reg);
3860                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3861                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3862
3863                 /* ...and lock them again */
3864                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3865         }
3866
3867         /* Schedule downclock */
3868         if (schedule)
3869                 mod_timer(&intel_crtc->idle_timer, jiffies +
3870                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3871 }
3872
3873 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3874 {
3875         struct drm_device *dev = crtc->dev;
3876         drm_i915_private_t *dev_priv = dev->dev_private;
3877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3878         int pipe = intel_crtc->pipe;
3879         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3880         int dpll = I915_READ(dpll_reg);
3881
3882         if (IS_IRONLAKE(dev))
3883                 return;
3884
3885         if (!dev_priv->lvds_downclock_avail)
3886                 return;
3887
3888         /*
3889          * Since this is called by a timer, we should never get here in
3890          * the manual case.
3891          */
3892         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3893                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3894
3895                 /* Unlock panel regs */
3896                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3897
3898                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3899                 I915_WRITE(dpll_reg, dpll);
3900                 dpll = I915_READ(dpll_reg);
3901                 intel_wait_for_vblank(dev);
3902                 dpll = I915_READ(dpll_reg);
3903                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3904                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3905
3906                 /* ...and lock them again */
3907                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3908         }
3909
3910 }
3911
3912 /**
3913  * intel_idle_update - adjust clocks for idleness
3914  * @work: work struct
3915  *
3916  * Either the GPU or display (or both) went idle.  Check the busy status
3917  * here and adjust the CRTC and GPU clocks as necessary.
3918  */
3919 static void intel_idle_update(struct work_struct *work)
3920 {
3921         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3922                                                     idle_work);
3923         struct drm_device *dev = dev_priv->dev;
3924         struct drm_crtc *crtc;
3925         struct intel_crtc *intel_crtc;
3926
3927         if (!i915_powersave)
3928                 return;
3929
3930         mutex_lock(&dev->struct_mutex);
3931
3932         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3933                 /* Skip inactive CRTCs */
3934                 if (!crtc->fb)
3935                         continue;
3936
3937                 intel_crtc = to_intel_crtc(crtc);
3938                 if (!intel_crtc->busy)
3939                         intel_decrease_pllclock(crtc);
3940         }
3941
3942         mutex_unlock(&dev->struct_mutex);
3943 }
3944
3945 /**
3946  * intel_mark_busy - mark the GPU and possibly the display busy
3947  * @dev: drm device
3948  * @obj: object we're operating on
3949  *
3950  * Callers can use this function to indicate that the GPU is busy processing
3951  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3952  * buffer), we'll also mark the display as busy, so we know to increase its
3953  * clock frequency.
3954  */
3955 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3956 {
3957         drm_i915_private_t *dev_priv = dev->dev_private;
3958         struct drm_crtc *crtc = NULL;
3959         struct intel_framebuffer *intel_fb;
3960         struct intel_crtc *intel_crtc;
3961
3962         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3963                 return;
3964
3965         if (!dev_priv->busy)
3966                 dev_priv->busy = true;
3967         else
3968                 mod_timer(&dev_priv->idle_timer, jiffies +
3969                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3970
3971         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3972                 if (!crtc->fb)
3973                         continue;
3974
3975                 intel_crtc = to_intel_crtc(crtc);
3976                 intel_fb = to_intel_framebuffer(crtc->fb);
3977                 if (intel_fb->obj == obj) {
3978                         if (!intel_crtc->busy) {
3979                                 /* Non-busy -> busy, upclock */
3980                                 intel_increase_pllclock(crtc, true);
3981                                 intel_crtc->busy = true;
3982                         } else {
3983                                 /* Busy -> busy, put off timer */
3984                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3985                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3986                         }
3987                 }
3988         }
3989 }
3990
3991 static void intel_crtc_destroy(struct drm_crtc *crtc)
3992 {
3993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3994
3995         drm_crtc_cleanup(crtc);
3996         kfree(intel_crtc);
3997 }
3998
3999 struct intel_unpin_work {
4000         struct work_struct work;
4001         struct drm_device *dev;
4002         struct drm_gem_object *obj;
4003         struct drm_pending_vblank_event *event;
4004         int pending;
4005 };
4006
4007 static void intel_unpin_work_fn(struct work_struct *__work)
4008 {
4009         struct intel_unpin_work *work =
4010                 container_of(__work, struct intel_unpin_work, work);
4011
4012         mutex_lock(&work->dev->struct_mutex);
4013         i915_gem_object_unpin(work->obj);
4014         drm_gem_object_unreference(work->obj);
4015         mutex_unlock(&work->dev->struct_mutex);
4016         kfree(work);
4017 }
4018
4019 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4020 {
4021         drm_i915_private_t *dev_priv = dev->dev_private;
4022         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4024         struct intel_unpin_work *work;
4025         struct drm_i915_gem_object *obj_priv;
4026         struct drm_pending_vblank_event *e;
4027         struct timeval now;
4028         unsigned long flags;
4029
4030         /* Ignore early vblank irqs */
4031         if (intel_crtc == NULL)
4032                 return;
4033
4034         spin_lock_irqsave(&dev->event_lock, flags);
4035         work = intel_crtc->unpin_work;
4036         if (work == NULL || !work->pending) {
4037                 spin_unlock_irqrestore(&dev->event_lock, flags);
4038                 return;
4039         }
4040
4041         intel_crtc->unpin_work = NULL;
4042         drm_vblank_put(dev, intel_crtc->pipe);
4043
4044         if (work->event) {
4045                 e = work->event;
4046                 do_gettimeofday(&now);
4047                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4048                 e->event.tv_sec = now.tv_sec;
4049                 e->event.tv_usec = now.tv_usec;
4050                 list_add_tail(&e->base.link,
4051                               &e->base.file_priv->event_list);
4052                 wake_up_interruptible(&e->base.file_priv->event_wait);
4053         }
4054
4055         spin_unlock_irqrestore(&dev->event_lock, flags);
4056
4057         obj_priv = work->obj->driver_private;
4058         if (atomic_dec_and_test(&obj_priv->pending_flip))
4059                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4060         schedule_work(&work->work);
4061 }
4062
4063 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4064 {
4065         drm_i915_private_t *dev_priv = dev->dev_private;
4066         struct intel_crtc *intel_crtc =
4067                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4068         unsigned long flags;
4069
4070         spin_lock_irqsave(&dev->event_lock, flags);
4071         if (intel_crtc->unpin_work)
4072                 intel_crtc->unpin_work->pending = 1;
4073         spin_unlock_irqrestore(&dev->event_lock, flags);
4074 }
4075
4076 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4077                                 struct drm_framebuffer *fb,
4078                                 struct drm_pending_vblank_event *event)
4079 {
4080         struct drm_device *dev = crtc->dev;
4081         struct drm_i915_private *dev_priv = dev->dev_private;
4082         struct intel_framebuffer *intel_fb;
4083         struct drm_i915_gem_object *obj_priv;
4084         struct drm_gem_object *obj;
4085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4086         struct intel_unpin_work *work;
4087         unsigned long flags;
4088         int ret;
4089         RING_LOCALS;
4090
4091         work = kzalloc(sizeof *work, GFP_KERNEL);
4092         if (work == NULL)
4093                 return -ENOMEM;
4094
4095         mutex_lock(&dev->struct_mutex);
4096
4097         work->event = event;
4098         work->dev = crtc->dev;
4099         intel_fb = to_intel_framebuffer(crtc->fb);
4100         work->obj = intel_fb->obj;
4101         INIT_WORK(&work->work, intel_unpin_work_fn);
4102
4103         /* We borrow the event spin lock for protecting unpin_work */
4104         spin_lock_irqsave(&dev->event_lock, flags);
4105         if (intel_crtc->unpin_work) {
4106                 spin_unlock_irqrestore(&dev->event_lock, flags);
4107                 kfree(work);
4108                 mutex_unlock(&dev->struct_mutex);
4109                 return -EBUSY;
4110         }
4111         intel_crtc->unpin_work = work;
4112         spin_unlock_irqrestore(&dev->event_lock, flags);
4113
4114         intel_fb = to_intel_framebuffer(fb);
4115         obj = intel_fb->obj;
4116
4117         ret = intel_pin_and_fence_fb_obj(dev, obj);
4118         if (ret != 0) {
4119                 kfree(work);
4120                 mutex_unlock(&dev->struct_mutex);
4121                 return ret;
4122         }
4123
4124         /* Reference the old fb object for the scheduled work. */
4125         drm_gem_object_reference(work->obj);
4126
4127         crtc->fb = fb;
4128         i915_gem_object_flush_write_domain(obj);
4129         drm_vblank_get(dev, intel_crtc->pipe);
4130         obj_priv = obj->driver_private;
4131         atomic_inc(&obj_priv->pending_flip);
4132
4133         BEGIN_LP_RING(4);
4134         OUT_RING(MI_DISPLAY_FLIP |
4135                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4136         OUT_RING(fb->pitch);
4137         if (IS_I965G(dev)) {
4138                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4139                 OUT_RING((fb->width << 16) | fb->height);
4140         } else {
4141                 OUT_RING(obj_priv->gtt_offset);
4142                 OUT_RING(MI_NOOP);
4143         }
4144         ADVANCE_LP_RING();
4145
4146         mutex_unlock(&dev->struct_mutex);
4147
4148         return 0;
4149 }
4150
4151 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4152         .dpms = intel_crtc_dpms,
4153         .mode_fixup = intel_crtc_mode_fixup,
4154         .mode_set = intel_crtc_mode_set,
4155         .mode_set_base = intel_pipe_set_base,
4156         .prepare = intel_crtc_prepare,
4157         .commit = intel_crtc_commit,
4158         .load_lut = intel_crtc_load_lut,
4159 };
4160
4161 static const struct drm_crtc_funcs intel_crtc_funcs = {
4162         .cursor_set = intel_crtc_cursor_set,
4163         .cursor_move = intel_crtc_cursor_move,
4164         .gamma_set = intel_crtc_gamma_set,
4165         .set_config = drm_crtc_helper_set_config,
4166         .destroy = intel_crtc_destroy,
4167         .page_flip = intel_crtc_page_flip,
4168 };
4169
4170
4171 static void intel_crtc_init(struct drm_device *dev, int pipe)
4172 {
4173         drm_i915_private_t *dev_priv = dev->dev_private;
4174         struct intel_crtc *intel_crtc;
4175         int i;
4176
4177         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4178         if (intel_crtc == NULL)
4179                 return;
4180
4181         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4182
4183         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4184         intel_crtc->pipe = pipe;
4185         intel_crtc->plane = pipe;
4186         for (i = 0; i < 256; i++) {
4187                 intel_crtc->lut_r[i] = i;
4188                 intel_crtc->lut_g[i] = i;
4189                 intel_crtc->lut_b[i] = i;
4190         }
4191
4192         /* Swap pipes & planes for FBC on pre-965 */
4193         intel_crtc->pipe = pipe;
4194         intel_crtc->plane = pipe;
4195         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4196                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4197                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4198         }
4199
4200         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4201                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4202         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4203         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4204
4205         intel_crtc->cursor_addr = 0;
4206         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4207         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4208
4209         intel_crtc->busy = false;
4210
4211         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4212                     (unsigned long)intel_crtc);
4213 }
4214
4215 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4216                                 struct drm_file *file_priv)
4217 {
4218         drm_i915_private_t *dev_priv = dev->dev_private;
4219         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4220         struct drm_mode_object *drmmode_obj;
4221         struct intel_crtc *crtc;
4222
4223         if (!dev_priv) {
4224                 DRM_ERROR("called with no initialization\n");
4225                 return -EINVAL;
4226         }
4227
4228         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4229                         DRM_MODE_OBJECT_CRTC);
4230
4231         if (!drmmode_obj) {
4232                 DRM_ERROR("no such CRTC id\n");
4233                 return -EINVAL;
4234         }
4235
4236         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4237         pipe_from_crtc_id->pipe = crtc->pipe;
4238
4239         return 0;
4240 }
4241
4242 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4243 {
4244         struct drm_crtc *crtc = NULL;
4245
4246         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4247                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4248                 if (intel_crtc->pipe == pipe)
4249                         break;
4250         }
4251         return crtc;
4252 }
4253
4254 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4255 {
4256         int index_mask = 0;
4257         struct drm_connector *connector;
4258         int entry = 0;
4259
4260         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4261                 struct intel_output *intel_output = to_intel_output(connector);
4262                 if (type_mask & intel_output->clone_mask)
4263                         index_mask |= (1 << entry);
4264                 entry++;
4265         }
4266         return index_mask;
4267 }
4268
4269
4270 static void intel_setup_outputs(struct drm_device *dev)
4271 {
4272         struct drm_i915_private *dev_priv = dev->dev_private;
4273         struct drm_connector *connector;
4274
4275         intel_crt_init(dev);
4276
4277         /* Set up integrated LVDS */
4278         if (IS_MOBILE(dev) && !IS_I830(dev))
4279                 intel_lvds_init(dev);
4280
4281         if (IS_IRONLAKE(dev)) {
4282                 int found;
4283
4284                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4285                         intel_dp_init(dev, DP_A);
4286
4287                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4288                         /* check SDVOB */
4289                         /* found = intel_sdvo_init(dev, HDMIB); */
4290                         found = 0;
4291                         if (!found)
4292                                 intel_hdmi_init(dev, HDMIB);
4293                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4294                                 intel_dp_init(dev, PCH_DP_B);
4295                 }
4296
4297                 if (I915_READ(HDMIC) & PORT_DETECTED)
4298                         intel_hdmi_init(dev, HDMIC);
4299
4300                 if (I915_READ(HDMID) & PORT_DETECTED)
4301                         intel_hdmi_init(dev, HDMID);
4302
4303                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4304                         intel_dp_init(dev, PCH_DP_C);
4305
4306                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4307                         intel_dp_init(dev, PCH_DP_D);
4308
4309         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4310                 bool found = false;
4311
4312                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4313                         DRM_DEBUG_KMS("probing SDVOB\n");
4314                         found = intel_sdvo_init(dev, SDVOB);
4315                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4316                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4317                                 intel_hdmi_init(dev, SDVOB);
4318                         }
4319
4320                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4321                                 DRM_DEBUG_KMS("probing DP_B\n");
4322                                 intel_dp_init(dev, DP_B);
4323                         }
4324                 }
4325
4326                 /* Before G4X SDVOC doesn't have its own detect register */
4327
4328                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4329                         DRM_DEBUG_KMS("probing SDVOC\n");
4330                         found = intel_sdvo_init(dev, SDVOC);
4331                 }
4332
4333                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4334
4335                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4336                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4337                                 intel_hdmi_init(dev, SDVOC);
4338                         }
4339                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4340                                 DRM_DEBUG_KMS("probing DP_C\n");
4341                                 intel_dp_init(dev, DP_C);
4342                         }
4343                 }
4344
4345                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4346                     (I915_READ(DP_D) & DP_DETECTED)) {
4347                         DRM_DEBUG_KMS("probing DP_D\n");
4348                         intel_dp_init(dev, DP_D);
4349                 }
4350         } else if (IS_I8XX(dev))
4351                 intel_dvo_init(dev);
4352
4353         if (SUPPORTS_TV(dev))
4354                 intel_tv_init(dev);
4355
4356         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4357                 struct intel_output *intel_output = to_intel_output(connector);
4358                 struct drm_encoder *encoder = &intel_output->enc;
4359
4360                 encoder->possible_crtcs = intel_output->crtc_mask;
4361                 encoder->possible_clones = intel_connector_clones(dev,
4362                                                 intel_output->clone_mask);
4363         }
4364 }
4365
4366 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4367 {
4368         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4369         struct drm_device *dev = fb->dev;
4370
4371         if (fb->fbdev)
4372                 intelfb_remove(dev, fb);
4373
4374         drm_framebuffer_cleanup(fb);
4375         mutex_lock(&dev->struct_mutex);
4376         drm_gem_object_unreference(intel_fb->obj);
4377         mutex_unlock(&dev->struct_mutex);
4378
4379         kfree(intel_fb);
4380 }
4381
4382 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4383                                                 struct drm_file *file_priv,
4384                                                 unsigned int *handle)
4385 {
4386         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4387         struct drm_gem_object *object = intel_fb->obj;
4388
4389         return drm_gem_handle_create(file_priv, object, handle);
4390 }
4391
4392 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4393         .destroy = intel_user_framebuffer_destroy,
4394         .create_handle = intel_user_framebuffer_create_handle,
4395 };
4396
4397 int intel_framebuffer_create(struct drm_device *dev,
4398                              struct drm_mode_fb_cmd *mode_cmd,
4399                              struct drm_framebuffer **fb,
4400                              struct drm_gem_object *obj)
4401 {
4402         struct intel_framebuffer *intel_fb;
4403         int ret;
4404
4405         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4406         if (!intel_fb)
4407                 return -ENOMEM;
4408
4409         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4410         if (ret) {
4411                 DRM_ERROR("framebuffer init failed %d\n", ret);
4412                 return ret;
4413         }
4414
4415         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4416
4417         intel_fb->obj = obj;
4418
4419         *fb = &intel_fb->base;
4420
4421         return 0;
4422 }
4423
4424
4425 static struct drm_framebuffer *
4426 intel_user_framebuffer_create(struct drm_device *dev,
4427                               struct drm_file *filp,
4428                               struct drm_mode_fb_cmd *mode_cmd)
4429 {
4430         struct drm_gem_object *obj;
4431         struct drm_framebuffer *fb;
4432         int ret;
4433
4434         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4435         if (!obj)
4436                 return NULL;
4437
4438         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4439         if (ret) {
4440                 mutex_lock(&dev->struct_mutex);
4441                 drm_gem_object_unreference(obj);
4442                 mutex_unlock(&dev->struct_mutex);
4443                 return NULL;
4444         }
4445
4446         return fb;
4447 }
4448
4449 static const struct drm_mode_config_funcs intel_mode_funcs = {
4450         .fb_create = intel_user_framebuffer_create,
4451         .fb_changed = intelfb_probe,
4452 };
4453
4454 static struct drm_gem_object *
4455 intel_alloc_power_context(struct drm_device *dev)
4456 {
4457         struct drm_gem_object *pwrctx;
4458         int ret;
4459
4460         pwrctx = drm_gem_object_alloc(dev, 4096);
4461         if (!pwrctx) {
4462                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4463                 return NULL;
4464         }
4465
4466         mutex_lock(&dev->struct_mutex);
4467         ret = i915_gem_object_pin(pwrctx, 4096);
4468         if (ret) {
4469                 DRM_ERROR("failed to pin power context: %d\n", ret);
4470                 goto err_unref;
4471         }
4472
4473         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4474         if (ret) {
4475                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4476                 goto err_unpin;
4477         }
4478         mutex_unlock(&dev->struct_mutex);
4479
4480         return pwrctx;
4481
4482 err_unpin:
4483         i915_gem_object_unpin(pwrctx);
4484 err_unref:
4485         drm_gem_object_unreference(pwrctx);
4486         mutex_unlock(&dev->struct_mutex);
4487         return NULL;
4488 }
4489
4490 void intel_init_clock_gating(struct drm_device *dev)
4491 {
4492         struct drm_i915_private *dev_priv = dev->dev_private;
4493
4494         /*
4495          * Disable clock gating reported to work incorrectly according to the
4496          * specs, but enable as much else as we can.
4497          */
4498         if (IS_IRONLAKE(dev)) {
4499                 return;
4500         } else if (IS_G4X(dev)) {
4501                 uint32_t dspclk_gate;
4502                 I915_WRITE(RENCLK_GATE_D1, 0);
4503                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4504                        GS_UNIT_CLOCK_GATE_DISABLE |
4505                        CL_UNIT_CLOCK_GATE_DISABLE);
4506                 I915_WRITE(RAMCLK_GATE_D, 0);
4507                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4508                         OVRUNIT_CLOCK_GATE_DISABLE |
4509                         OVCUNIT_CLOCK_GATE_DISABLE;
4510                 if (IS_GM45(dev))
4511                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4512                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4513         } else if (IS_I965GM(dev)) {
4514                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4515                 I915_WRITE(RENCLK_GATE_D2, 0);
4516                 I915_WRITE(DSPCLK_GATE_D, 0);
4517                 I915_WRITE(RAMCLK_GATE_D, 0);
4518                 I915_WRITE16(DEUC, 0);
4519         } else if (IS_I965G(dev)) {
4520                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4521                        I965_RCC_CLOCK_GATE_DISABLE |
4522                        I965_RCPB_CLOCK_GATE_DISABLE |
4523                        I965_ISC_CLOCK_GATE_DISABLE |
4524                        I965_FBC_CLOCK_GATE_DISABLE);
4525                 I915_WRITE(RENCLK_GATE_D2, 0);
4526         } else if (IS_I9XX(dev)) {
4527                 u32 dstate = I915_READ(D_STATE);
4528
4529                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4530                         DSTATE_DOT_CLOCK_GATING;
4531                 I915_WRITE(D_STATE, dstate);
4532         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4533                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4534         } else if (IS_I830(dev)) {
4535                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4536         }
4537
4538         /*
4539          * GPU can automatically power down the render unit if given a page
4540          * to save state.
4541          */
4542         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4543                 struct drm_i915_gem_object *obj_priv = NULL;
4544
4545                 if (dev_priv->pwrctx) {
4546                         obj_priv = dev_priv->pwrctx->driver_private;
4547                 } else {
4548                         struct drm_gem_object *pwrctx;
4549
4550                         pwrctx = intel_alloc_power_context(dev);
4551                         if (pwrctx) {
4552                                 dev_priv->pwrctx = pwrctx;
4553                                 obj_priv = pwrctx->driver_private;
4554                         }
4555                 }
4556
4557                 if (obj_priv) {
4558                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4559                         I915_WRITE(MCHBAR_RENDER_STANDBY,
4560                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4561                 }
4562         }
4563 }
4564
4565 /* Set up chip specific display functions */
4566 static void intel_init_display(struct drm_device *dev)
4567 {
4568         struct drm_i915_private *dev_priv = dev->dev_private;
4569
4570         /* We always want a DPMS function */
4571         if (IS_IRONLAKE(dev))
4572                 dev_priv->display.dpms = ironlake_crtc_dpms;
4573         else
4574                 dev_priv->display.dpms = i9xx_crtc_dpms;
4575
4576         /* Only mobile has FBC, leave pointers NULL for other chips */
4577         if (IS_MOBILE(dev)) {
4578                 if (IS_GM45(dev)) {
4579                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4580                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4581                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4582                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4583                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4584                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4585                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4586                 }
4587                 /* 855GM needs testing */
4588         }
4589
4590         /* Returns the core display clock speed */
4591         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4592                 dev_priv->display.get_display_clock_speed =
4593                         i945_get_display_clock_speed;
4594         else if (IS_I915G(dev))
4595                 dev_priv->display.get_display_clock_speed =
4596                         i915_get_display_clock_speed;
4597         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4598                 dev_priv->display.get_display_clock_speed =
4599                         i9xx_misc_get_display_clock_speed;
4600         else if (IS_I915GM(dev))
4601                 dev_priv->display.get_display_clock_speed =
4602                         i915gm_get_display_clock_speed;
4603         else if (IS_I865G(dev))
4604                 dev_priv->display.get_display_clock_speed =
4605                         i865_get_display_clock_speed;
4606         else if (IS_I85X(dev))
4607                 dev_priv->display.get_display_clock_speed =
4608                         i855_get_display_clock_speed;
4609         else /* 852, 830 */
4610                 dev_priv->display.get_display_clock_speed =
4611                         i830_get_display_clock_speed;
4612
4613         /* For FIFO watermark updates */
4614         if (IS_IRONLAKE(dev))
4615                 dev_priv->display.update_wm = NULL;
4616         else if (IS_G4X(dev))
4617                 dev_priv->display.update_wm = g4x_update_wm;
4618         else if (IS_I965G(dev))
4619                 dev_priv->display.update_wm = i965_update_wm;
4620         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4621                 dev_priv->display.update_wm = i9xx_update_wm;
4622                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4623         } else {
4624                 if (IS_I85X(dev))
4625                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4626                 else if (IS_845G(dev))
4627                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4628                 else
4629                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4630                 dev_priv->display.update_wm = i830_update_wm;
4631         }
4632 }
4633
4634 void intel_modeset_init(struct drm_device *dev)
4635 {
4636         struct drm_i915_private *dev_priv = dev->dev_private;
4637         int num_pipe;
4638         int i;
4639
4640         drm_mode_config_init(dev);
4641
4642         dev->mode_config.min_width = 0;
4643         dev->mode_config.min_height = 0;
4644
4645         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4646
4647         intel_init_display(dev);
4648
4649         if (IS_I965G(dev)) {
4650                 dev->mode_config.max_width = 8192;
4651                 dev->mode_config.max_height = 8192;
4652         } else if (IS_I9XX(dev)) {
4653                 dev->mode_config.max_width = 4096;
4654                 dev->mode_config.max_height = 4096;
4655         } else {
4656                 dev->mode_config.max_width = 2048;
4657                 dev->mode_config.max_height = 2048;
4658         }
4659
4660         /* set memory base */
4661         if (IS_I9XX(dev))
4662                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4663         else
4664                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4665
4666         if (IS_MOBILE(dev) || IS_I9XX(dev))
4667                 num_pipe = 2;
4668         else
4669                 num_pipe = 1;
4670         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4671                   num_pipe, num_pipe > 1 ? "s" : "");
4672
4673         if (IS_I85X(dev))
4674                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4675         else if (IS_I9XX(dev) || IS_G4X(dev))
4676                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4677
4678         for (i = 0; i < num_pipe; i++) {
4679                 intel_crtc_init(dev, i);
4680         }
4681
4682         intel_setup_outputs(dev);
4683
4684         intel_init_clock_gating(dev);
4685
4686         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4687         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4688                     (unsigned long)dev);
4689
4690         intel_setup_overlay(dev);
4691
4692         if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4693                                                         dev_priv->fsb_freq,
4694                                                         dev_priv->mem_freq))
4695                 DRM_INFO("failed to find known CxSR latency "
4696                          "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4697                          dev_priv->fsb_freq, dev_priv->mem_freq);
4698 }
4699
4700 void intel_modeset_cleanup(struct drm_device *dev)
4701 {
4702         struct drm_i915_private *dev_priv = dev->dev_private;
4703         struct drm_crtc *crtc;
4704         struct intel_crtc *intel_crtc;
4705
4706         mutex_lock(&dev->struct_mutex);
4707
4708         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4709                 /* Skip inactive CRTCs */
4710                 if (!crtc->fb)
4711                         continue;
4712
4713                 intel_crtc = to_intel_crtc(crtc);
4714                 intel_increase_pllclock(crtc, false);
4715                 del_timer_sync(&intel_crtc->idle_timer);
4716         }
4717
4718         del_timer_sync(&dev_priv->idle_timer);
4719
4720         if (dev_priv->display.disable_fbc)
4721                 dev_priv->display.disable_fbc(dev);
4722
4723         if (dev_priv->pwrctx) {
4724                 struct drm_i915_gem_object *obj_priv;
4725
4726                 obj_priv = dev_priv->pwrctx->driver_private;
4727                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4728                 I915_READ(PWRCTXA);
4729                 i915_gem_object_unpin(dev_priv->pwrctx);
4730                 drm_gem_object_unreference(dev_priv->pwrctx);
4731         }
4732
4733         mutex_unlock(&dev->struct_mutex);
4734
4735         drm_mode_config_cleanup(dev);
4736 }
4737
4738
4739 /* current intel driver doesn't take advantage of encoders
4740    always give back the encoder for the connector
4741 */
4742 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4743 {
4744         struct intel_output *intel_output = to_intel_output(connector);
4745
4746         return &intel_output->enc;
4747 }
4748
4749 /*
4750  * set vga decode state - true == enable VGA decode
4751  */
4752 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4753 {
4754         struct drm_i915_private *dev_priv = dev->dev_private;
4755         u16 gmch_ctrl;
4756
4757         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4758         if (state)
4759                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4760         else
4761                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4762         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4763         return 0;
4764 }