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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "drm_dp_helper.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73 };
  74
  75 #define I8XX_DOT_MIN              25000
  76 #define I8XX_DOT_MAX             350000
  77 #define I8XX_VCO_MIN             930000
  78 #define I8XX_VCO_MAX            1400000
  79 #define I8XX_N_MIN                    3
  80 #define I8XX_N_MAX                   16
  81 #define I8XX_M_MIN                   96
  82 #define I8XX_M_MAX                  140
  83 #define I8XX_M1_MIN                  18
  84 #define I8XX_M1_MAX                  26
  85 #define I8XX_M2_MIN                   6
  86 #define I8XX_M2_MAX                  16
  87 #define I8XX_P_MIN                    4
  88 #define I8XX_P_MAX                  128
  89 #define I8XX_P1_MIN                   2
  90 #define I8XX_P1_MAX                  33
  91 #define I8XX_P1_LVDS_MIN              1
  92 #define I8XX_P1_LVDS_MAX              6
  93 #define I8XX_P2_SLOW                  4
  94 #define I8XX_P2_FAST                  2
  95 #define I8XX_P2_LVDS_SLOW             14
  96 #define I8XX_P2_LVDS_FAST             7
  97 #define I8XX_P2_SLOW_LIMIT       165000
  98
  99 #define I9XX_DOT_MIN              20000
 100 #define I9XX_DOT_MAX             400000
 101 #define I9XX_VCO_MIN            1400000
 102 #define I9XX_VCO_MAX            2800000
 103 #define PINEVIEW_VCO_MIN                1700000
 104 #define PINEVIEW_VCO_MAX                3500000
 105 #define I9XX_N_MIN                    1
 106 #define I9XX_N_MAX                    6
 107 /* Pineview's Ncounter is a ring counter */
 108 #define PINEVIEW_N_MIN                3
 109 #define PINEVIEW_N_MAX                6
 110 #define I9XX_M_MIN                   70
 111 #define I9XX_M_MAX                  120
 112 #define PINEVIEW_M_MIN                2
 113 #define PINEVIEW_M_MAX              256
 114 #define I9XX_M1_MIN                  10
 115 #define I9XX_M1_MAX                  22
 116 #define I9XX_M2_MIN                   5
 117 #define I9XX_M2_MAX                   9
 118 /* Pineview M1 is reserved, and must be 0 */
 119 #define PINEVIEW_M1_MIN               0
 120 #define PINEVIEW_M1_MAX               0
 121 #define PINEVIEW_M2_MIN               0
 122 #define PINEVIEW_M2_MAX               254
 123 #define I9XX_P_SDVO_DAC_MIN           5
 124 #define I9XX_P_SDVO_DAC_MAX          80
 125 #define I9XX_P_LVDS_MIN               7
 126 #define I9XX_P_LVDS_MAX              98
 127 #define PINEVIEW_P_LVDS_MIN                   7
 128 #define PINEVIEW_P_LVDS_MAX                  112
 129 #define I9XX_P1_MIN                   1
 130 #define I9XX_P1_MAX                   8
 131 #define I9XX_P2_SDVO_DAC_SLOW                10
 132 #define I9XX_P2_SDVO_DAC_FAST                 5
 133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 134 #define I9XX_P2_LVDS_SLOW                    14
 135 #define I9XX_P2_LVDS_FAST                     7
 136 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 137
 138 /*The parameter is for SDVO on G4x platform*/
 139 #define G4X_DOT_SDVO_MIN           25000
 140 #define G4X_DOT_SDVO_MAX           270000
 141 #define G4X_VCO_MIN                1750000
 142 #define G4X_VCO_MAX                3500000
 143 #define G4X_N_SDVO_MIN             1
 144 #define G4X_N_SDVO_MAX             4
 145 #define G4X_M_SDVO_MIN             104
 146 #define G4X_M_SDVO_MAX             138
 147 #define G4X_M1_SDVO_MIN            17
 148 #define G4X_M1_SDVO_MAX            23
 149 #define G4X_M2_SDVO_MIN            5
 150 #define G4X_M2_SDVO_MAX            11
 151 #define G4X_P_SDVO_MIN             10
 152 #define G4X_P_SDVO_MAX             30
 153 #define G4X_P1_SDVO_MIN            1
 154 #define G4X_P1_SDVO_MAX            3
 155 #define G4X_P2_SDVO_SLOW           10
 156 #define G4X_P2_SDVO_FAST           10
 157 #define G4X_P2_SDVO_LIMIT          270000
 158
 159 /*The parameter is for HDMI_DAC on G4x platform*/
 160 #define G4X_DOT_HDMI_DAC_MIN           22000
 161 #define G4X_DOT_HDMI_DAC_MAX           400000
 162 #define G4X_N_HDMI_DAC_MIN             1
 163 #define G4X_N_HDMI_DAC_MAX             4
 164 #define G4X_M_HDMI_DAC_MIN             104
 165 #define G4X_M_HDMI_DAC_MAX             138
 166 #define G4X_M1_HDMI_DAC_MIN            16
 167 #define G4X_M1_HDMI_DAC_MAX            23
 168 #define G4X_M2_HDMI_DAC_MIN            5
 169 #define G4X_M2_HDMI_DAC_MAX            11
 170 #define G4X_P_HDMI_DAC_MIN             5
 171 #define G4X_P_HDMI_DAC_MAX             80
 172 #define G4X_P1_HDMI_DAC_MIN            1
 173 #define G4X_P1_HDMI_DAC_MAX            8
 174 #define G4X_P2_HDMI_DAC_SLOW           10
 175 #define G4X_P2_HDMI_DAC_FAST           5
 176 #define G4X_P2_HDMI_DAC_LIMIT          165000
 177
 178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 196
 197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 215
 216 /*The parameter is for DISPLAY PORT on G4x platform*/
 217 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 218 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 219 #define G4X_N_DISPLAY_PORT_MIN             1
 220 #define G4X_N_DISPLAY_PORT_MAX             2
 221 #define G4X_M_DISPLAY_PORT_MIN             97
 222 #define G4X_M_DISPLAY_PORT_MAX             108
 223 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 224 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 225 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 226 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 227 #define G4X_P_DISPLAY_PORT_MIN             10
 228 #define G4X_P_DISPLAY_PORT_MAX             20
 229 #define G4X_P1_DISPLAY_PORT_MIN            1
 230 #define G4X_P1_DISPLAY_PORT_MAX            2
 231 #define G4X_P2_DISPLAY_PORT_SLOW           10
 232 #define G4X_P2_DISPLAY_PORT_FAST           10
 233 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 234
 235 /* Ironlake / Sandybridge */
 236 /* as we calculate clock using (register_value + 2) for
 237    N/M1/M2, so here the range value for them is (actual_value-2).
 238  */
 239 #define IRONLAKE_DOT_MIN         25000
 240 #define IRONLAKE_DOT_MAX         350000
 241 #define IRONLAKE_VCO_MIN         1760000
 242 #define IRONLAKE_VCO_MAX         3510000
 243 #define IRONLAKE_M1_MIN          12
 244 #define IRONLAKE_M1_MAX          22
 245 #define IRONLAKE_M2_MIN          5
 246 #define IRONLAKE_M2_MAX          9
 247 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 248
 249 /* We have parameter ranges for different type of outputs. */
 250
 251 /* DAC & HDMI Refclk 120Mhz */
 252 #define IRONLAKE_DAC_N_MIN      1
 253 #define IRONLAKE_DAC_N_MAX      5
 254 #define IRONLAKE_DAC_M_MIN      79
 255 #define IRONLAKE_DAC_M_MAX      127
 256 #define IRONLAKE_DAC_P_MIN      5
 257 #define IRONLAKE_DAC_P_MAX      80
 258 #define IRONLAKE_DAC_P1_MIN     1
 259 #define IRONLAKE_DAC_P1_MAX     8
 260 #define IRONLAKE_DAC_P2_SLOW    10
 261 #define IRONLAKE_DAC_P2_FAST    5
 262
 263 /* LVDS single-channel 120Mhz refclk */
 264 #define IRONLAKE_LVDS_S_N_MIN   1
 265 #define IRONLAKE_LVDS_S_N_MAX   3
 266 #define IRONLAKE_LVDS_S_M_MIN   79
 267 #define IRONLAKE_LVDS_S_M_MAX   118
 268 #define IRONLAKE_LVDS_S_P_MIN   28
 269 #define IRONLAKE_LVDS_S_P_MAX   112
 270 #define IRONLAKE_LVDS_S_P1_MIN  2
 271 #define IRONLAKE_LVDS_S_P1_MAX  8
 272 #define IRONLAKE_LVDS_S_P2_SLOW 14
 273 #define IRONLAKE_LVDS_S_P2_FAST 14
 274
 275 /* LVDS dual-channel 120Mhz refclk */
 276 #define IRONLAKE_LVDS_D_N_MIN   1
 277 #define IRONLAKE_LVDS_D_N_MAX   3
 278 #define IRONLAKE_LVDS_D_M_MIN   79
 279 #define IRONLAKE_LVDS_D_M_MAX   127
 280 #define IRONLAKE_LVDS_D_P_MIN   14
 281 #define IRONLAKE_LVDS_D_P_MAX   56
 282 #define IRONLAKE_LVDS_D_P1_MIN  2
 283 #define IRONLAKE_LVDS_D_P1_MAX  8
 284 #define IRONLAKE_LVDS_D_P2_SLOW 7
 285 #define IRONLAKE_LVDS_D_P2_FAST 7
 286
 287 /* LVDS single-channel 100Mhz refclk */
 288 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 289 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 290 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 291 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 292 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 293 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 294 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 295 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 296 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 297 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 298
 299 /* LVDS dual-channel 100Mhz refclk */
 300 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 301 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 302 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 303 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 304 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 305 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 306 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 307 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 308 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 309 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 310
 311 /* DisplayPort */
 312 #define IRONLAKE_DP_N_MIN               1
 313 #define IRONLAKE_DP_N_MAX               2
 314 #define IRONLAKE_DP_M_MIN               81
 315 #define IRONLAKE_DP_M_MAX               90
 316 #define IRONLAKE_DP_P_MIN               10
 317 #define IRONLAKE_DP_P_MAX               20
 318 #define IRONLAKE_DP_P2_FAST             10
 319 #define IRONLAKE_DP_P2_SLOW             10
 320 #define IRONLAKE_DP_P2_LIMIT            0
 321 #define IRONLAKE_DP_P1_MIN              1
 322 #define IRONLAKE_DP_P1_MAX              2
 323
 324 static bool
 325 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 326                     int target, int refclk, intel_clock_t *best_clock);
 327 static bool
 328 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 329                         int target, int refclk, intel_clock_t *best_clock);
 330
 331 static bool
 332 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 333                       int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 336                            int target, int refclk, intel_clock_t *best_clock);
 337
 338 static const intel_limit_t intel_limits_i8xx_dvo = {
 339         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 340         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 341         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 342         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 343         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 344         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 345         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 346         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 347         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 348                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 349         .find_pll = intel_find_best_PLL,
 350 };
 351
 352 static const intel_limit_t intel_limits_i8xx_lvds = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i9xx_sdvo = {
 367         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 368         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 369         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 370         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 371         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 372         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 373         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 374         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 375         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 376                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_lvds = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         /* The single-channel range is 25-112Mhz, and dual-channel
 390          * is 80-224Mhz.  Prefer single channel as much as possible.
 391          */
 392         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397     /* below parameter and function is for G4X Chipset Family*/
 398 static const intel_limit_t intel_limits_g4x_sdvo = {
 399         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 400         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 401         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 402         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 403         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 404         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 405         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 406         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 407         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 408                  .p2_slow = G4X_P2_SDVO_SLOW,
 409                  .p2_fast = G4X_P2_SDVO_FAST
 410         },
 411         .find_pll = intel_g4x_find_best_PLL,
 412 };
 413
 414 static const intel_limit_t intel_limits_g4x_hdmi = {
 415         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 416         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 417         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 418         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 419         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 420         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 421         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 422         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 423         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 424                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 425                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 426         },
 427         .find_pll = intel_g4x_find_best_PLL,
 428 };
 429
 430 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 431         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 432                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 433         .vco = { .min = G4X_VCO_MIN,
 434                  .max = G4X_VCO_MAX },
 435         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 436                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 437         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 438                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 439         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 440                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 441         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 442                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 443         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 444                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 445         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 447         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 448                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 449                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 450         },
 451         .find_pll = intel_g4x_find_best_PLL,
 452 };
 453
 454 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 455         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 456                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 457         .vco = { .min = G4X_VCO_MIN,
 458                  .max = G4X_VCO_MAX },
 459         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 460                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 461         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 462                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 463         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 464                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 465         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 466                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 467         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 468                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 469         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 471         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 472                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 473                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 474         },
 475         .find_pll = intel_g4x_find_best_PLL,
 476 };
 477
 478 static const intel_limit_t intel_limits_g4x_display_port = {
 479         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 480                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 481         .vco = { .min = G4X_VCO_MIN,
 482                  .max = G4X_VCO_MAX},
 483         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 484                  .max = G4X_N_DISPLAY_PORT_MAX },
 485         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 486                  .max = G4X_M_DISPLAY_PORT_MAX },
 487         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 488                  .max = G4X_M1_DISPLAY_PORT_MAX },
 489         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 490                  .max = G4X_M2_DISPLAY_PORT_MAX },
 491         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 492                  .max = G4X_P_DISPLAY_PORT_MAX },
 493         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 494                  .max = G4X_P1_DISPLAY_PORT_MAX},
 495         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 496                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 497                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 498         .find_pll = intel_find_pll_g4x_dp,
 499 };
 500
 501 static const intel_limit_t intel_limits_pineview_sdvo = {
 502         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 503         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 504         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 505         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 506         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 507         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 508         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 509         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 510         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 511                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 512         .find_pll = intel_find_best_PLL,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_lvds = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         /* Pineview only supports single-channel mode. */
 525         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 526                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 527         .find_pll = intel_find_best_PLL,
 528 };
 529
 530 static const intel_limit_t intel_limits_ironlake_dac = {
 531         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 532         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 533         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 534         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 535         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 536         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 537         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 538         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 539         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 540                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 541                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 542         .find_pll = intel_g4x_find_best_PLL,
 543 };
 544
 545 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 546         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 547         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 548         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 549         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 550         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 551         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 552         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 553         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 554         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 555                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 556                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 557         .find_pll = intel_g4x_find_best_PLL,
 558 };
 559
 560 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 561         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 562         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 563         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 564         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 565         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 566         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 567         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 568         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 569         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 570                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 571                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 572         .find_pll = intel_g4x_find_best_PLL,
 573 };
 574
 575 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 576         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 577         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 578         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 579         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 580         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 581         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 582         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 583         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 584         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 585                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 586                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 587         .find_pll = intel_g4x_find_best_PLL,
 588 };
 589
 590 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 591         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 592         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 593         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 594         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 595         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 596         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 597         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 598         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 599         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 600                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 601                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 602         .find_pll = intel_g4x_find_best_PLL,
 603 };
 604
 605 static const intel_limit_t intel_limits_ironlake_display_port = {
 606         .dot = { .min = IRONLAKE_DOT_MIN,
 607                  .max = IRONLAKE_DOT_MAX },
 608         .vco = { .min = IRONLAKE_VCO_MIN,
 609                  .max = IRONLAKE_VCO_MAX},
 610         .n   = { .min = IRONLAKE_DP_N_MIN,
 611                  .max = IRONLAKE_DP_N_MAX },
 612         .m   = { .min = IRONLAKE_DP_M_MIN,
 613                  .max = IRONLAKE_DP_M_MAX },
 614         .m1  = { .min = IRONLAKE_M1_MIN,
 615                  .max = IRONLAKE_M1_MAX },
 616         .m2  = { .min = IRONLAKE_M2_MIN,
 617                  .max = IRONLAKE_M2_MAX },
 618         .p   = { .min = IRONLAKE_DP_P_MIN,
 619                  .max = IRONLAKE_DP_P_MAX },
 620         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 621                  .max = IRONLAKE_DP_P1_MAX},
 622         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 623                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 624                  .p2_fast = IRONLAKE_DP_P2_FAST },
 625         .find_pll = intel_find_pll_ironlake_dp,
 626 };
 627
 628 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         struct drm_i915_private *dev_priv = dev->dev_private;
 632         const intel_limit_t *limit;
 633         int refclk = 120;
 634
 635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 636                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 637                         refclk = 100;
 638
 639                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 640                     LVDS_CLKB_POWER_UP) {
 641                         /* LVDS dual channel */
 642                         if (refclk == 100)
 643                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 644                         else
 645                                 limit = &intel_limits_ironlake_dual_lvds;
 646                 } else {
 647                         if (refclk == 100)
 648                                 limit = &intel_limits_ironlake_single_lvds_100m;
 649                         else
 650                                 limit = &intel_limits_ironlake_single_lvds;
 651                 }
 652         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 653                         HAS_eDP)
 654                 limit = &intel_limits_ironlake_display_port;
 655         else
 656                 limit = &intel_limits_ironlake_dac;
 657
 658         return limit;
 659 }
 660
 661 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 662 {
 663         struct drm_device *dev = crtc->dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         const intel_limit_t *limit;
 666
 667         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 668                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 669                     LVDS_CLKB_POWER_UP)
 670                         /* LVDS with dual channel */
 671                         limit = &intel_limits_g4x_dual_channel_lvds;
 672                 else
 673                         /* LVDS with dual channel */
 674                         limit = &intel_limits_g4x_single_channel_lvds;
 675         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 676                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 677                 limit = &intel_limits_g4x_hdmi;
 678         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 679                 limit = &intel_limits_g4x_sdvo;
 680         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 681                 limit = &intel_limits_g4x_display_port;
 682         } else /* The option is for other outputs */
 683                 limit = &intel_limits_i9xx_sdvo;
 684
 685         return limit;
 686 }
 687
 688 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         const intel_limit_t *limit;
 692
 693         if (HAS_PCH_SPLIT(dev))
 694                 limit = intel_ironlake_limit(crtc);
 695         else if (IS_G4X(dev)) {
 696                 limit = intel_g4x_limit(crtc);
 697         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 698                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 699                         limit = &intel_limits_i9xx_lvds;
 700                 else
 701                         limit = &intel_limits_i9xx_sdvo;
 702         } else if (IS_PINEVIEW(dev)) {
 703                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 704                         limit = &intel_limits_pineview_lvds;
 705                 else
 706                         limit = &intel_limits_pineview_sdvo;
 707         } else {
 708                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 709                         limit = &intel_limits_i8xx_lvds;
 710                 else
 711                         limit = &intel_limits_i8xx_dvo;
 712         }
 713         return limit;
 714 }
 715
 716 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 717 static void pineview_clock(int refclk, intel_clock_t *clock)
 718 {
 719         clock->m = clock->m2 + 2;
 720         clock->p = clock->p1 * clock->p2;
 721         clock->vco = refclk * clock->m / clock->n;
 722         clock->dot = clock->vco / clock->p;
 723 }
 724
 725 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 726 {
 727         if (IS_PINEVIEW(dev)) {
 728                 pineview_clock(refclk, clock);
 729                 return;
 730         }
 731         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 732         clock->p = clock->p1 * clock->p2;
 733         clock->vco = refclk * clock->m / (clock->n + 2);
 734         clock->dot = clock->vco / clock->p;
 735 }
 736
 737 /**
 738  * Returns whether any output on the specified pipe is of the specified type
 739  */
 740 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 741 {
 742     struct drm_device *dev = crtc->dev;
 743     struct drm_mode_config *mode_config = &dev->mode_config;
 744     struct drm_encoder *l_entry;
 745
 746     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 747             if (l_entry && l_entry->crtc == crtc) {
 748                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 749                     if (intel_encoder->type == type)
 750                             return true;
 751             }
 752     }
 753     return false;
 754 }
 755
 756 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 757 /**
 758  * Returns whether the given set of divisors are valid for a given refclk with
 759  * the given connectors.
 760  */
 761
 762 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 763 {
 764         const intel_limit_t *limit = intel_limit (crtc);
 765         struct drm_device *dev = crtc->dev;
 766
 767         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 768                 INTELPllInvalid ("p1 out of range\n");
 769         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 770                 INTELPllInvalid ("p out of range\n");
 771         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 772                 INTELPllInvalid ("m2 out of range\n");
 773         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 774                 INTELPllInvalid ("m1 out of range\n");
 775         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 776                 INTELPllInvalid ("m1 <= m2\n");
 777         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 778                 INTELPllInvalid ("m out of range\n");
 779         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 780                 INTELPllInvalid ("n out of range\n");
 781         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 782                 INTELPllInvalid ("vco out of range\n");
 783         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 784          * connector, etc., rather than just a single range.
 785          */
 786         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 787                 INTELPllInvalid ("dot out of range\n");
 788
 789         return true;
 790 }
 791
 792 static bool
 793 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 794                     int target, int refclk, intel_clock_t *best_clock)
 795
 796 {
 797         struct drm_device *dev = crtc->dev;
 798         struct drm_i915_private *dev_priv = dev->dev_private;
 799         intel_clock_t clock;
 800         int err = target;
 801
 802         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 803             (I915_READ(LVDS)) != 0) {
 804                 /*
 805                  * For LVDS, if the panel is on, just rely on its current
 806                  * settings for dual-channel.  We haven't figured out how to
 807                  * reliably set up different single/dual channel state, if we
 808                  * even can.
 809                  */
 810                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 811                     LVDS_CLKB_POWER_UP)
 812                         clock.p2 = limit->p2.p2_fast;
 813                 else
 814                         clock.p2 = limit->p2.p2_slow;
 815         } else {
 816                 if (target < limit->p2.dot_limit)
 817                         clock.p2 = limit->p2.p2_slow;
 818                 else
 819                         clock.p2 = limit->p2.p2_fast;
 820         }
 821
 822         memset (best_clock, 0, sizeof (*best_clock));
 823
 824         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 825              clock.m1++) {
 826                 for (clock.m2 = limit->m2.min;
 827                      clock.m2 <= limit->m2.max; clock.m2++) {
 828                         /* m1 is always 0 in Pineview */
 829                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 830                                 break;
 831                         for (clock.n = limit->n.min;
 832                              clock.n <= limit->n.max; clock.n++) {
 833                                 for (clock.p1 = limit->p1.min;
 834                                         clock.p1 <= limit->p1.max; clock.p1++) {
 835                                         int this_err;
 836
 837                                         intel_clock(dev, refclk, &clock);
 838
 839                                         if (!intel_PLL_is_valid(crtc, &clock))
 840                                                 continue;
 841
 842                                         this_err = abs(clock.dot - target);
 843                                         if (this_err < err) {
 844                                                 *best_clock = clock;
 845                                                 err = this_err;
 846                                         }
 847                                 }
 848                         }
 849                 }
 850         }
 851
 852         return (err != target);
 853 }
 854
 855 static bool
 856 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 857                         int target, int refclk, intel_clock_t *best_clock)
 858 {
 859         struct drm_device *dev = crtc->dev;
 860         struct drm_i915_private *dev_priv = dev->dev_private;
 861         intel_clock_t clock;
 862         int max_n;
 863         bool found;
 864         /* approximately equals target * 0.00488 */
 865         int err_most = (target >> 8) + (target >> 10);
 866         found = false;
 867
 868         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 869                 int lvds_reg;
 870
 871                 if (HAS_PCH_SPLIT(dev))
 872                         lvds_reg = PCH_LVDS;
 873                 else
 874                         lvds_reg = LVDS;
 875                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 876                     LVDS_CLKB_POWER_UP)
 877                         clock.p2 = limit->p2.p2_fast;
 878                 else
 879                         clock.p2 = limit->p2.p2_slow;
 880         } else {
 881                 if (target < limit->p2.dot_limit)
 882                         clock.p2 = limit->p2.p2_slow;
 883                 else
 884                         clock.p2 = limit->p2.p2_fast;
 885         }
 886
 887         memset(best_clock, 0, sizeof(*best_clock));
 888         max_n = limit->n.max;
 889         /* based on hardware requriment prefer smaller n to precision */
 890         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 891                 /* based on hardware requirment prefere larger m1,m2 */
 892                 for (clock.m1 = limit->m1.max;
 893                      clock.m1 >= limit->m1.min; clock.m1--) {
 894                         for (clock.m2 = limit->m2.max;
 895                              clock.m2 >= limit->m2.min; clock.m2--) {
 896                                 for (clock.p1 = limit->p1.max;
 897                                      clock.p1 >= limit->p1.min; clock.p1--) {
 898                                         int this_err;
 899
 900                                         intel_clock(dev, refclk, &clock);
 901                                         if (!intel_PLL_is_valid(crtc, &clock))
 902                                                 continue;
 903                                         this_err = abs(clock.dot - target) ;
 904                                         if (this_err < err_most) {
 905                                                 *best_clock = clock;
 906                                                 err_most = this_err;
 907                                                 max_n = clock.n;
 908                                                 found = true;
 909                                         }
 910                                 }
 911                         }
 912                 }
 913         }
 914         return found;
 915 }
 916
 917 static bool
 918 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 919                            int target, int refclk, intel_clock_t *best_clock)
 920 {
 921         struct drm_device *dev = crtc->dev;
 922         intel_clock_t clock;
 923
 924         /* return directly when it is eDP */
 925         if (HAS_eDP)
 926                 return true;
 927
 928         if (target < 200000) {
 929                 clock.n = 1;
 930                 clock.p1 = 2;
 931                 clock.p2 = 10;
 932                 clock.m1 = 12;
 933                 clock.m2 = 9;
 934         } else {
 935                 clock.n = 2;
 936                 clock.p1 = 1;
 937                 clock.p2 = 10;
 938                 clock.m1 = 14;
 939                 clock.m2 = 8;
 940         }
 941         intel_clock(dev, refclk, &clock);
 942         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 943         return true;
 944 }
 945
 946 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 947 static bool
 948 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 949                       int target, int refclk, intel_clock_t *best_clock)
 950 {
 951     intel_clock_t clock;
 952     if (target < 200000) {
 953         clock.p1 = 2;
 954         clock.p2 = 10;
 955         clock.n = 2;
 956         clock.m1 = 23;
 957         clock.m2 = 8;
 958     } else {
 959         clock.p1 = 1;
 960         clock.p2 = 10;
 961         clock.n = 1;
 962         clock.m1 = 14;
 963         clock.m2 = 2;
 964     }
 965     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 966     clock.p = (clock.p1 * clock.p2);
 967     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 968     clock.vco = 0;
 969     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 970     return true;
 971 }
 972
 973 void
 974 intel_wait_for_vblank(struct drm_device *dev)
 975 {
 976         /* Wait for 20ms, i.e. one cycle at 50hz. */
 977         msleep(20);
 978 }
 979
 980 /* Parameters have changed, update FBC info */
 981 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 982 {
 983         struct drm_device *dev = crtc->dev;
 984         struct drm_i915_private *dev_priv = dev->dev_private;
 985         struct drm_framebuffer *fb = crtc->fb;
 986         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 987         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
 988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 989         int plane, i;
 990         u32 fbc_ctl, fbc_ctl2;
 991
 992         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 993
 994         if (fb->pitch < dev_priv->cfb_pitch)
 995                 dev_priv->cfb_pitch = fb->pitch;
 996
 997         /* FBC_CTL wants 64B units */
 998         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 999         dev_priv->cfb_fence = obj_priv->fence_reg;
1000         dev_priv->cfb_plane = intel_crtc->plane;
1001         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1002
1003         /* Clear old tags */
1004         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1005                 I915_WRITE(FBC_TAG + (i * 4), 0);
1006
1007         /* Set it up... */
1008         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1009         if (obj_priv->tiling_mode != I915_TILING_NONE)
1010                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1011         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1012         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1013
1014         /* enable it... */
1015         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1016         if (IS_I945GM(dev))
1017                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1018         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1019         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1020         if (obj_priv->tiling_mode != I915_TILING_NONE)
1021                 fbc_ctl |= dev_priv->cfb_fence;
1022         I915_WRITE(FBC_CONTROL, fbc_ctl);
1023
1024         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1025                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1026 }
1027
1028 void i8xx_disable_fbc(struct drm_device *dev)
1029 {
1030         struct drm_i915_private *dev_priv = dev->dev_private;
1031         u32 fbc_ctl;
1032
1033         if (!I915_HAS_FBC(dev))
1034                 return;
1035
1036         /* Disable compression */
1037         fbc_ctl = I915_READ(FBC_CONTROL);
1038         fbc_ctl &= ~FBC_CTL_EN;
1039         I915_WRITE(FBC_CONTROL, fbc_ctl);
1040
1041         /* Wait for compressing bit to clear */
1042         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1043                 ; /* nothing */
1044
1045         intel_wait_for_vblank(dev);
1046
1047         DRM_DEBUG_KMS("disabled FBC\n");
1048 }
1049
1050 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1051 {
1052         struct drm_device *dev = crtc->dev;
1053         struct drm_i915_private *dev_priv = dev->dev_private;
1054
1055         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1056 }
1057
1058 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1059 {
1060         struct drm_device *dev = crtc->dev;
1061         struct drm_i915_private *dev_priv = dev->dev_private;
1062         struct drm_framebuffer *fb = crtc->fb;
1063         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1064         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1066         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1067                      DPFC_CTL_PLANEB);
1068         unsigned long stall_watermark = 200;
1069         u32 dpfc_ctl;
1070
1071         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1072         dev_priv->cfb_fence = obj_priv->fence_reg;
1073         dev_priv->cfb_plane = intel_crtc->plane;
1074
1075         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1076         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1077                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1078                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1079         } else {
1080                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1081         }
1082
1083         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1084         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1085                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1086                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1087         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1088
1089         /* enable it... */
1090         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1091
1092         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1093 }
1094
1095 void g4x_disable_fbc(struct drm_device *dev)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         u32 dpfc_ctl;
1099
1100         /* Disable compression */
1101         dpfc_ctl = I915_READ(DPFC_CONTROL);
1102         dpfc_ctl &= ~DPFC_CTL_EN;
1103         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1104         intel_wait_for_vblank(dev);
1105
1106         DRM_DEBUG_KMS("disabled FBC\n");
1107 }
1108
1109 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1110 {
1111         struct drm_device *dev = crtc->dev;
1112         struct drm_i915_private *dev_priv = dev->dev_private;
1113
1114         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1115 }
1116
1117 /**
1118  * intel_update_fbc - enable/disable FBC as needed
1119  * @crtc: CRTC to point the compressor at
1120  * @mode: mode in use
1121  *
1122  * Set up the framebuffer compression hardware at mode set time.  We
1123  * enable it if possible:
1124  *   - plane A only (on pre-965)
1125  *   - no pixel mulitply/line duplication
1126  *   - no alpha buffer discard
1127  *   - no dual wide
1128  *   - framebuffer <= 2048 in width, 1536 in height
1129  *
1130  * We can't assume that any compression will take place (worst case),
1131  * so the compressed buffer has to be the same size as the uncompressed
1132  * one.  It also must reside (along with the line length buffer) in
1133  * stolen memory.
1134  *
1135  * We need to enable/disable FBC on a global basis.
1136  */
1137 static void intel_update_fbc(struct drm_crtc *crtc,
1138                              struct drm_display_mode *mode)
1139 {
1140         struct drm_device *dev = crtc->dev;
1141         struct drm_i915_private *dev_priv = dev->dev_private;
1142         struct drm_framebuffer *fb = crtc->fb;
1143         struct intel_framebuffer *intel_fb;
1144         struct drm_i915_gem_object *obj_priv;
1145         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1146         int plane = intel_crtc->plane;
1147
1148         if (!i915_powersave)
1149                 return;
1150
1151         if (!dev_priv->display.fbc_enabled ||
1152             !dev_priv->display.enable_fbc ||
1153             !dev_priv->display.disable_fbc)
1154                 return;
1155
1156         if (!crtc->fb)
1157                 return;
1158
1159         intel_fb = to_intel_framebuffer(fb);
1160         obj_priv = to_intel_bo(intel_fb->obj);
1161
1162         /*
1163          * If FBC is already on, we just have to verify that we can
1164          * keep it that way...
1165          * Need to disable if:
1166          *   - changing FBC params (stride, fence, mode)
1167          *   - new fb is too large to fit in compressed buffer
1168          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1169          */
1170         if (intel_fb->obj->size > dev_priv->cfb_size) {
1171                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1172                                 "compression\n");
1173                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1174                 goto out_disable;
1175         }
1176         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1177             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1178                 DRM_DEBUG_KMS("mode incompatible with compression, "
1179                                 "disabling\n");
1180                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1181                 goto out_disable;
1182         }
1183         if ((mode->hdisplay > 2048) ||
1184             (mode->vdisplay > 1536)) {
1185                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1186                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1187                 goto out_disable;
1188         }
1189         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1190                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1191                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1192                 goto out_disable;
1193         }
1194         if (obj_priv->tiling_mode != I915_TILING_X) {
1195                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1196                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1197                 goto out_disable;
1198         }
1199
1200         if (dev_priv->display.fbc_enabled(crtc)) {
1201                 /* We can re-enable it in this case, but need to update pitch */
1202                 if (fb->pitch > dev_priv->cfb_pitch)
1203                         dev_priv->display.disable_fbc(dev);
1204                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1205                         dev_priv->display.disable_fbc(dev);
1206                 if (plane != dev_priv->cfb_plane)
1207                         dev_priv->display.disable_fbc(dev);
1208         }
1209
1210         if (!dev_priv->display.fbc_enabled(crtc)) {
1211                 /* Now try to turn it back on if possible */
1212                 dev_priv->display.enable_fbc(crtc, 500);
1213         }
1214
1215         return;
1216
1217 out_disable:
1218         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1219         /* Multiple disables should be harmless */
1220         if (dev_priv->display.fbc_enabled(crtc))
1221                 dev_priv->display.disable_fbc(dev);
1222 }
1223
1224 static int
1225 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1226 {
1227         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1228         u32 alignment;
1229         int ret;
1230
1231         switch (obj_priv->tiling_mode) {
1232         case I915_TILING_NONE:
1233                 alignment = 64 * 1024;
1234                 break;
1235         case I915_TILING_X:
1236                 /* pin() will align the object as required by fence */
1237                 alignment = 0;
1238                 break;
1239         case I915_TILING_Y:
1240                 /* FIXME: Is this true? */
1241                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1242                 return -EINVAL;
1243         default:
1244                 BUG();
1245         }
1246
1247         ret = i915_gem_object_pin(obj, alignment);
1248         if (ret != 0)
1249                 return ret;
1250
1251         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1252          * fence, whereas 965+ only requires a fence if using
1253          * framebuffer compression.  For simplicity, we always install
1254          * a fence as the cost is not that onerous.
1255          */
1256         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1257             obj_priv->tiling_mode != I915_TILING_NONE) {
1258                 ret = i915_gem_object_get_fence_reg(obj);
1259                 if (ret != 0) {
1260                         i915_gem_object_unpin(obj);
1261                         return ret;
1262                 }
1263         }
1264
1265         return 0;
1266 }
1267
1268 static int
1269 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1270                     struct drm_framebuffer *old_fb)
1271 {
1272         struct drm_device *dev = crtc->dev;
1273         struct drm_i915_private *dev_priv = dev->dev_private;
1274         struct drm_i915_master_private *master_priv;
1275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1276         struct intel_framebuffer *intel_fb;
1277         struct drm_i915_gem_object *obj_priv;
1278         struct drm_gem_object *obj;
1279         int pipe = intel_crtc->pipe;
1280         int plane = intel_crtc->plane;
1281         unsigned long Start, Offset;
1282         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1283         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1284         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1285         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1286         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1287         u32 dspcntr;
1288         int ret;
1289
1290         /* no fb bound */
1291         if (!crtc->fb) {
1292                 DRM_DEBUG_KMS("No FB bound\n");
1293                 return 0;
1294         }
1295
1296         switch (plane) {
1297         case 0:
1298         case 1:
1299                 break;
1300         default:
1301                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1302                 return -EINVAL;
1303         }
1304
1305         intel_fb = to_intel_framebuffer(crtc->fb);
1306         obj = intel_fb->obj;
1307         obj_priv = to_intel_bo(obj);
1308
1309         mutex_lock(&dev->struct_mutex);
1310         ret = intel_pin_and_fence_fb_obj(dev, obj);
1311         if (ret != 0) {
1312                 mutex_unlock(&dev->struct_mutex);
1313                 return ret;
1314         }
1315
1316         ret = i915_gem_object_set_to_display_plane(obj);
1317         if (ret != 0) {
1318                 i915_gem_object_unpin(obj);
1319                 mutex_unlock(&dev->struct_mutex);
1320                 return ret;
1321         }
1322
1323         dspcntr = I915_READ(dspcntr_reg);
1324         /* Mask out pixel format bits in case we change it */
1325         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1326         switch (crtc->fb->bits_per_pixel) {
1327         case 8:
1328                 dspcntr |= DISPPLANE_8BPP;
1329                 break;
1330         case 16:
1331                 if (crtc->fb->depth == 15)
1332                         dspcntr |= DISPPLANE_15_16BPP;
1333                 else
1334                         dspcntr |= DISPPLANE_16BPP;
1335                 break;
1336         case 24:
1337         case 32:
1338                 if (crtc->fb->depth == 30)
1339                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1340                 else
1341                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1342                 break;
1343         default:
1344                 DRM_ERROR("Unknown color depth\n");
1345                 i915_gem_object_unpin(obj);
1346                 mutex_unlock(&dev->struct_mutex);
1347                 return -EINVAL;
1348         }
1349         if (IS_I965G(dev)) {
1350                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1351                         dspcntr |= DISPPLANE_TILED;
1352                 else
1353                         dspcntr &= ~DISPPLANE_TILED;
1354         }
1355
1356         if (HAS_PCH_SPLIT(dev))
1357                 /* must disable */
1358                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1359
1360         I915_WRITE(dspcntr_reg, dspcntr);
1361
1362         Start = obj_priv->gtt_offset;
1363         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1364
1365         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1366         I915_WRITE(dspstride, crtc->fb->pitch);
1367         if (IS_I965G(dev)) {
1368                 I915_WRITE(dspbase, Offset);
1369                 I915_READ(dspbase);
1370                 I915_WRITE(dspsurf, Start);
1371                 I915_READ(dspsurf);
1372                 I915_WRITE(dsptileoff, (y << 16) | x);
1373         } else {
1374                 I915_WRITE(dspbase, Start + Offset);
1375                 I915_READ(dspbase);
1376         }
1377
1378         if ((IS_I965G(dev) || plane == 0))
1379                 intel_update_fbc(crtc, &crtc->mode);
1380
1381         intel_wait_for_vblank(dev);
1382
1383         if (old_fb) {
1384                 intel_fb = to_intel_framebuffer(old_fb);
1385                 obj_priv = to_intel_bo(intel_fb->obj);
1386                 i915_gem_object_unpin(intel_fb->obj);
1387         }
1388         intel_increase_pllclock(crtc, true);
1389
1390         mutex_unlock(&dev->struct_mutex);
1391
1392         if (!dev->primary->master)
1393                 return 0;
1394
1395         master_priv = dev->primary->master->driver_priv;
1396         if (!master_priv->sarea_priv)
1397                 return 0;
1398
1399         if (pipe) {
1400                 master_priv->sarea_priv->pipeB_x = x;
1401                 master_priv->sarea_priv->pipeB_y = y;
1402         } else {
1403                 master_priv->sarea_priv->pipeA_x = x;
1404                 master_priv->sarea_priv->pipeA_y = y;
1405         }
1406
1407         return 0;
1408 }
1409
1410 /* Disable the VGA plane that we never use */
1411 static void i915_disable_vga (struct drm_device *dev)
1412 {
1413         struct drm_i915_private *dev_priv = dev->dev_private;
1414         u8 sr1;
1415         u32 vga_reg;
1416
1417         if (HAS_PCH_SPLIT(dev))
1418                 vga_reg = CPU_VGACNTRL;
1419         else
1420                 vga_reg = VGACNTRL;
1421
1422         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1423                 return;
1424
1425         I915_WRITE8(VGA_SR_INDEX, 1);
1426         sr1 = I915_READ8(VGA_SR_DATA);
1427         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1428         udelay(100);
1429
1430         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1431 }
1432
1433 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1434 {
1435         struct drm_device *dev = crtc->dev;
1436         struct drm_i915_private *dev_priv = dev->dev_private;
1437         u32 dpa_ctl;
1438
1439         DRM_DEBUG_KMS("\n");
1440         dpa_ctl = I915_READ(DP_A);
1441         dpa_ctl &= ~DP_PLL_ENABLE;
1442         I915_WRITE(DP_A, dpa_ctl);
1443 }
1444
1445 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1446 {
1447         struct drm_device *dev = crtc->dev;
1448         struct drm_i915_private *dev_priv = dev->dev_private;
1449         u32 dpa_ctl;
1450
1451         dpa_ctl = I915_READ(DP_A);
1452         dpa_ctl |= DP_PLL_ENABLE;
1453         I915_WRITE(DP_A, dpa_ctl);
1454         udelay(200);
1455 }
1456
1457
1458 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1459 {
1460         struct drm_device *dev = crtc->dev;
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         u32 dpa_ctl;
1463
1464         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1465         dpa_ctl = I915_READ(DP_A);
1466         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1467
1468         if (clock < 200000) {
1469                 u32 temp;
1470                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1471                 /* workaround for 160Mhz:
1472                    1) program 0x4600c bits 15:0 = 0x8124
1473                    2) program 0x46010 bit 0 = 1
1474                    3) program 0x46034 bit 24 = 1
1475                    4) program 0x64000 bit 14 = 1
1476                    */
1477                 temp = I915_READ(0x4600c);
1478                 temp &= 0xffff0000;
1479                 I915_WRITE(0x4600c, temp | 0x8124);
1480
1481                 temp = I915_READ(0x46010);
1482                 I915_WRITE(0x46010, temp | 1);
1483
1484                 temp = I915_READ(0x46034);
1485                 I915_WRITE(0x46034, temp | (1 << 24));
1486         } else {
1487                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1488         }
1489         I915_WRITE(DP_A, dpa_ctl);
1490
1491         udelay(500);
1492 }
1493
1494 /* The FDI link training functions for ILK/Ibexpeak. */
1495 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1496 {
1497         struct drm_device *dev = crtc->dev;
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1500         int pipe = intel_crtc->pipe;
1501         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1502         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1503         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1504         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1505         u32 temp, tries = 0;
1506
1507         /* enable CPU FDI TX and PCH FDI RX */
1508         temp = I915_READ(fdi_tx_reg);
1509         temp |= FDI_TX_ENABLE;
1510         temp &= ~(7 << 19);
1511         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1512         temp &= ~FDI_LINK_TRAIN_NONE;
1513         temp |= FDI_LINK_TRAIN_PATTERN_1;
1514         I915_WRITE(fdi_tx_reg, temp);
1515         I915_READ(fdi_tx_reg);
1516
1517         temp = I915_READ(fdi_rx_reg);
1518         temp &= ~FDI_LINK_TRAIN_NONE;
1519         temp |= FDI_LINK_TRAIN_PATTERN_1;
1520         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1521         I915_READ(fdi_rx_reg);
1522         udelay(150);
1523
1524         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1525            for train result */
1526         temp = I915_READ(fdi_rx_imr_reg);
1527         temp &= ~FDI_RX_SYMBOL_LOCK;
1528         temp &= ~FDI_RX_BIT_LOCK;
1529         I915_WRITE(fdi_rx_imr_reg, temp);
1530         I915_READ(fdi_rx_imr_reg);
1531         udelay(150);
1532
1533         for (;;) {
1534                 temp = I915_READ(fdi_rx_iir_reg);
1535                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1536
1537                 if ((temp & FDI_RX_BIT_LOCK)) {
1538                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1539                         I915_WRITE(fdi_rx_iir_reg,
1540                                    temp | FDI_RX_BIT_LOCK);
1541                         break;
1542                 }
1543
1544                 tries++;
1545
1546                 if (tries > 5) {
1547                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1548                         break;
1549                 }
1550         }
1551
1552         /* Train 2 */
1553         temp = I915_READ(fdi_tx_reg);
1554         temp &= ~FDI_LINK_TRAIN_NONE;
1555         temp |= FDI_LINK_TRAIN_PATTERN_2;
1556         I915_WRITE(fdi_tx_reg, temp);
1557
1558         temp = I915_READ(fdi_rx_reg);
1559         temp &= ~FDI_LINK_TRAIN_NONE;
1560         temp |= FDI_LINK_TRAIN_PATTERN_2;
1561         I915_WRITE(fdi_rx_reg, temp);
1562         udelay(150);
1563
1564         tries = 0;
1565
1566         for (;;) {
1567                 temp = I915_READ(fdi_rx_iir_reg);
1568                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1569
1570                 if (temp & FDI_RX_SYMBOL_LOCK) {
1571                         I915_WRITE(fdi_rx_iir_reg,
1572                                    temp | FDI_RX_SYMBOL_LOCK);
1573                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1574                         break;
1575                 }
1576
1577                 tries++;
1578
1579                 if (tries > 5) {
1580                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1581                         break;
1582                 }
1583         }
1584
1585         DRM_DEBUG_KMS("FDI train done\n");
1586 }
1587
1588 static int snb_b_fdi_train_param [] = {
1589         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1590         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1591         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1592         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1593 };
1594
1595 /* The FDI link training functions for SNB/Cougarpoint. */
1596 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1597 {
1598         struct drm_device *dev = crtc->dev;
1599         struct drm_i915_private *dev_priv = dev->dev_private;
1600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1601         int pipe = intel_crtc->pipe;
1602         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1603         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1604         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1605         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1606         u32 temp, i;
1607
1608         /* enable CPU FDI TX and PCH FDI RX */
1609         temp = I915_READ(fdi_tx_reg);
1610         temp |= FDI_TX_ENABLE;
1611         temp &= ~(7 << 19);
1612         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1613         temp &= ~FDI_LINK_TRAIN_NONE;
1614         temp |= FDI_LINK_TRAIN_PATTERN_1;
1615         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1616         /* SNB-B */
1617         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1618         I915_WRITE(fdi_tx_reg, temp);
1619         I915_READ(fdi_tx_reg);
1620
1621         temp = I915_READ(fdi_rx_reg);
1622         if (HAS_PCH_CPT(dev)) {
1623                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1624                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1625         } else {
1626                 temp &= ~FDI_LINK_TRAIN_NONE;
1627                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1628         }
1629         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1630         I915_READ(fdi_rx_reg);
1631         udelay(150);
1632
1633         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1634            for train result */
1635         temp = I915_READ(fdi_rx_imr_reg);
1636         temp &= ~FDI_RX_SYMBOL_LOCK;
1637         temp &= ~FDI_RX_BIT_LOCK;
1638         I915_WRITE(fdi_rx_imr_reg, temp);
1639         I915_READ(fdi_rx_imr_reg);
1640         udelay(150);
1641
1642         for (i = 0; i < 4; i++ ) {
1643                 temp = I915_READ(fdi_tx_reg);
1644                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1645                 temp |= snb_b_fdi_train_param[i];
1646                 I915_WRITE(fdi_tx_reg, temp);
1647                 udelay(500);
1648
1649                 temp = I915_READ(fdi_rx_iir_reg);
1650                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1651
1652                 if (temp & FDI_RX_BIT_LOCK) {
1653                         I915_WRITE(fdi_rx_iir_reg,
1654                                    temp | FDI_RX_BIT_LOCK);
1655                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1656                         break;
1657                 }
1658         }
1659         if (i == 4)
1660                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1661
1662         /* Train 2 */
1663         temp = I915_READ(fdi_tx_reg);
1664         temp &= ~FDI_LINK_TRAIN_NONE;
1665         temp |= FDI_LINK_TRAIN_PATTERN_2;
1666         if (IS_GEN6(dev)) {
1667                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1668                 /* SNB-B */
1669                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1670         }
1671         I915_WRITE(fdi_tx_reg, temp);
1672
1673         temp = I915_READ(fdi_rx_reg);
1674         if (HAS_PCH_CPT(dev)) {
1675                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1676                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1677         } else {
1678                 temp &= ~FDI_LINK_TRAIN_NONE;
1679                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1680         }
1681         I915_WRITE(fdi_rx_reg, temp);
1682         udelay(150);
1683
1684         for (i = 0; i < 4; i++ ) {
1685                 temp = I915_READ(fdi_tx_reg);
1686                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1687                 temp |= snb_b_fdi_train_param[i];
1688                 I915_WRITE(fdi_tx_reg, temp);
1689                 udelay(500);
1690
1691                 temp = I915_READ(fdi_rx_iir_reg);
1692                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1693
1694                 if (temp & FDI_RX_SYMBOL_LOCK) {
1695                         I915_WRITE(fdi_rx_iir_reg,
1696                                    temp | FDI_RX_SYMBOL_LOCK);
1697                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1698                         break;
1699                 }
1700         }
1701         if (i == 4)
1702                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1703
1704         DRM_DEBUG_KMS("FDI train done.\n");
1705 }
1706
1707 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1708 {
1709         struct drm_device *dev = crtc->dev;
1710         struct drm_i915_private *dev_priv = dev->dev_private;
1711         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1712         int pipe = intel_crtc->pipe;
1713         int plane = intel_crtc->plane;
1714         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1715         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1716         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1717         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1718         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1719         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1720         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1721         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1722         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1723         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1724         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1725         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1726         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1727         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1728         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1729         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1730         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1731         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1732         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1733         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1734         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1735         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1736         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1737         u32 temp;
1738         int n;
1739         u32 pipe_bpc;
1740
1741         temp = I915_READ(pipeconf_reg);
1742         pipe_bpc = temp & PIPE_BPC_MASK;
1743
1744         /* XXX: When our outputs are all unaware of DPMS modes other than off
1745          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1746          */
1747         switch (mode) {
1748         case DRM_MODE_DPMS_ON:
1749         case DRM_MODE_DPMS_STANDBY:
1750         case DRM_MODE_DPMS_SUSPEND:
1751                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1752
1753                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1754                         temp = I915_READ(PCH_LVDS);
1755                         if ((temp & LVDS_PORT_EN) == 0) {
1756                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1757                                 POSTING_READ(PCH_LVDS);
1758                         }
1759                 }
1760
1761                 if (HAS_eDP) {
1762                         /* enable eDP PLL */
1763                         ironlake_enable_pll_edp(crtc);
1764                 } else {
1765
1766                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1767                         temp = I915_READ(fdi_rx_reg);
1768                         /*
1769                          * make the BPC in FDI Rx be consistent with that in
1770                          * pipeconf reg.
1771                          */
1772                         temp &= ~(0x7 << 16);
1773                         temp |= (pipe_bpc << 11);
1774                         temp &= ~(7 << 19);
1775                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1776                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1777                         I915_READ(fdi_rx_reg);
1778                         udelay(200);
1779
1780                         /* Switch from Rawclk to PCDclk */
1781                         temp = I915_READ(fdi_rx_reg);
1782                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1783                         I915_READ(fdi_rx_reg);
1784                         udelay(200);
1785
1786                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1787                         temp = I915_READ(fdi_tx_reg);
1788                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1789                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1790                                 I915_READ(fdi_tx_reg);
1791                                 udelay(100);
1792                         }
1793                 }
1794
1795                 /* Enable panel fitting for LVDS */
1796                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1797                         temp = I915_READ(pf_ctl_reg);
1798                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1799
1800                         /* currently full aspect */
1801                         I915_WRITE(pf_win_pos, 0);
1802
1803                         I915_WRITE(pf_win_size,
1804                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1805                                    (dev_priv->panel_fixed_mode->vdisplay));
1806                 }
1807
1808                 /* Enable CPU pipe */
1809                 temp = I915_READ(pipeconf_reg);
1810                 if ((temp & PIPEACONF_ENABLE) == 0) {
1811                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1812                         I915_READ(pipeconf_reg);
1813                         udelay(100);
1814                 }
1815
1816                 /* configure and enable CPU plane */
1817                 temp = I915_READ(dspcntr_reg);
1818                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1819                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1820                         /* Flush the plane changes */
1821                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1822                 }
1823
1824                 if (!HAS_eDP) {
1825                         /* For PCH output, training FDI link */
1826                         if (IS_GEN6(dev))
1827                                 gen6_fdi_link_train(crtc);
1828                         else
1829                                 ironlake_fdi_link_train(crtc);
1830
1831                         /* enable PCH DPLL */
1832                         temp = I915_READ(pch_dpll_reg);
1833                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1834                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1835                                 I915_READ(pch_dpll_reg);
1836                         }
1837                         udelay(200);
1838
1839                         if (HAS_PCH_CPT(dev)) {
1840                                 /* Be sure PCH DPLL SEL is set */
1841                                 temp = I915_READ(PCH_DPLL_SEL);
1842                                 if (trans_dpll_sel == 0 &&
1843                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1844                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1845                                 else if (trans_dpll_sel == 1 &&
1846                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1847                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1848                                 I915_WRITE(PCH_DPLL_SEL, temp);
1849                                 I915_READ(PCH_DPLL_SEL);
1850                         }
1851
1852                         /* set transcoder timing */
1853                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1854                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1855                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1856
1857                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1858                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1859                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1860
1861                         /* enable normal train */
1862                         temp = I915_READ(fdi_tx_reg);
1863                         temp &= ~FDI_LINK_TRAIN_NONE;
1864                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1865                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1866                         I915_READ(fdi_tx_reg);
1867
1868                         temp = I915_READ(fdi_rx_reg);
1869                         if (HAS_PCH_CPT(dev)) {
1870                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1871                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1872                         } else {
1873                                 temp &= ~FDI_LINK_TRAIN_NONE;
1874                                 temp |= FDI_LINK_TRAIN_NONE;
1875                         }
1876                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1877                         I915_READ(fdi_rx_reg);
1878
1879                         /* wait one idle pattern time */
1880                         udelay(100);
1881
1882                         /* For PCH DP, enable TRANS_DP_CTL */
1883                         if (HAS_PCH_CPT(dev) &&
1884                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1885                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1886                                 int reg;
1887
1888                                 reg = I915_READ(trans_dp_ctl);
1889                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
1890                                 reg = TRANS_DP_OUTPUT_ENABLE |
1891                                       TRANS_DP_ENH_FRAMING |
1892                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
1893                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
1894
1895                                 switch (intel_trans_dp_port_sel(crtc)) {
1896                                 case PCH_DP_B:
1897                                         reg |= TRANS_DP_PORT_SEL_B;
1898                                         break;
1899                                 case PCH_DP_C:
1900                                         reg |= TRANS_DP_PORT_SEL_C;
1901                                         break;
1902                                 case PCH_DP_D:
1903                                         reg |= TRANS_DP_PORT_SEL_D;
1904                                         break;
1905                                 default:
1906                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1907                                         reg |= TRANS_DP_PORT_SEL_B;
1908                                         break;
1909                                 }
1910
1911                                 I915_WRITE(trans_dp_ctl, reg);
1912                                 POSTING_READ(trans_dp_ctl);
1913                         }
1914
1915                         /* enable PCH transcoder */
1916                         temp = I915_READ(transconf_reg);
1917                         /*
1918                          * make the BPC in transcoder be consistent with
1919                          * that in pipeconf reg.
1920                          */
1921                         temp &= ~PIPE_BPC_MASK;
1922                         temp |= pipe_bpc;
1923                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1924                         I915_READ(transconf_reg);
1925
1926                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1927                                 ;
1928
1929                 }
1930
1931                 intel_crtc_load_lut(crtc);
1932
1933         break;
1934         case DRM_MODE_DPMS_OFF:
1935                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1936
1937                 drm_vblank_off(dev, pipe);
1938                 /* Disable display plane */
1939                 temp = I915_READ(dspcntr_reg);
1940                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1941                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1942                         /* Flush the plane changes */
1943                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1944                         I915_READ(dspbase_reg);
1945                 }
1946
1947                 i915_disable_vga(dev);
1948
1949                 /* disable cpu pipe, disable after all planes disabled */
1950                 temp = I915_READ(pipeconf_reg);
1951                 if ((temp & PIPEACONF_ENABLE) != 0) {
1952                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1953                         I915_READ(pipeconf_reg);
1954                         n = 0;
1955                         /* wait for cpu pipe off, pipe state */
1956                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1957                                 n++;
1958                                 if (n < 60) {
1959                                         udelay(500);
1960                                         continue;
1961                                 } else {
1962                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1963                                                                 pipe);
1964                                         break;
1965                                 }
1966                         }
1967                 } else
1968                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1969
1970                 udelay(100);
1971
1972                 /* Disable PF */
1973                 temp = I915_READ(pf_ctl_reg);
1974                 if ((temp & PF_ENABLE) != 0) {
1975                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1976                         I915_READ(pf_ctl_reg);
1977                 }
1978                 I915_WRITE(pf_win_size, 0);
1979                 POSTING_READ(pf_win_size);
1980
1981
1982                 /* disable CPU FDI tx and PCH FDI rx */
1983                 temp = I915_READ(fdi_tx_reg);
1984                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1985                 I915_READ(fdi_tx_reg);
1986
1987                 temp = I915_READ(fdi_rx_reg);
1988                 /* BPC in FDI rx is consistent with that in pipeconf */
1989                 temp &= ~(0x07 << 16);
1990                 temp |= (pipe_bpc << 11);
1991                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1992                 I915_READ(fdi_rx_reg);
1993
1994                 udelay(100);
1995
1996                 /* still set train pattern 1 */
1997                 temp = I915_READ(fdi_tx_reg);
1998                 temp &= ~FDI_LINK_TRAIN_NONE;
1999                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2000                 I915_WRITE(fdi_tx_reg, temp);
2001                 POSTING_READ(fdi_tx_reg);
2002
2003                 temp = I915_READ(fdi_rx_reg);
2004                 if (HAS_PCH_CPT(dev)) {
2005                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2006                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2007                 } else {
2008                         temp &= ~FDI_LINK_TRAIN_NONE;
2009                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2010                 }
2011                 I915_WRITE(fdi_rx_reg, temp);
2012                 POSTING_READ(fdi_rx_reg);
2013
2014                 udelay(100);
2015
2016                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2017                         temp = I915_READ(PCH_LVDS);
2018                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2019                         I915_READ(PCH_LVDS);
2020                         udelay(100);
2021                 }
2022
2023                 /* disable PCH transcoder */
2024                 temp = I915_READ(transconf_reg);
2025                 if ((temp & TRANS_ENABLE) != 0) {
2026                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2027                         I915_READ(transconf_reg);
2028                         n = 0;
2029                         /* wait for PCH transcoder off, transcoder state */
2030                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2031                                 n++;
2032                                 if (n < 60) {
2033                                         udelay(500);
2034                                         continue;
2035                                 } else {
2036                                         DRM_DEBUG_KMS("transcoder %d off "
2037                                                         "delay\n", pipe);
2038                                         break;
2039                                 }
2040                         }
2041                 }
2042
2043                 temp = I915_READ(transconf_reg);
2044                 /* BPC in transcoder is consistent with that in pipeconf */
2045                 temp &= ~PIPE_BPC_MASK;
2046                 temp |= pipe_bpc;
2047                 I915_WRITE(transconf_reg, temp);
2048                 I915_READ(transconf_reg);
2049                 udelay(100);
2050
2051                 if (HAS_PCH_CPT(dev)) {
2052                         /* disable TRANS_DP_CTL */
2053                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2054                         int reg;
2055
2056                         reg = I915_READ(trans_dp_ctl);
2057                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2058                         I915_WRITE(trans_dp_ctl, reg);
2059                         POSTING_READ(trans_dp_ctl);
2060
2061                         /* disable DPLL_SEL */
2062                         temp = I915_READ(PCH_DPLL_SEL);
2063                         if (trans_dpll_sel == 0)
2064                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2065                         else
2066                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2067                         I915_WRITE(PCH_DPLL_SEL, temp);
2068                         I915_READ(PCH_DPLL_SEL);
2069
2070                 }
2071
2072                 /* disable PCH DPLL */
2073                 temp = I915_READ(pch_dpll_reg);
2074                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2075                 I915_READ(pch_dpll_reg);
2076
2077                 if (HAS_eDP) {
2078                         ironlake_disable_pll_edp(crtc);
2079                 }
2080
2081                 /* Switch from PCDclk to Rawclk */
2082                 temp = I915_READ(fdi_rx_reg);
2083                 temp &= ~FDI_SEL_PCDCLK;
2084                 I915_WRITE(fdi_rx_reg, temp);
2085                 I915_READ(fdi_rx_reg);
2086
2087                 /* Disable CPU FDI TX PLL */
2088                 temp = I915_READ(fdi_tx_reg);
2089                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2090                 I915_READ(fdi_tx_reg);
2091                 udelay(100);
2092
2093                 temp = I915_READ(fdi_rx_reg);
2094                 temp &= ~FDI_RX_PLL_ENABLE;
2095                 I915_WRITE(fdi_rx_reg, temp);
2096                 I915_READ(fdi_rx_reg);
2097
2098                 /* Wait for the clocks to turn off. */
2099                 udelay(100);
2100                 break;
2101         }
2102 }
2103
2104 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2105 {
2106         struct intel_overlay *overlay;
2107         int ret;
2108
2109         if (!enable && intel_crtc->overlay) {
2110                 overlay = intel_crtc->overlay;
2111                 mutex_lock(&overlay->dev->struct_mutex);
2112                 for (;;) {
2113                         ret = intel_overlay_switch_off(overlay);
2114                         if (ret == 0)
2115                                 break;
2116
2117                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2118                         if (ret != 0) {
2119                                 /* overlay doesn't react anymore. Usually
2120                                  * results in a black screen and an unkillable
2121                                  * X server. */
2122                                 BUG();
2123                                 overlay->hw_wedged = HW_WEDGED;
2124                                 break;
2125                         }
2126                 }
2127                 mutex_unlock(&overlay->dev->struct_mutex);
2128         }
2129         /* Let userspace switch the overlay on again. In most cases userspace
2130          * has to recompute where to put it anyway. */
2131
2132         return;
2133 }
2134
2135 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2136 {
2137         struct drm_device *dev = crtc->dev;
2138         struct drm_i915_private *dev_priv = dev->dev_private;
2139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140         int pipe = intel_crtc->pipe;
2141         int plane = intel_crtc->plane;
2142         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2143         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2144         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2145         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2146         u32 temp;
2147
2148         /* XXX: When our outputs are all unaware of DPMS modes other than off
2149          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2150          */
2151         switch (mode) {
2152         case DRM_MODE_DPMS_ON:
2153         case DRM_MODE_DPMS_STANDBY:
2154         case DRM_MODE_DPMS_SUSPEND:
2155                 intel_update_watermarks(dev);
2156
2157                 /* Enable the DPLL */
2158                 temp = I915_READ(dpll_reg);
2159                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2160                         I915_WRITE(dpll_reg, temp);
2161                         I915_READ(dpll_reg);
2162                         /* Wait for the clocks to stabilize. */
2163                         udelay(150);
2164                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2165                         I915_READ(dpll_reg);
2166                         /* Wait for the clocks to stabilize. */
2167                         udelay(150);
2168                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2169                         I915_READ(dpll_reg);
2170                         /* Wait for the clocks to stabilize. */
2171                         udelay(150);
2172                 }
2173
2174                 /* Enable the pipe */
2175                 temp = I915_READ(pipeconf_reg);
2176                 if ((temp & PIPEACONF_ENABLE) == 0)
2177                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2178
2179                 /* Enable the plane */
2180                 temp = I915_READ(dspcntr_reg);
2181                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2182                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2183                         /* Flush the plane changes */
2184                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2185                 }
2186
2187                 intel_crtc_load_lut(crtc);
2188
2189                 if ((IS_I965G(dev) || plane == 0))
2190                         intel_update_fbc(crtc, &crtc->mode);
2191
2192                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2193                 intel_crtc_dpms_overlay(intel_crtc, true);
2194         break;
2195         case DRM_MODE_DPMS_OFF:
2196                 intel_update_watermarks(dev);
2197
2198                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2199                 intel_crtc_dpms_overlay(intel_crtc, false);
2200                 drm_vblank_off(dev, pipe);
2201
2202                 if (dev_priv->cfb_plane == plane &&
2203                     dev_priv->display.disable_fbc)
2204                         dev_priv->display.disable_fbc(dev);
2205
2206                 /* Disable the VGA plane that we never use */
2207                 i915_disable_vga(dev);
2208
2209                 /* Disable display plane */
2210                 temp = I915_READ(dspcntr_reg);
2211                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2212                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2213                         /* Flush the plane changes */
2214                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2215                         I915_READ(dspbase_reg);
2216                 }
2217
2218                 if (!IS_I9XX(dev)) {
2219                         /* Wait for vblank for the disable to take effect */
2220                         intel_wait_for_vblank(dev);
2221                 }
2222
2223                 /* Next, disable display pipes */
2224                 temp = I915_READ(pipeconf_reg);
2225                 if ((temp & PIPEACONF_ENABLE) != 0) {
2226                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2227                         I915_READ(pipeconf_reg);
2228                 }
2229
2230                 /* Wait for vblank for the disable to take effect. */
2231                 intel_wait_for_vblank(dev);
2232
2233                 temp = I915_READ(dpll_reg);
2234                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2235                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2236                         I915_READ(dpll_reg);
2237                 }
2238
2239                 /* Wait for the clocks to turn off. */
2240                 udelay(150);
2241                 break;
2242         }
2243 }
2244
2245 /**
2246  * Sets the power management mode of the pipe and plane.
2247  *
2248  * This code should probably grow support for turning the cursor off and back
2249  * on appropriately at the same time as we're turning the pipe off/on.
2250  */
2251 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2252 {
2253         struct drm_device *dev = crtc->dev;
2254         struct drm_i915_private *dev_priv = dev->dev_private;
2255         struct drm_i915_master_private *master_priv;
2256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2257         int pipe = intel_crtc->pipe;
2258         bool enabled;
2259
2260         dev_priv->display.dpms(crtc, mode);
2261
2262         intel_crtc->dpms_mode = mode;
2263
2264         if (!dev->primary->master)
2265                 return;
2266
2267         master_priv = dev->primary->master->driver_priv;
2268         if (!master_priv->sarea_priv)
2269                 return;
2270
2271         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2272
2273         switch (pipe) {
2274         case 0:
2275                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2276                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2277                 break;
2278         case 1:
2279                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2280                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2281                 break;
2282         default:
2283                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2284                 break;
2285         }
2286 }
2287
2288 static void intel_crtc_prepare (struct drm_crtc *crtc)
2289 {
2290         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2291         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2292 }
2293
2294 static void intel_crtc_commit (struct drm_crtc *crtc)
2295 {
2296         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2297         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2298 }
2299
2300 void intel_encoder_prepare (struct drm_encoder *encoder)
2301 {
2302         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2303         /* lvds has its own version of prepare see intel_lvds_prepare */
2304         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2305 }
2306
2307 void intel_encoder_commit (struct drm_encoder *encoder)
2308 {
2309         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2310         /* lvds has its own version of commit see intel_lvds_commit */
2311         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2312 }
2313
2314 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2315                                   struct drm_display_mode *mode,
2316                                   struct drm_display_mode *adjusted_mode)
2317 {
2318         struct drm_device *dev = crtc->dev;
2319         if (HAS_PCH_SPLIT(dev)) {
2320                 /* FDI link clock is fixed at 2.7G */
2321                 if (mode->clock * 3 > 27000 * 4)
2322                         return MODE_CLOCK_HIGH;
2323         }
2324         return true;
2325 }
2326
2327 static int i945_get_display_clock_speed(struct drm_device *dev)
2328 {
2329         return 400000;
2330 }
2331
2332 static int i915_get_display_clock_speed(struct drm_device *dev)
2333 {
2334         return 333000;
2335 }
2336
2337 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2338 {
2339         return 200000;
2340 }
2341
2342 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2343 {
2344         u16 gcfgc = 0;
2345
2346         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2347
2348         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2349                 return 133000;
2350         else {
2351                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2352                 case GC_DISPLAY_CLOCK_333_MHZ:
2353                         return 333000;
2354                 default:
2355                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2356                         return 190000;
2357                 }
2358         }
2359 }
2360
2361 static int i865_get_display_clock_speed(struct drm_device *dev)
2362 {
2363         return 266000;
2364 }
2365
2366 static int i855_get_display_clock_speed(struct drm_device *dev)
2367 {
2368         u16 hpllcc = 0;
2369         /* Assume that the hardware is in the high speed state.  This
2370          * should be the default.
2371          */
2372         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2373         case GC_CLOCK_133_200:
2374         case GC_CLOCK_100_200:
2375                 return 200000;
2376         case GC_CLOCK_166_250:
2377                 return 250000;
2378         case GC_CLOCK_100_133:
2379                 return 133000;
2380         }
2381
2382         /* Shouldn't happen */
2383         return 0;
2384 }
2385
2386 static int i830_get_display_clock_speed(struct drm_device *dev)
2387 {
2388         return 133000;
2389 }
2390
2391 /**
2392  * Return the pipe currently connected to the panel fitter,
2393  * or -1 if the panel fitter is not present or not in use
2394  */
2395 int intel_panel_fitter_pipe (struct drm_device *dev)
2396 {
2397         struct drm_i915_private *dev_priv = dev->dev_private;
2398         u32  pfit_control;
2399
2400         /* i830 doesn't have a panel fitter */
2401         if (IS_I830(dev))
2402                 return -1;
2403
2404         pfit_control = I915_READ(PFIT_CONTROL);
2405
2406         /* See if the panel fitter is in use */
2407         if ((pfit_control & PFIT_ENABLE) == 0)
2408                 return -1;
2409
2410         /* 965 can place panel fitter on either pipe */
2411         if (IS_I965G(dev))
2412                 return (pfit_control >> 29) & 0x3;
2413
2414         /* older chips can only use pipe 1 */
2415         return 1;
2416 }
2417
2418 struct fdi_m_n {
2419         u32        tu;
2420         u32        gmch_m;
2421         u32        gmch_n;
2422         u32        link_m;
2423         u32        link_n;
2424 };
2425
2426 static void
2427 fdi_reduce_ratio(u32 *num, u32 *den)
2428 {
2429         while (*num > 0xffffff || *den > 0xffffff) {
2430                 *num >>= 1;
2431                 *den >>= 1;
2432         }
2433 }
2434
2435 #define DATA_N 0x800000
2436 #define LINK_N 0x80000
2437
2438 static void
2439 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2440                      int link_clock, struct fdi_m_n *m_n)
2441 {
2442         u64 temp;
2443
2444         m_n->tu = 64; /* default size */
2445
2446         temp = (u64) DATA_N * pixel_clock;
2447         temp = div_u64(temp, link_clock);
2448         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2449         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2450         m_n->gmch_n = DATA_N;
2451         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2452
2453         temp = (u64) LINK_N * pixel_clock;
2454         m_n->link_m = div_u64(temp, link_clock);
2455         m_n->link_n = LINK_N;
2456         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2457 }
2458
2459
2460 struct intel_watermark_params {
2461         unsigned long fifo_size;
2462         unsigned long max_wm;
2463         unsigned long default_wm;
2464         unsigned long guard_size;
2465         unsigned long cacheline_size;
2466 };
2467
2468 /* Pineview has different values for various configs */
2469 static struct intel_watermark_params pineview_display_wm = {
2470         PINEVIEW_DISPLAY_FIFO,
2471         PINEVIEW_MAX_WM,
2472         PINEVIEW_DFT_WM,
2473         PINEVIEW_GUARD_WM,
2474         PINEVIEW_FIFO_LINE_SIZE
2475 };
2476 static struct intel_watermark_params pineview_display_hplloff_wm = {
2477         PINEVIEW_DISPLAY_FIFO,
2478         PINEVIEW_MAX_WM,
2479         PINEVIEW_DFT_HPLLOFF_WM,
2480         PINEVIEW_GUARD_WM,
2481         PINEVIEW_FIFO_LINE_SIZE
2482 };
2483 static struct intel_watermark_params pineview_cursor_wm = {
2484         PINEVIEW_CURSOR_FIFO,
2485         PINEVIEW_CURSOR_MAX_WM,
2486         PINEVIEW_CURSOR_DFT_WM,
2487         PINEVIEW_CURSOR_GUARD_WM,
2488         PINEVIEW_FIFO_LINE_SIZE,
2489 };
2490 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2491         PINEVIEW_CURSOR_FIFO,
2492         PINEVIEW_CURSOR_MAX_WM,
2493         PINEVIEW_CURSOR_DFT_WM,
2494         PINEVIEW_CURSOR_GUARD_WM,
2495         PINEVIEW_FIFO_LINE_SIZE
2496 };
2497 static struct intel_watermark_params g4x_wm_info = {
2498         G4X_FIFO_SIZE,
2499         G4X_MAX_WM,
2500         G4X_MAX_WM,
2501         2,
2502         G4X_FIFO_LINE_SIZE,
2503 };
2504 static struct intel_watermark_params i945_wm_info = {
2505         I945_FIFO_SIZE,
2506         I915_MAX_WM,
2507         1,
2508         2,
2509         I915_FIFO_LINE_SIZE
2510 };
2511 static struct intel_watermark_params i915_wm_info = {
2512         I915_FIFO_SIZE,
2513         I915_MAX_WM,
2514         1,
2515         2,
2516         I915_FIFO_LINE_SIZE
2517 };
2518 static struct intel_watermark_params i855_wm_info = {
2519         I855GM_FIFO_SIZE,
2520         I915_MAX_WM,
2521         1,
2522         2,
2523         I830_FIFO_LINE_SIZE
2524 };
2525 static struct intel_watermark_params i830_wm_info = {
2526         I830_FIFO_SIZE,
2527         I915_MAX_WM,
2528         1,
2529         2,
2530         I830_FIFO_LINE_SIZE
2531 };
2532
2533 static struct intel_watermark_params ironlake_display_wm_info = {
2534         ILK_DISPLAY_FIFO,
2535         ILK_DISPLAY_MAXWM,
2536         ILK_DISPLAY_DFTWM,
2537         2,
2538         ILK_FIFO_LINE_SIZE
2539 };
2540
2541 static struct intel_watermark_params ironlake_display_srwm_info = {
2542         ILK_DISPLAY_SR_FIFO,
2543         ILK_DISPLAY_MAX_SRWM,
2544         ILK_DISPLAY_DFT_SRWM,
2545         2,
2546         ILK_FIFO_LINE_SIZE
2547 };
2548
2549 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2550         ILK_CURSOR_SR_FIFO,
2551         ILK_CURSOR_MAX_SRWM,
2552         ILK_CURSOR_DFT_SRWM,
2553         2,
2554         ILK_FIFO_LINE_SIZE
2555 };
2556
2557 /**
2558  * intel_calculate_wm - calculate watermark level
2559  * @clock_in_khz: pixel clock
2560  * @wm: chip FIFO params
2561  * @pixel_size: display pixel size
2562  * @latency_ns: memory latency for the platform
2563  *
2564  * Calculate the watermark level (the level at which the display plane will
2565  * start fetching from memory again).  Each chip has a different display
2566  * FIFO size and allocation, so the caller needs to figure that out and pass
2567  * in the correct intel_watermark_params structure.
2568  *
2569  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2570  * on the pixel size.  When it reaches the watermark level, it'll start
2571  * fetching FIFO line sized based chunks from memory until the FIFO fills
2572  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2573  * will occur, and a display engine hang could result.
2574  */
2575 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2576                                         struct intel_watermark_params *wm,
2577                                         int pixel_size,
2578                                         unsigned long latency_ns)
2579 {
2580         long entries_required, wm_size;
2581
2582         /*
2583          * Note: we need to make sure we don't overflow for various clock &
2584          * latency values.
2585          * clocks go from a few thousand to several hundred thousand.
2586          * latency is usually a few thousand
2587          */
2588         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2589                 1000;
2590         entries_required /= wm->cacheline_size;
2591
2592         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2593
2594         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2595
2596         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2597
2598         /* Don't promote wm_size to unsigned... */
2599         if (wm_size > (long)wm->max_wm)
2600                 wm_size = wm->max_wm;
2601         if (wm_size <= 0)
2602                 wm_size = wm->default_wm;
2603         return wm_size;
2604 }
2605
2606 struct cxsr_latency {
2607         int is_desktop;
2608         unsigned long fsb_freq;
2609         unsigned long mem_freq;
2610         unsigned long display_sr;
2611         unsigned long display_hpll_disable;
2612         unsigned long cursor_sr;
2613         unsigned long cursor_hpll_disable;
2614 };
2615
2616 static struct cxsr_latency cxsr_latency_table[] = {
2617         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2618         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2619         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2620
2621         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2622         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2623         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2624
2625         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2626         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2627         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2628
2629         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2630         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2631         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2632
2633         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2634         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2635         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2636
2637         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2638         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2639         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2640 };
2641
2642 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2643                                                    int mem)
2644 {
2645         int i;
2646         struct cxsr_latency *latency;
2647
2648         if (fsb == 0 || mem == 0)
2649                 return NULL;
2650
2651         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2652                 latency = &cxsr_latency_table[i];
2653                 if (is_desktop == latency->is_desktop &&
2654                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2655                         return latency;
2656         }
2657
2658         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2659
2660         return NULL;
2661 }
2662
2663 static void pineview_disable_cxsr(struct drm_device *dev)
2664 {
2665         struct drm_i915_private *dev_priv = dev->dev_private;
2666         u32 reg;
2667
2668         /* deactivate cxsr */
2669         reg = I915_READ(DSPFW3);
2670         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2671         I915_WRITE(DSPFW3, reg);
2672         DRM_INFO("Big FIFO is disabled\n");
2673 }
2674
2675 /*
2676  * Latency for FIFO fetches is dependent on several factors:
2677  *   - memory configuration (speed, channels)
2678  *   - chipset
2679  *   - current MCH state
2680  * It can be fairly high in some situations, so here we assume a fairly
2681  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2682  * set this value too high, the FIFO will fetch frequently to stay full)
2683  * and power consumption (set it too low to save power and we might see
2684  * FIFO underruns and display "flicker").
2685  *
2686  * A value of 5us seems to be a good balance; safe for very low end
2687  * platforms but not overly aggressive on lower latency configs.
2688  */
2689 static const int latency_ns = 5000;
2690
2691 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2692 {
2693         struct drm_i915_private *dev_priv = dev->dev_private;
2694         uint32_t dsparb = I915_READ(DSPARB);
2695         int size;
2696
2697         if (plane == 0)
2698                 size = dsparb & 0x7f;
2699         else
2700                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2701                         (dsparb & 0x7f);
2702
2703         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2704                         plane ? "B" : "A", size);
2705
2706         return size;
2707 }
2708
2709 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2710 {
2711         struct drm_i915_private *dev_priv = dev->dev_private;
2712         uint32_t dsparb = I915_READ(DSPARB);
2713         int size;
2714
2715         if (plane == 0)
2716                 size = dsparb & 0x1ff;
2717         else
2718                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2719                         (dsparb & 0x1ff);
2720         size >>= 1; /* Convert to cachelines */
2721
2722         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2723                         plane ? "B" : "A", size);
2724
2725         return size;
2726 }
2727
2728 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2729 {
2730         struct drm_i915_private *dev_priv = dev->dev_private;
2731         uint32_t dsparb = I915_READ(DSPARB);
2732         int size;
2733
2734         size = dsparb & 0x7f;
2735         size >>= 2; /* Convert to cachelines */
2736
2737         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2738                         plane ? "B" : "A",
2739                   size);
2740
2741         return size;
2742 }
2743
2744 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2745 {
2746         struct drm_i915_private *dev_priv = dev->dev_private;
2747         uint32_t dsparb = I915_READ(DSPARB);
2748         int size;
2749
2750         size = dsparb & 0x7f;
2751         size >>= 1; /* Convert to cachelines */
2752
2753         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2754                         plane ? "B" : "A", size);
2755
2756         return size;
2757 }
2758
2759 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2760                           int planeb_clock, int sr_hdisplay, int pixel_size)
2761 {
2762         struct drm_i915_private *dev_priv = dev->dev_private;
2763         u32 reg;
2764         unsigned long wm;
2765         struct cxsr_latency *latency;
2766         int sr_clock;
2767
2768         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2769                                          dev_priv->mem_freq);
2770         if (!latency) {
2771                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2772                 pineview_disable_cxsr(dev);
2773                 return;
2774         }
2775
2776         if (!planea_clock || !planeb_clock) {
2777                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2778
2779                 /* Display SR */
2780                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2781                                         pixel_size, latency->display_sr);
2782                 reg = I915_READ(DSPFW1);
2783                 reg &= ~DSPFW_SR_MASK;
2784                 reg |= wm << DSPFW_SR_SHIFT;
2785                 I915_WRITE(DSPFW1, reg);
2786                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2787
2788                 /* cursor SR */
2789                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2790                                         pixel_size, latency->cursor_sr);
2791                 reg = I915_READ(DSPFW3);
2792                 reg &= ~DSPFW_CURSOR_SR_MASK;
2793                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2794                 I915_WRITE(DSPFW3, reg);
2795
2796                 /* Display HPLL off SR */
2797                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2798                                         pixel_size, latency->display_hpll_disable);
2799                 reg = I915_READ(DSPFW3);
2800                 reg &= ~DSPFW_HPLL_SR_MASK;
2801                 reg |= wm & DSPFW_HPLL_SR_MASK;
2802                 I915_WRITE(DSPFW3, reg);
2803
2804                 /* cursor HPLL off SR */
2805                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2806                                         pixel_size, latency->cursor_hpll_disable);
2807                 reg = I915_READ(DSPFW3);
2808                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2809                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2810                 I915_WRITE(DSPFW3, reg);
2811                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2812
2813                 /* activate cxsr */
2814                 reg = I915_READ(DSPFW3);
2815                 reg |= PINEVIEW_SELF_REFRESH_EN;
2816                 I915_WRITE(DSPFW3, reg);
2817                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2818         } else {
2819                 pineview_disable_cxsr(dev);
2820                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2821         }
2822 }
2823
2824 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2825                           int planeb_clock, int sr_hdisplay, int pixel_size)
2826 {
2827         struct drm_i915_private *dev_priv = dev->dev_private;
2828         int total_size, cacheline_size;
2829         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2830         struct intel_watermark_params planea_params, planeb_params;
2831         unsigned long line_time_us;
2832         int sr_clock, sr_entries = 0, entries_required;
2833
2834         /* Create copies of the base settings for each pipe */
2835         planea_params = planeb_params = g4x_wm_info;
2836
2837         /* Grab a couple of global values before we overwrite them */
2838         total_size = planea_params.fifo_size;
2839         cacheline_size = planea_params.cacheline_size;
2840
2841         /*
2842          * Note: we need to make sure we don't overflow for various clock &
2843          * latency values.
2844          * clocks go from a few thousand to several hundred thousand.
2845          * latency is usually a few thousand
2846          */
2847         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2848                 1000;
2849         entries_required /= G4X_FIFO_LINE_SIZE;
2850         planea_wm = entries_required + planea_params.guard_size;
2851
2852         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2853                 1000;
2854         entries_required /= G4X_FIFO_LINE_SIZE;
2855         planeb_wm = entries_required + planeb_params.guard_size;
2856
2857         cursora_wm = cursorb_wm = 16;
2858         cursor_sr = 32;
2859
2860         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2861
2862         /* Calc sr entries for one plane configs */
2863         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2864                 /* self-refresh has much higher latency */
2865                 static const int sr_latency_ns = 12000;
2866
2867                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2868                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2869
2870                 /* Use ns/us then divide to preserve precision */
2871                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2872                               pixel_size * sr_hdisplay) / 1000;
2873                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2874                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2875                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2876         } else {
2877                 /* Turn off self refresh if both pipes are enabled */
2878                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2879                                         & ~FW_BLC_SELF_EN);
2880         }
2881
2882         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2883                   planea_wm, planeb_wm, sr_entries);
2884
2885         planea_wm &= 0x3f;
2886         planeb_wm &= 0x3f;
2887
2888         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2889                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2890                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2891         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2892                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2893         /* HPLL off in SR has some issues on G4x... disable it */
2894         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2895                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2896 }
2897
2898 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2899                            int planeb_clock, int sr_hdisplay, int pixel_size)
2900 {
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         unsigned long line_time_us;
2903         int sr_clock, sr_entries, srwm = 1;
2904
2905         /* Calc sr entries for one plane configs */
2906         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2907                 /* self-refresh has much higher latency */
2908                 static const int sr_latency_ns = 12000;
2909
2910                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2911                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2912
2913                 /* Use ns/us then divide to preserve precision */
2914                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2915                               pixel_size * sr_hdisplay) / 1000;
2916                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2917                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2918                 srwm = I945_FIFO_SIZE - sr_entries;
2919                 if (srwm < 0)
2920                         srwm = 1;
2921                 srwm &= 0x3f;
2922                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2923         } else {
2924                 /* Turn off self refresh if both pipes are enabled */
2925                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2926                                         & ~FW_BLC_SELF_EN);
2927         }
2928
2929         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2930                       srwm);
2931
2932         /* 965 has limitations... */
2933         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2934                    (8 << 0));
2935         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2936 }
2937
2938 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2939                            int planeb_clock, int sr_hdisplay, int pixel_size)
2940 {
2941         struct drm_i915_private *dev_priv = dev->dev_private;
2942         uint32_t fwater_lo;
2943         uint32_t fwater_hi;
2944         int total_size, cacheline_size, cwm, srwm = 1;
2945         int planea_wm, planeb_wm;
2946         struct intel_watermark_params planea_params, planeb_params;
2947         unsigned long line_time_us;
2948         int sr_clock, sr_entries = 0;
2949
2950         /* Create copies of the base settings for each pipe */
2951         if (IS_I965GM(dev) || IS_I945GM(dev))
2952                 planea_params = planeb_params = i945_wm_info;
2953         else if (IS_I9XX(dev))
2954                 planea_params = planeb_params = i915_wm_info;
2955         else
2956                 planea_params = planeb_params = i855_wm_info;
2957
2958         /* Grab a couple of global values before we overwrite them */
2959         total_size = planea_params.fifo_size;
2960         cacheline_size = planea_params.cacheline_size;
2961
2962         /* Update per-plane FIFO sizes */
2963         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2964         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2965
2966         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2967                                        pixel_size, latency_ns);
2968         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2969                                        pixel_size, latency_ns);
2970         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2971
2972         /*
2973          * Overlay gets an aggressive default since video jitter is bad.
2974          */
2975         cwm = 2;
2976
2977         /* Calc sr entries for one plane configs */
2978         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2979             (!planea_clock || !planeb_clock)) {
2980                 /* self-refresh has much higher latency */
2981                 static const int sr_latency_ns = 6000;
2982
2983                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2984                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2985
2986                 /* Use ns/us then divide to preserve precision */
2987                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2988                               pixel_size * sr_hdisplay) / 1000;
2989                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2990                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2991                 srwm = total_size - sr_entries;
2992                 if (srwm < 0)
2993                         srwm = 1;
2994
2995                 if (IS_I945G(dev) || IS_I945GM(dev))
2996                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2997                 else if (IS_I915GM(dev)) {
2998                         /* 915M has a smaller SRWM field */
2999                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3000                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3001                 }
3002         } else {
3003                 /* Turn off self refresh if both pipes are enabled */
3004                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3005                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3006                                    & ~FW_BLC_SELF_EN);
3007                 } else if (IS_I915GM(dev)) {
3008                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3009                 }
3010         }
3011
3012         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3013                   planea_wm, planeb_wm, cwm, srwm);
3014
3015         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3016         fwater_hi = (cwm & 0x1f);
3017
3018         /* Set request length to 8 cachelines per fetch */
3019         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3020         fwater_hi = fwater_hi | (1 << 8);
3021
3022         I915_WRITE(FW_BLC, fwater_lo);
3023         I915_WRITE(FW_BLC2, fwater_hi);
3024 }
3025
3026 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3027                            int unused2, int pixel_size)
3028 {
3029         struct drm_i915_private *dev_priv = dev->dev_private;
3030         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3031         int planea_wm;
3032
3033         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3034
3035         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3036                                        pixel_size, latency_ns);
3037         fwater_lo |= (3<<8) | planea_wm;
3038
3039         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3040
3041         I915_WRITE(FW_BLC, fwater_lo);
3042 }
3043
3044 #define ILK_LP0_PLANE_LATENCY           700
3045
3046 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3047                        int planeb_clock, int sr_hdisplay, int pixel_size)
3048 {
3049         struct drm_i915_private *dev_priv = dev->dev_private;
3050         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3051         int sr_wm, cursor_wm;
3052         unsigned long line_time_us;
3053         int sr_clock, entries_required;
3054         u32 reg_value;
3055
3056         /* Calculate and update the watermark for plane A */
3057         if (planea_clock) {
3058                 entries_required = ((planea_clock / 1000) * pixel_size *
3059                                      ILK_LP0_PLANE_LATENCY) / 1000;
3060                 entries_required = DIV_ROUND_UP(entries_required,
3061                                    ironlake_display_wm_info.cacheline_size);
3062                 planea_wm = entries_required +
3063                             ironlake_display_wm_info.guard_size;
3064
3065                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3066                         planea_wm = ironlake_display_wm_info.max_wm;
3067
3068                 cursora_wm = 16;
3069                 reg_value = I915_READ(WM0_PIPEA_ILK);
3070                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3071                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3072                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3073                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3074                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3075                                 "cursor: %d\n", planea_wm, cursora_wm);
3076         }
3077         /* Calculate and update the watermark for plane B */
3078         if (planeb_clock) {
3079                 entries_required = ((planeb_clock / 1000) * pixel_size *
3080                                      ILK_LP0_PLANE_LATENCY) / 1000;
3081                 entries_required = DIV_ROUND_UP(entries_required,
3082                                    ironlake_display_wm_info.cacheline_size);
3083                 planeb_wm = entries_required +
3084                             ironlake_display_wm_info.guard_size;
3085
3086                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3087                         planeb_wm = ironlake_display_wm_info.max_wm;
3088
3089                 cursorb_wm = 16;
3090                 reg_value = I915_READ(WM0_PIPEB_ILK);
3091                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3092                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3093                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3094                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3095                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3096                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3097         }
3098
3099         /*
3100          * Calculate and update the self-refresh watermark only when one
3101          * display plane is used.
3102          */
3103         if (!planea_clock || !planeb_clock) {
3104                 int line_count;
3105                 /* Read the self-refresh latency. The unit is 0.5us */
3106                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3107
3108                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3109                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3110
3111                 /* Use ns/us then divide to preserve precision */
3112                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3113                                / 1000;
3114
3115                 /* calculate the self-refresh watermark for display plane */
3116                 entries_required = line_count * sr_hdisplay * pixel_size;
3117                 entries_required = DIV_ROUND_UP(entries_required,
3118                                    ironlake_display_srwm_info.cacheline_size);
3119                 sr_wm = entries_required +
3120                         ironlake_display_srwm_info.guard_size;
3121
3122                 /* calculate the self-refresh watermark for display cursor */
3123                 entries_required = line_count * pixel_size * 64;
3124                 entries_required = DIV_ROUND_UP(entries_required,
3125                                    ironlake_cursor_srwm_info.cacheline_size);
3126                 cursor_wm = entries_required +
3127                             ironlake_cursor_srwm_info.guard_size;
3128
3129                 /* configure watermark and enable self-refresh */
3130                 reg_value = I915_READ(WM1_LP_ILK);
3131                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3132                                WM1_LP_CURSOR_MASK);
3133                 reg_value |= WM1_LP_SR_EN |
3134                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3135                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3136
3137                 I915_WRITE(WM1_LP_ILK, reg_value);
3138                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3139                                 "cursor %d\n", sr_wm, cursor_wm);
3140
3141         } else {
3142                 /* Turn off self refresh if both pipes are enabled */
3143                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3144         }
3145 }
3146 /**
3147  * intel_update_watermarks - update FIFO watermark values based on current modes
3148  *
3149  * Calculate watermark values for the various WM regs based on current mode
3150  * and plane configuration.
3151  *
3152  * There are several cases to deal with here:
3153  *   - normal (i.e. non-self-refresh)
3154  *   - self-refresh (SR) mode
3155  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3156  *   - lines are small relative to FIFO size (buffer can hold more than 2
3157  *     lines), so need to account for TLB latency
3158  *
3159  *   The normal calculation is:
3160  *     watermark = dotclock * bytes per pixel * latency
3161  *   where latency is platform & configuration dependent (we assume pessimal
3162  *   values here).
3163  *
3164  *   The SR calculation is:
3165  *     watermark = (trunc(latency/line time)+1) * surface width *
3166  *       bytes per pixel
3167  *   where
3168  *     line time = htotal / dotclock
3169  *   and latency is assumed to be high, as above.
3170  *
3171  * The final value programmed to the register should always be rounded up,
3172  * and include an extra 2 entries to account for clock crossings.
3173  *
3174  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3175  * to set the non-SR watermarks to 8.
3176   */
3177 static void intel_update_watermarks(struct drm_device *dev)
3178 {
3179         struct drm_i915_private *dev_priv = dev->dev_private;
3180         struct drm_crtc *crtc;
3181         struct intel_crtc *intel_crtc;
3182         int sr_hdisplay = 0;
3183         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3184         int enabled = 0, pixel_size = 0;
3185
3186         if (!dev_priv->display.update_wm)
3187                 return;
3188
3189         /* Get the clock config from both planes */
3190         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3191                 intel_crtc = to_intel_crtc(crtc);
3192                 if (crtc->enabled) {
3193                         enabled++;
3194                         if (intel_crtc->plane == 0) {
3195                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3196                                           intel_crtc->pipe, crtc->mode.clock);
3197                                 planea_clock = crtc->mode.clock;
3198                         } else {
3199                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3200                                           intel_crtc->pipe, crtc->mode.clock);
3201                                 planeb_clock = crtc->mode.clock;
3202                         }
3203                         sr_hdisplay = crtc->mode.hdisplay;
3204                         sr_clock = crtc->mode.clock;
3205                         if (crtc->fb)
3206                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3207                         else
3208                                 pixel_size = 4; /* by default */
3209                 }
3210         }
3211
3212         if (enabled <= 0)
3213                 return;
3214
3215         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3216                                     sr_hdisplay, pixel_size);
3217 }
3218
3219 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3220                                struct drm_display_mode *mode,
3221                                struct drm_display_mode *adjusted_mode,
3222                                int x, int y,
3223                                struct drm_framebuffer *old_fb)
3224 {
3225         struct drm_device *dev = crtc->dev;
3226         struct drm_i915_private *dev_priv = dev->dev_private;
3227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3228         int pipe = intel_crtc->pipe;
3229         int plane = intel_crtc->plane;
3230         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3231         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3232         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3233         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3234         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3235         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3236         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3237         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3238         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3239         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3240         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3241         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3242         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3243         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3244         int refclk, num_connectors = 0;
3245         intel_clock_t clock, reduced_clock;
3246         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3247         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3248         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3249         bool is_edp = false;
3250         struct drm_mode_config *mode_config = &dev->mode_config;
3251         struct drm_encoder *encoder;
3252         struct intel_encoder *intel_encoder = NULL;
3253         const intel_limit_t *limit;
3254         int ret;
3255         struct fdi_m_n m_n = {0};
3256         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3257         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3258         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3259         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3260         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3261         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3262         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3263         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3264         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3265         int lvds_reg = LVDS;
3266         u32 temp;
3267         int sdvo_pixel_multiply;
3268         int target_clock;
3269
3270         drm_vblank_pre_modeset(dev, pipe);
3271
3272         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3273
3274                 if (!encoder || encoder->crtc != crtc)
3275                         continue;
3276
3277                 intel_encoder = enc_to_intel_encoder(encoder);
3278
3279                 switch (intel_encoder->type) {
3280                 case INTEL_OUTPUT_LVDS:
3281                         is_lvds = true;
3282                         break;
3283                 case INTEL_OUTPUT_SDVO:
3284                 case INTEL_OUTPUT_HDMI:
3285                         is_sdvo = true;
3286                         if (intel_encoder->needs_tv_clock)
3287                                 is_tv = true;
3288                         break;
3289                 case INTEL_OUTPUT_DVO:
3290                         is_dvo = true;
3291                         break;
3292                 case INTEL_OUTPUT_TVOUT:
3293                         is_tv = true;
3294                         break;
3295                 case INTEL_OUTPUT_ANALOG:
3296                         is_crt = true;
3297                         break;
3298                 case INTEL_OUTPUT_DISPLAYPORT:
3299                         is_dp = true;
3300                         break;
3301                 case INTEL_OUTPUT_EDP:
3302                         is_edp = true;
3303                         break;
3304                 }
3305
3306                 num_connectors++;
3307         }
3308
3309         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3310                 refclk = dev_priv->lvds_ssc_freq * 1000;
3311                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3312                                         refclk / 1000);
3313         } else if (IS_I9XX(dev)) {
3314                 refclk = 96000;
3315                 if (HAS_PCH_SPLIT(dev))
3316                         refclk = 120000; /* 120Mhz refclk */
3317         } else {
3318                 refclk = 48000;
3319         }
3320
3321
3322         /*
3323          * Returns a set of divisors for the desired target clock with the given
3324          * refclk, or FALSE.  The returned values represent the clock equation:
3325          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3326          */
3327         limit = intel_limit(crtc);
3328         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3329         if (!ok) {
3330                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3331                 drm_vblank_post_modeset(dev, pipe);
3332                 return -EINVAL;
3333         }
3334
3335         if (is_lvds && dev_priv->lvds_downclock_avail) {
3336                 has_reduced_clock = limit->find_pll(limit, crtc,
3337                                                             dev_priv->lvds_downclock,
3338                                                             refclk,
3339                                                             &reduced_clock);
3340                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3341                         /*
3342                          * If the different P is found, it means that we can't
3343                          * switch the display clock by using the FP0/FP1.
3344                          * In such case we will disable the LVDS downclock
3345                          * feature.
3346                          */
3347                         DRM_DEBUG_KMS("Different P is found for "
3348                                                 "LVDS clock/downclock\n");
3349                         has_reduced_clock = 0;
3350                 }
3351         }
3352         /* SDVO TV has fixed PLL values depend on its clock range,
3353            this mirrors vbios setting. */
3354         if (is_sdvo && is_tv) {
3355                 if (adjusted_mode->clock >= 100000
3356                                 && adjusted_mode->clock < 140500) {
3357                         clock.p1 = 2;
3358                         clock.p2 = 10;
3359                         clock.n = 3;
3360                         clock.m1 = 16;
3361                         clock.m2 = 8;
3362                 } else if (adjusted_mode->clock >= 140500
3363                                 && adjusted_mode->clock <= 200000) {
3364                         clock.p1 = 1;
3365                         clock.p2 = 10;
3366                         clock.n = 6;
3367                         clock.m1 = 12;
3368                         clock.m2 = 8;
3369                 }
3370         }
3371
3372         /* FDI link */
3373         if (HAS_PCH_SPLIT(dev)) {
3374                 int lane = 0, link_bw, bpp;
3375                 /* eDP doesn't require FDI link, so just set DP M/N
3376                    according to current link config */
3377                 if (is_edp) {
3378                         target_clock = mode->clock;
3379                         intel_edp_link_config(intel_encoder,
3380                                         &lane, &link_bw);
3381                 } else {
3382                         /* DP over FDI requires target mode clock
3383                            instead of link clock */
3384                         if (is_dp)
3385                                 target_clock = mode->clock;
3386                         else
3387                                 target_clock = adjusted_mode->clock;
3388                         link_bw = 270000;
3389                 }
3390
3391                 /* determine panel color depth */
3392                 temp = I915_READ(pipeconf_reg);
3393                 temp &= ~PIPE_BPC_MASK;
3394                 if (is_lvds) {
3395                         int lvds_reg = I915_READ(PCH_LVDS);
3396                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3397                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3398                                 temp |= PIPE_8BPC;
3399                         else
3400                                 temp |= PIPE_6BPC;
3401                 } else if (is_edp) {
3402                         switch (dev_priv->edp_bpp/3) {
3403                         case 8:
3404                                 temp |= PIPE_8BPC;
3405                                 break;
3406                         case 10:
3407                                 temp |= PIPE_10BPC;
3408                                 break;
3409                         case 6:
3410                                 temp |= PIPE_6BPC;
3411                                 break;
3412                         case 12:
3413                                 temp |= PIPE_12BPC;
3414                                 break;
3415                         }
3416                 } else
3417                         temp |= PIPE_8BPC;
3418                 I915_WRITE(pipeconf_reg, temp);
3419                 I915_READ(pipeconf_reg);
3420
3421                 switch (temp & PIPE_BPC_MASK) {
3422                 case PIPE_8BPC:
3423                         bpp = 24;
3424                         break;
3425                 case PIPE_10BPC:
3426                         bpp = 30;
3427                         break;
3428                 case PIPE_6BPC:
3429                         bpp = 18;
3430                         break;
3431                 case PIPE_12BPC:
3432                         bpp = 36;
3433                         break;
3434                 default:
3435                         DRM_ERROR("unknown pipe bpc value\n");
3436                         bpp = 24;
3437                 }
3438
3439                 if (!lane) {
3440                         /*
3441                          * Account for spread spectrum to avoid
3442                          * oversubscribing the link. Max center spread
3443                          * is 2.5%; use 5% for safety's sake.
3444                          */
3445                         u32 bps = target_clock * bpp * 21 / 20;
3446                         lane = bps / (link_bw * 8) + 1;
3447                 }
3448
3449                 intel_crtc->fdi_lanes = lane;
3450
3451                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3452         }
3453
3454         /* Ironlake: try to setup display ref clock before DPLL
3455          * enabling. This is only under driver's control after
3456          * PCH B stepping, previous chipset stepping should be
3457          * ignoring this setting.
3458          */
3459         if (HAS_PCH_SPLIT(dev)) {
3460                 temp = I915_READ(PCH_DREF_CONTROL);
3461                 /* Always enable nonspread source */
3462                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3463                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3464                 I915_WRITE(PCH_DREF_CONTROL, temp);
3465                 POSTING_READ(PCH_DREF_CONTROL);
3466
3467                 temp &= ~DREF_SSC_SOURCE_MASK;
3468                 temp |= DREF_SSC_SOURCE_ENABLE;
3469                 I915_WRITE(PCH_DREF_CONTROL, temp);
3470                 POSTING_READ(PCH_DREF_CONTROL);
3471
3472                 udelay(200);
3473
3474                 if (is_edp) {
3475                         if (dev_priv->lvds_use_ssc) {
3476                                 temp |= DREF_SSC1_ENABLE;
3477                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3478                                 POSTING_READ(PCH_DREF_CONTROL);
3479
3480                                 udelay(200);
3481
3482                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3483                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3484                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3485                                 POSTING_READ(PCH_DREF_CONTROL);
3486                         } else {
3487                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3488                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3489                                 POSTING_READ(PCH_DREF_CONTROL);
3490                         }
3491                 }
3492         }
3493
3494         if (IS_PINEVIEW(dev)) {
3495                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3496                 if (has_reduced_clock)
3497                         fp2 = (1 << reduced_clock.n) << 16 |
3498                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3499         } else {
3500                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3501                 if (has_reduced_clock)
3502                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3503                                 reduced_clock.m2;
3504         }
3505
3506         if (!HAS_PCH_SPLIT(dev))
3507                 dpll = DPLL_VGA_MODE_DIS;
3508
3509         if (IS_I9XX(dev)) {
3510                 if (is_lvds)
3511                         dpll |= DPLLB_MODE_LVDS;
3512                 else
3513                         dpll |= DPLLB_MODE_DAC_SERIAL;
3514                 if (is_sdvo) {
3515                         dpll |= DPLL_DVO_HIGH_SPEED;
3516                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3517                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3518                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3519                         else if (HAS_PCH_SPLIT(dev))
3520                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3521                 }
3522                 if (is_dp)
3523                         dpll |= DPLL_DVO_HIGH_SPEED;
3524
3525                 /* compute bitmask from p1 value */
3526                 if (IS_PINEVIEW(dev))
3527                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3528                 else {
3529                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3530                         /* also FPA1 */
3531                         if (HAS_PCH_SPLIT(dev))
3532                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3533                         if (IS_G4X(dev) && has_reduced_clock)
3534                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3535                 }
3536                 switch (clock.p2) {
3537                 case 5:
3538                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3539                         break;
3540                 case 7:
3541                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3542                         break;
3543                 case 10:
3544                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3545                         break;
3546                 case 14:
3547                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3548                         break;
3549                 }
3550                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3551                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3552         } else {
3553                 if (is_lvds) {
3554                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3555                 } else {
3556                         if (clock.p1 == 2)
3557                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3558                         else
3559                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3560                         if (clock.p2 == 4)
3561                                 dpll |= PLL_P2_DIVIDE_BY_4;
3562                 }
3563         }
3564
3565         if (is_sdvo && is_tv)
3566                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3567         else if (is_tv)
3568                 /* XXX: just matching BIOS for now */
3569                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3570                 dpll |= 3;
3571         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3572                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3573         else
3574                 dpll |= PLL_REF_INPUT_DREFCLK;
3575
3576         /* setup pipeconf */
3577         pipeconf = I915_READ(pipeconf_reg);
3578
3579         /* Set up the display plane register */
3580         dspcntr = DISPPLANE_GAMMA_ENABLE;
3581
3582         /* Ironlake's plane is forced to pipe, bit 24 is to
3583            enable color space conversion */
3584         if (!HAS_PCH_SPLIT(dev)) {
3585                 if (pipe == 0)
3586                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3587                 else
3588                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3589         }
3590
3591         if (pipe == 0 && !IS_I965G(dev)) {
3592                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3593                  * core speed.
3594                  *
3595                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3596                  * pipe == 0 check?
3597                  */
3598                 if (mode->clock >
3599                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3600                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3601                 else
3602                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3603         }
3604
3605         /* Disable the panel fitter if it was on our pipe */
3606         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3607                 I915_WRITE(PFIT_CONTROL, 0);
3608
3609         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3610         drm_mode_debug_printmodeline(mode);
3611
3612         /* assign to Ironlake registers */
3613         if (HAS_PCH_SPLIT(dev)) {
3614                 fp_reg = pch_fp_reg;
3615                 dpll_reg = pch_dpll_reg;
3616         }
3617
3618         if (is_edp) {
3619                 ironlake_disable_pll_edp(crtc);
3620         } else if ((dpll & DPLL_VCO_ENABLE)) {
3621                 I915_WRITE(fp_reg, fp);
3622                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3623                 I915_READ(dpll_reg);
3624                 udelay(150);
3625         }
3626
3627         /* enable transcoder DPLL */
3628         if (HAS_PCH_CPT(dev)) {
3629                 temp = I915_READ(PCH_DPLL_SEL);
3630                 if (trans_dpll_sel == 0)
3631                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3632                 else
3633                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3634                 I915_WRITE(PCH_DPLL_SEL, temp);
3635                 I915_READ(PCH_DPLL_SEL);
3636                 udelay(150);
3637         }
3638
3639         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3640          * This is an exception to the general rule that mode_set doesn't turn
3641          * things on.
3642          */
3643         if (is_lvds) {
3644                 u32 lvds;
3645
3646                 if (HAS_PCH_SPLIT(dev))
3647                         lvds_reg = PCH_LVDS;
3648
3649                 lvds = I915_READ(lvds_reg);
3650                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3651                 if (pipe == 1) {
3652                         if (HAS_PCH_CPT(dev))
3653                                 lvds |= PORT_TRANS_B_SEL_CPT;
3654                         else
3655                                 lvds |= LVDS_PIPEB_SELECT;
3656                 } else {
3657                         if (HAS_PCH_CPT(dev))
3658                                 lvds &= ~PORT_TRANS_SEL_MASK;
3659                         else
3660                                 lvds &= ~LVDS_PIPEB_SELECT;
3661                 }
3662                 /* set the corresponsding LVDS_BORDER bit */
3663                 lvds |= dev_priv->lvds_border_bits;
3664                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3665                  * set the DPLLs for dual-channel mode or not.
3666                  */
3667                 if (clock.p2 == 7)
3668                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3669                 else
3670                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3671
3672                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3673                  * appropriately here, but we need to look more thoroughly into how
3674                  * panels behave in the two modes.
3675                  */
3676                 /* set the dithering flag */
3677                 if (IS_I965G(dev)) {
3678                         if (dev_priv->lvds_dither) {
3679                                 if (HAS_PCH_SPLIT(dev))
3680                                         pipeconf |= PIPE_ENABLE_DITHER;
3681                                 else
3682                                         lvds |= LVDS_ENABLE_DITHER;
3683                         } else {
3684                                 if (HAS_PCH_SPLIT(dev))
3685                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3686                                 else
3687                                         lvds &= ~LVDS_ENABLE_DITHER;
3688                         }
3689                 }
3690                 I915_WRITE(lvds_reg, lvds);
3691                 I915_READ(lvds_reg);
3692         }
3693         if (is_dp)
3694                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3695         else if (HAS_PCH_SPLIT(dev)) {
3696                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3697                 if (pipe == 0) {
3698                         I915_WRITE(TRANSA_DATA_M1, 0);
3699                         I915_WRITE(TRANSA_DATA_N1, 0);
3700                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3701                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3702                 } else {
3703                         I915_WRITE(TRANSB_DATA_M1, 0);
3704                         I915_WRITE(TRANSB_DATA_N1, 0);
3705                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3706                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3707                 }
3708         }
3709
3710         if (!is_edp) {
3711                 I915_WRITE(fp_reg, fp);
3712                 I915_WRITE(dpll_reg, dpll);
3713                 I915_READ(dpll_reg);
3714                 /* Wait for the clocks to stabilize. */
3715                 udelay(150);
3716
3717                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3718                         if (is_sdvo) {
3719                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3720                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3721                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3722                         } else
3723                                 I915_WRITE(dpll_md_reg, 0);
3724                 } else {
3725                         /* write it again -- the BIOS does, after all */
3726                         I915_WRITE(dpll_reg, dpll);
3727                 }
3728                 I915_READ(dpll_reg);
3729                 /* Wait for the clocks to stabilize. */
3730                 udelay(150);
3731         }
3732
3733         if (is_lvds && has_reduced_clock && i915_powersave) {
3734                 I915_WRITE(fp_reg + 4, fp2);
3735                 intel_crtc->lowfreq_avail = true;
3736                 if (HAS_PIPE_CXSR(dev)) {
3737                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3738                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3739                 }
3740         } else {
3741                 I915_WRITE(fp_reg + 4, fp);
3742                 intel_crtc->lowfreq_avail = false;
3743                 if (HAS_PIPE_CXSR(dev)) {
3744                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3745                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3746                 }
3747         }
3748
3749         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3750                    ((adjusted_mode->crtc_htotal - 1) << 16));
3751         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3752                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3753         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3754                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3755         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3756                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3757         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3758                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3759         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3760                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3761         /* pipesrc and dspsize control the size that is scaled from, which should
3762          * always be the user's requested size.
3763          */
3764         if (!HAS_PCH_SPLIT(dev)) {
3765                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3766                                 (mode->hdisplay - 1));
3767                 I915_WRITE(dsppos_reg, 0);
3768         }
3769         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3770
3771         if (HAS_PCH_SPLIT(dev)) {
3772                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3773                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3774                 I915_WRITE(link_m1_reg, m_n.link_m);
3775                 I915_WRITE(link_n1_reg, m_n.link_n);
3776
3777                 if (is_edp) {
3778                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3779                 } else {
3780                         /* enable FDI RX PLL too */
3781                         temp = I915_READ(fdi_rx_reg);
3782                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3783                         I915_READ(fdi_rx_reg);
3784                         udelay(200);
3785
3786                         /* enable FDI TX PLL too */
3787                         temp = I915_READ(fdi_tx_reg);
3788                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3789                         I915_READ(fdi_tx_reg);
3790
3791                         /* enable FDI RX PCDCLK */
3792                         temp = I915_READ(fdi_rx_reg);
3793                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3794                         I915_READ(fdi_rx_reg);
3795                         udelay(200);
3796                 }
3797         }
3798
3799         I915_WRITE(pipeconf_reg, pipeconf);
3800         I915_READ(pipeconf_reg);
3801
3802         intel_wait_for_vblank(dev);
3803
3804         if (IS_IRONLAKE(dev)) {
3805                 /* enable address swizzle for tiling buffer */
3806                 temp = I915_READ(DISP_ARB_CTL);
3807                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3808         }
3809
3810         I915_WRITE(dspcntr_reg, dspcntr);
3811
3812         /* Flush the plane changes */
3813         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3814
3815         if ((IS_I965G(dev) || plane == 0))
3816                 intel_update_fbc(crtc, &crtc->mode);
3817
3818         intel_update_watermarks(dev);
3819
3820         drm_vblank_post_modeset(dev, pipe);
3821
3822         return ret;
3823 }
3824
3825 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3826 void intel_crtc_load_lut(struct drm_crtc *crtc)
3827 {
3828         struct drm_device *dev = crtc->dev;
3829         struct drm_i915_private *dev_priv = dev->dev_private;
3830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3832         int i;
3833
3834         /* The clocks have to be on to load the palette. */
3835         if (!crtc->enabled)
3836                 return;
3837
3838         /* use legacy palette for Ironlake */
3839         if (HAS_PCH_SPLIT(dev))
3840                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3841                                                    LGC_PALETTE_B;
3842
3843         for (i = 0; i < 256; i++) {
3844                 I915_WRITE(palreg + 4 * i,
3845                            (intel_crtc->lut_r[i] << 16) |
3846                            (intel_crtc->lut_g[i] << 8) |
3847                            intel_crtc->lut_b[i]);
3848         }
3849 }
3850
3851 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3852                                  struct drm_file *file_priv,
3853                                  uint32_t handle,
3854                                  uint32_t width, uint32_t height)
3855 {
3856         struct drm_device *dev = crtc->dev;
3857         struct drm_i915_private *dev_priv = dev->dev_private;
3858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3859         struct drm_gem_object *bo;
3860         struct drm_i915_gem_object *obj_priv;
3861         int pipe = intel_crtc->pipe;
3862         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3863         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3864         uint32_t temp = I915_READ(control);
3865         size_t addr;
3866         int ret;
3867
3868         DRM_DEBUG_KMS("\n");
3869
3870         /* if we want to turn off the cursor ignore width and height */
3871         if (!handle) {
3872                 DRM_DEBUG_KMS("cursor off\n");
3873                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3874                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3875                         temp |= CURSOR_MODE_DISABLE;
3876                 } else {
3877                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3878                 }
3879                 addr = 0;
3880                 bo = NULL;
3881                 mutex_lock(&dev->struct_mutex);
3882                 goto finish;
3883         }
3884
3885         /* Currently we only support 64x64 cursors */
3886         if (width != 64 || height != 64) {
3887                 DRM_ERROR("we currently only support 64x64 cursors\n");
3888                 return -EINVAL;
3889         }
3890
3891         bo = drm_gem_object_lookup(dev, file_priv, handle);
3892         if (!bo)
3893                 return -ENOENT;
3894
3895         obj_priv = to_intel_bo(bo);
3896
3897         if (bo->size < width * height * 4) {
3898                 DRM_ERROR("buffer is to small\n");
3899                 ret = -ENOMEM;
3900                 goto fail;
3901         }
3902
3903         /* we only need to pin inside GTT if cursor is non-phy */
3904         mutex_lock(&dev->struct_mutex);
3905         if (!dev_priv->info->cursor_needs_physical) {
3906                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3907                 if (ret) {
3908                         DRM_ERROR("failed to pin cursor bo\n");
3909                         goto fail_locked;
3910                 }
3911                 addr = obj_priv->gtt_offset;
3912         } else {
3913                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3914                 if (ret) {
3915                         DRM_ERROR("failed to attach phys object\n");
3916                         goto fail_locked;
3917                 }
3918                 addr = obj_priv->phys_obj->handle->busaddr;
3919         }
3920
3921         if (!IS_I9XX(dev))
3922                 I915_WRITE(CURSIZE, (height << 12) | width);
3923
3924         /* Hooray for CUR*CNTR differences */
3925         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3926                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3927                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3928                 temp |= (pipe << 28); /* Connect to correct pipe */
3929         } else {
3930                 temp &= ~(CURSOR_FORMAT_MASK);
3931                 temp |= CURSOR_ENABLE;
3932                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3933         }
3934
3935  finish:
3936         I915_WRITE(control, temp);
3937         I915_WRITE(base, addr);
3938
3939         if (intel_crtc->cursor_bo) {
3940                 if (dev_priv->info->cursor_needs_physical) {
3941                         if (intel_crtc->cursor_bo != bo)
3942                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3943                 } else
3944                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3945                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3946         }
3947
3948         mutex_unlock(&dev->struct_mutex);
3949
3950         intel_crtc->cursor_addr = addr;
3951         intel_crtc->cursor_bo = bo;
3952
3953         return 0;
3954 fail_locked:
3955         mutex_unlock(&dev->struct_mutex);
3956 fail:
3957         drm_gem_object_unreference_unlocked(bo);
3958         return ret;
3959 }
3960
3961 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3962 {
3963         struct drm_device *dev = crtc->dev;
3964         struct drm_i915_private *dev_priv = dev->dev_private;
3965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3966         struct intel_framebuffer *intel_fb;
3967         int pipe = intel_crtc->pipe;
3968         uint32_t temp = 0;
3969         uint32_t adder;
3970
3971         if (crtc->fb) {
3972                 intel_fb = to_intel_framebuffer(crtc->fb);
3973                 intel_mark_busy(dev, intel_fb->obj);
3974         }
3975
3976         if (x < 0) {
3977                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3978                 x = -x;
3979         }
3980         if (y < 0) {
3981                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3982                 y = -y;
3983         }
3984
3985         temp |= x << CURSOR_X_SHIFT;
3986         temp |= y << CURSOR_Y_SHIFT;
3987
3988         adder = intel_crtc->cursor_addr;
3989         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3990         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3991
3992         return 0;
3993 }
3994
3995 /** Sets the color ramps on behalf of RandR */
3996 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3997                                  u16 blue, int regno)
3998 {
3999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4000
4001         intel_crtc->lut_r[regno] = red >> 8;
4002         intel_crtc->lut_g[regno] = green >> 8;
4003         intel_crtc->lut_b[regno] = blue >> 8;
4004 }
4005
4006 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4007                              u16 *blue, int regno)
4008 {
4009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4010
4011         *red = intel_crtc->lut_r[regno] << 8;
4012         *green = intel_crtc->lut_g[regno] << 8;
4013         *blue = intel_crtc->lut_b[regno] << 8;
4014 }
4015
4016 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4017                                  u16 *blue, uint32_t size)
4018 {
4019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4020         int i;
4021
4022         if (size != 256)
4023                 return;
4024
4025         for (i = 0; i < 256; i++) {
4026                 intel_crtc->lut_r[i] = red[i] >> 8;
4027                 intel_crtc->lut_g[i] = green[i] >> 8;
4028                 intel_crtc->lut_b[i] = blue[i] >> 8;
4029         }
4030
4031         intel_crtc_load_lut(crtc);
4032 }
4033
4034 /**
4035  * Get a pipe with a simple mode set on it for doing load-based monitor
4036  * detection.
4037  *
4038  * It will be up to the load-detect code to adjust the pipe as appropriate for
4039  * its requirements.  The pipe will be connected to no other encoders.
4040  *
4041  * Currently this code will only succeed if there is a pipe with no encoders
4042  * configured for it.  In the future, it could choose to temporarily disable
4043  * some outputs to free up a pipe for its use.
4044  *
4045  * \return crtc, or NULL if no pipes are available.
4046  */
4047
4048 /* VESA 640x480x72Hz mode to set on the pipe */
4049 static struct drm_display_mode load_detect_mode = {
4050         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4051                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4052 };
4053
4054 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4055                                             struct drm_connector *connector,
4056                                             struct drm_display_mode *mode,
4057                                             int *dpms_mode)
4058 {
4059         struct intel_crtc *intel_crtc;
4060         struct drm_crtc *possible_crtc;
4061         struct drm_crtc *supported_crtc =NULL;
4062         struct drm_encoder *encoder = &intel_encoder->enc;
4063         struct drm_crtc *crtc = NULL;
4064         struct drm_device *dev = encoder->dev;
4065         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4066         struct drm_crtc_helper_funcs *crtc_funcs;
4067         int i = -1;
4068
4069         /*
4070          * Algorithm gets a little messy:
4071          *   - if the connector already has an assigned crtc, use it (but make
4072          *     sure it's on first)
4073          *   - try to find the first unused crtc that can drive this connector,
4074          *     and use that if we find one
4075          *   - if there are no unused crtcs available, try to use the first
4076          *     one we found that supports the connector
4077          */
4078
4079         /* See if we already have a CRTC for this connector */
4080         if (encoder->crtc) {
4081                 crtc = encoder->crtc;
4082                 /* Make sure the crtc and connector are running */
4083                 intel_crtc = to_intel_crtc(crtc);
4084                 *dpms_mode = intel_crtc->dpms_mode;
4085                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4086                         crtc_funcs = crtc->helper_private;
4087                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4088                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4089                 }
4090                 return crtc;
4091         }
4092
4093         /* Find an unused one (if possible) */
4094         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4095                 i++;
4096                 if (!(encoder->possible_crtcs & (1 << i)))
4097                         continue;
4098                 if (!possible_crtc->enabled) {
4099                         crtc = possible_crtc;
4100                         break;
4101                 }
4102                 if (!supported_crtc)
4103                         supported_crtc = possible_crtc;
4104         }
4105
4106         /*
4107          * If we didn't find an unused CRTC, don't use any.
4108          */
4109         if (!crtc) {
4110                 return NULL;
4111         }
4112
4113         encoder->crtc = crtc;
4114         connector->encoder = encoder;
4115         intel_encoder->load_detect_temp = true;
4116
4117         intel_crtc = to_intel_crtc(crtc);
4118         *dpms_mode = intel_crtc->dpms_mode;
4119
4120         if (!crtc->enabled) {
4121                 if (!mode)
4122                         mode = &load_detect_mode;
4123                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4124         } else {
4125                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4126                         crtc_funcs = crtc->helper_private;
4127                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4128                 }
4129
4130                 /* Add this connector to the crtc */
4131                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4132                 encoder_funcs->commit(encoder);
4133         }
4134         /* let the connector get through one full cycle before testing */
4135         intel_wait_for_vblank(dev);
4136
4137         return crtc;
4138 }
4139
4140 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4141                                     struct drm_connector *connector, int dpms_mode)
4142 {
4143         struct drm_encoder *encoder = &intel_encoder->enc;
4144         struct drm_device *dev = encoder->dev;
4145         struct drm_crtc *crtc = encoder->crtc;
4146         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4147         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4148
4149         if (intel_encoder->load_detect_temp) {
4150                 encoder->crtc = NULL;
4151                 connector->encoder = NULL;
4152                 intel_encoder->load_detect_temp = false;
4153                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4154                 drm_helper_disable_unused_functions(dev);
4155         }
4156
4157         /* Switch crtc and encoder back off if necessary */
4158         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4159                 if (encoder->crtc == crtc)
4160                         encoder_funcs->dpms(encoder, dpms_mode);
4161                 crtc_funcs->dpms(crtc, dpms_mode);
4162         }
4163 }
4164
4165 /* Returns the clock of the currently programmed mode of the given pipe. */
4166 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4167 {
4168         struct drm_i915_private *dev_priv = dev->dev_private;
4169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4170         int pipe = intel_crtc->pipe;
4171         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4172         u32 fp;
4173         intel_clock_t clock;
4174
4175         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4176                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4177         else
4178                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4179
4180         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4181         if (IS_PINEVIEW(dev)) {
4182                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4183                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4184         } else {
4185                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4186                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4187         }
4188
4189         if (IS_I9XX(dev)) {
4190                 if (IS_PINEVIEW(dev))
4191                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4192                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4193                 else
4194                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4195                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4196
4197                 switch (dpll & DPLL_MODE_MASK) {
4198                 case DPLLB_MODE_DAC_SERIAL:
4199                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4200                                 5 : 10;
4201                         break;
4202                 case DPLLB_MODE_LVDS:
4203                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4204                                 7 : 14;
4205                         break;
4206                 default:
4207                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4208                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4209                         return 0;
4210                 }
4211
4212                 /* XXX: Handle the 100Mhz refclk */
4213                 intel_clock(dev, 96000, &clock);
4214         } else {
4215                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4216
4217                 if (is_lvds) {
4218                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4219                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4220                         clock.p2 = 14;
4221
4222                         if ((dpll & PLL_REF_INPUT_MASK) ==
4223                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4224                                 /* XXX: might not be 66MHz */
4225                                 intel_clock(dev, 66000, &clock);
4226                         } else
4227                                 intel_clock(dev, 48000, &clock);
4228                 } else {
4229                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4230                                 clock.p1 = 2;
4231                         else {
4232                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4233                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4234                         }
4235                         if (dpll & PLL_P2_DIVIDE_BY_4)
4236                                 clock.p2 = 4;
4237                         else
4238                                 clock.p2 = 2;
4239
4240                         intel_clock(dev, 48000, &clock);
4241                 }
4242         }
4243
4244         /* XXX: It would be nice to validate the clocks, but we can't reuse
4245          * i830PllIsValid() because it relies on the xf86_config connector
4246          * configuration being accurate, which it isn't necessarily.
4247          */
4248
4249         return clock.dot;
4250 }
4251
4252 /** Returns the currently programmed mode of the given pipe. */
4253 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4254                                              struct drm_crtc *crtc)
4255 {
4256         struct drm_i915_private *dev_priv = dev->dev_private;
4257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4258         int pipe = intel_crtc->pipe;
4259         struct drm_display_mode *mode;
4260         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4261         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4262         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4263         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4264
4265         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4266         if (!mode)
4267                 return NULL;
4268
4269         mode->clock = intel_crtc_clock_get(dev, crtc);
4270         mode->hdisplay = (htot & 0xffff) + 1;
4271         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4272         mode->hsync_start = (hsync & 0xffff) + 1;
4273         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4274         mode->vdisplay = (vtot & 0xffff) + 1;
4275         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4276         mode->vsync_start = (vsync & 0xffff) + 1;
4277         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4278
4279         drm_mode_set_name(mode);
4280         drm_mode_set_crtcinfo(mode, 0);
4281
4282         return mode;
4283 }
4284
4285 #define GPU_IDLE_TIMEOUT 500 /* ms */
4286
4287 /* When this timer fires, we've been idle for awhile */
4288 static void intel_gpu_idle_timer(unsigned long arg)
4289 {
4290         struct drm_device *dev = (struct drm_device *)arg;
4291         drm_i915_private_t *dev_priv = dev->dev_private;
4292
4293         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4294
4295         dev_priv->busy = false;
4296
4297         queue_work(dev_priv->wq, &dev_priv->idle_work);
4298 }
4299
4300 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4301
4302 static void intel_crtc_idle_timer(unsigned long arg)
4303 {
4304         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4305         struct drm_crtc *crtc = &intel_crtc->base;
4306         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4307
4308         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4309
4310         intel_crtc->busy = false;
4311
4312         queue_work(dev_priv->wq, &dev_priv->idle_work);
4313 }
4314
4315 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4316 {
4317         struct drm_device *dev = crtc->dev;
4318         drm_i915_private_t *dev_priv = dev->dev_private;
4319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4320         int pipe = intel_crtc->pipe;
4321         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4322         int dpll = I915_READ(dpll_reg);
4323
4324         if (HAS_PCH_SPLIT(dev))
4325                 return;
4326
4327         if (!dev_priv->lvds_downclock_avail)
4328                 return;
4329
4330         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4331                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4332
4333                 /* Unlock panel regs */
4334                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4335
4336                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4337                 I915_WRITE(dpll_reg, dpll);
4338                 dpll = I915_READ(dpll_reg);
4339                 intel_wait_for_vblank(dev);
4340                 dpll = I915_READ(dpll_reg);
4341                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4342                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4343
4344                 /* ...and lock them again */
4345                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4346         }
4347
4348         /* Schedule downclock */
4349         if (schedule)
4350                 mod_timer(&intel_crtc->idle_timer, jiffies +
4351                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4352 }
4353
4354 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4355 {
4356         struct drm_device *dev = crtc->dev;
4357         drm_i915_private_t *dev_priv = dev->dev_private;
4358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4359         int pipe = intel_crtc->pipe;
4360         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4361         int dpll = I915_READ(dpll_reg);
4362
4363         if (HAS_PCH_SPLIT(dev))
4364                 return;
4365
4366         if (!dev_priv->lvds_downclock_avail)
4367                 return;
4368
4369         /*
4370          * Since this is called by a timer, we should never get here in
4371          * the manual case.
4372          */
4373         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4374                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4375
4376                 /* Unlock panel regs */
4377                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4378
4379                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4380                 I915_WRITE(dpll_reg, dpll);
4381                 dpll = I915_READ(dpll_reg);
4382                 intel_wait_for_vblank(dev);
4383                 dpll = I915_READ(dpll_reg);
4384                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4385                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4386
4387                 /* ...and lock them again */
4388                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4389         }
4390
4391 }
4392
4393 /**
4394  * intel_idle_update - adjust clocks for idleness
4395  * @work: work struct
4396  *
4397  * Either the GPU or display (or both) went idle.  Check the busy status
4398  * here and adjust the CRTC and GPU clocks as necessary.
4399  */
4400 static void intel_idle_update(struct work_struct *work)
4401 {
4402         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4403                                                     idle_work);
4404         struct drm_device *dev = dev_priv->dev;
4405         struct drm_crtc *crtc;
4406         struct intel_crtc *intel_crtc;
4407
4408         if (!i915_powersave)
4409                 return;
4410
4411         mutex_lock(&dev->struct_mutex);
4412
4413         if (IS_I945G(dev) || IS_I945GM(dev)) {
4414                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4415                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4416         }
4417
4418         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4419                 /* Skip inactive CRTCs */
4420                 if (!crtc->fb)
4421                         continue;
4422
4423                 intel_crtc = to_intel_crtc(crtc);
4424                 if (!intel_crtc->busy)
4425                         intel_decrease_pllclock(crtc);
4426         }
4427
4428         mutex_unlock(&dev->struct_mutex);
4429 }
4430
4431 /**
4432  * intel_mark_busy - mark the GPU and possibly the display busy
4433  * @dev: drm device
4434  * @obj: object we're operating on
4435  *
4436  * Callers can use this function to indicate that the GPU is busy processing
4437  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4438  * buffer), we'll also mark the display as busy, so we know to increase its
4439  * clock frequency.
4440  */
4441 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4442 {
4443         drm_i915_private_t *dev_priv = dev->dev_private;
4444         struct drm_crtc *crtc = NULL;
4445         struct intel_framebuffer *intel_fb;
4446         struct intel_crtc *intel_crtc;
4447
4448         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4449                 return;
4450
4451         if (!dev_priv->busy) {
4452                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4453                         u32 fw_blc_self;
4454
4455                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4456                         fw_blc_self = I915_READ(FW_BLC_SELF);
4457                         fw_blc_self &= ~FW_BLC_SELF_EN;
4458                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4459                 }
4460                 dev_priv->busy = true;
4461         } else
4462                 mod_timer(&dev_priv->idle_timer, jiffies +
4463                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4464
4465         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4466                 if (!crtc->fb)
4467                         continue;
4468
4469                 intel_crtc = to_intel_crtc(crtc);
4470                 intel_fb = to_intel_framebuffer(crtc->fb);
4471                 if (intel_fb->obj == obj) {
4472                         if (!intel_crtc->busy) {
4473                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4474                                         u32 fw_blc_self;
4475
4476                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4477                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4478                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4479                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4480                                 }
4481                                 /* Non-busy -> busy, upclock */
4482                                 intel_increase_pllclock(crtc, true);
4483                                 intel_crtc->busy = true;
4484                         } else {
4485                                 /* Busy -> busy, put off timer */
4486                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4487                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4488                         }
4489                 }
4490         }
4491 }
4492
4493 static void intel_crtc_destroy(struct drm_crtc *crtc)
4494 {
4495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4496
4497         drm_crtc_cleanup(crtc);
4498         kfree(intel_crtc);
4499 }
4500
4501 struct intel_unpin_work {
4502         struct work_struct work;
4503         struct drm_device *dev;
4504         struct drm_gem_object *old_fb_obj;
4505         struct drm_gem_object *pending_flip_obj;
4506         struct drm_pending_vblank_event *event;
4507         int pending;
4508 };
4509
4510 static void intel_unpin_work_fn(struct work_struct *__work)
4511 {
4512         struct intel_unpin_work *work =
4513                 container_of(__work, struct intel_unpin_work, work);
4514
4515         mutex_lock(&work->dev->struct_mutex);
4516         i915_gem_object_unpin(work->old_fb_obj);
4517         drm_gem_object_unreference(work->pending_flip_obj);
4518         drm_gem_object_unreference(work->old_fb_obj);
4519         mutex_unlock(&work->dev->struct_mutex);
4520         kfree(work);
4521 }
4522
4523 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4524 {
4525         drm_i915_private_t *dev_priv = dev->dev_private;
4526         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4528         struct intel_unpin_work *work;
4529         struct drm_i915_gem_object *obj_priv;
4530         struct drm_pending_vblank_event *e;
4531         struct timeval now;
4532         unsigned long flags;
4533
4534         /* Ignore early vblank irqs */
4535         if (intel_crtc == NULL)
4536                 return;
4537
4538         spin_lock_irqsave(&dev->event_lock, flags);
4539         work = intel_crtc->unpin_work;
4540         if (work == NULL || !work->pending) {
4541                 if (work && !work->pending) {
4542                         obj_priv = to_intel_bo(work->pending_flip_obj);
4543                         DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4544                                          obj_priv,
4545                                          atomic_read(&obj_priv->pending_flip));
4546                 }
4547                 spin_unlock_irqrestore(&dev->event_lock, flags);
4548                 return;
4549         }
4550
4551         intel_crtc->unpin_work = NULL;
4552         drm_vblank_put(dev, intel_crtc->pipe);
4553
4554         if (work->event) {
4555                 e = work->event;
4556                 do_gettimeofday(&now);
4557                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4558                 e->event.tv_sec = now.tv_sec;
4559                 e->event.tv_usec = now.tv_usec;
4560                 list_add_tail(&e->base.link,
4561                               &e->base.file_priv->event_list);
4562                 wake_up_interruptible(&e->base.file_priv->event_wait);
4563         }
4564
4565         spin_unlock_irqrestore(&dev->event_lock, flags);
4566
4567         obj_priv = to_intel_bo(work->pending_flip_obj);
4568
4569         /* Initial scanout buffer will have a 0 pending flip count */
4570         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4571             atomic_dec_and_test(&obj_priv->pending_flip))
4572                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4573         schedule_work(&work->work);
4574 }
4575
4576 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4577 {
4578         drm_i915_private_t *dev_priv = dev->dev_private;
4579         struct intel_crtc *intel_crtc =
4580                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4581         unsigned long flags;
4582
4583         spin_lock_irqsave(&dev->event_lock, flags);
4584         if (intel_crtc->unpin_work) {
4585                 intel_crtc->unpin_work->pending = 1;
4586         } else {
4587                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4588         }
4589         spin_unlock_irqrestore(&dev->event_lock, flags);
4590 }
4591
4592 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4593                                 struct drm_framebuffer *fb,
4594                                 struct drm_pending_vblank_event *event)
4595 {
4596         struct drm_device *dev = crtc->dev;
4597         struct drm_i915_private *dev_priv = dev->dev_private;
4598         struct intel_framebuffer *intel_fb;
4599         struct drm_i915_gem_object *obj_priv;
4600         struct drm_gem_object *obj;
4601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4602         struct intel_unpin_work *work;
4603         unsigned long flags;
4604         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4605         int ret, pipesrc;
4606         RING_LOCALS;
4607
4608         work = kzalloc(sizeof *work, GFP_KERNEL);
4609         if (work == NULL)
4610                 return -ENOMEM;
4611
4612         mutex_lock(&dev->struct_mutex);
4613
4614         work->event = event;
4615         work->dev = crtc->dev;
4616         intel_fb = to_intel_framebuffer(crtc->fb);
4617         work->old_fb_obj = intel_fb->obj;
4618         INIT_WORK(&work->work, intel_unpin_work_fn);
4619
4620         /* We borrow the event spin lock for protecting unpin_work */
4621         spin_lock_irqsave(&dev->event_lock, flags);
4622         if (intel_crtc->unpin_work) {
4623                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4624                 spin_unlock_irqrestore(&dev->event_lock, flags);
4625                 kfree(work);
4626                 mutex_unlock(&dev->struct_mutex);
4627                 return -EBUSY;
4628         }
4629         intel_crtc->unpin_work = work;
4630         spin_unlock_irqrestore(&dev->event_lock, flags);
4631
4632         intel_fb = to_intel_framebuffer(fb);
4633         obj = intel_fb->obj;
4634
4635         ret = intel_pin_and_fence_fb_obj(dev, obj);
4636         if (ret != 0) {
4637                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4638                           to_intel_bo(obj));
4639                 kfree(work);
4640                 intel_crtc->unpin_work = NULL;
4641                 mutex_unlock(&dev->struct_mutex);
4642                 return ret;
4643         }
4644
4645         /* Reference the objects for the scheduled work. */
4646         drm_gem_object_reference(work->old_fb_obj);
4647         drm_gem_object_reference(obj);
4648
4649         crtc->fb = fb;
4650         i915_gem_object_flush_write_domain(obj);
4651         drm_vblank_get(dev, intel_crtc->pipe);
4652         obj_priv = to_intel_bo(obj);
4653         atomic_inc(&obj_priv->pending_flip);
4654         work->pending_flip_obj = obj;
4655
4656         BEGIN_LP_RING(4);
4657         OUT_RING(MI_DISPLAY_FLIP |
4658                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4659         OUT_RING(fb->pitch);
4660         if (IS_I965G(dev)) {
4661                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4662                 pipesrc = I915_READ(pipesrc_reg);
4663                 OUT_RING(pipesrc & 0x0fff0fff);
4664         } else {
4665                 OUT_RING(obj_priv->gtt_offset);
4666                 OUT_RING(MI_NOOP);
4667         }
4668         ADVANCE_LP_RING();
4669
4670         mutex_unlock(&dev->struct_mutex);
4671
4672         return 0;
4673 }
4674
4675 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4676         .dpms = intel_crtc_dpms,
4677         .mode_fixup = intel_crtc_mode_fixup,
4678         .mode_set = intel_crtc_mode_set,
4679         .mode_set_base = intel_pipe_set_base,
4680         .prepare = intel_crtc_prepare,
4681         .commit = intel_crtc_commit,
4682         .load_lut = intel_crtc_load_lut,
4683 };
4684
4685 static const struct drm_crtc_funcs intel_crtc_funcs = {
4686         .cursor_set = intel_crtc_cursor_set,
4687         .cursor_move = intel_crtc_cursor_move,
4688         .gamma_set = intel_crtc_gamma_set,
4689         .set_config = drm_crtc_helper_set_config,
4690         .destroy = intel_crtc_destroy,
4691         .page_flip = intel_crtc_page_flip,
4692 };
4693
4694
4695 static void intel_crtc_init(struct drm_device *dev, int pipe)
4696 {
4697         drm_i915_private_t *dev_priv = dev->dev_private;
4698         struct intel_crtc *intel_crtc;
4699         int i;
4700
4701         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4702         if (intel_crtc == NULL)
4703                 return;
4704
4705         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4706
4707         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4708         intel_crtc->pipe = pipe;
4709         intel_crtc->plane = pipe;
4710         for (i = 0; i < 256; i++) {
4711                 intel_crtc->lut_r[i] = i;
4712                 intel_crtc->lut_g[i] = i;
4713                 intel_crtc->lut_b[i] = i;
4714         }
4715
4716         /* Swap pipes & planes for FBC on pre-965 */
4717         intel_crtc->pipe = pipe;
4718         intel_crtc->plane = pipe;
4719         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4720                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4721                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4722         }
4723
4724         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4725                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4726         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4727         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4728
4729         intel_crtc->cursor_addr = 0;
4730         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4731         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4732
4733         intel_crtc->busy = false;
4734
4735         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4736                     (unsigned long)intel_crtc);
4737 }
4738
4739 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4740                                 struct drm_file *file_priv)
4741 {
4742         drm_i915_private_t *dev_priv = dev->dev_private;
4743         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4744         struct drm_mode_object *drmmode_obj;
4745         struct intel_crtc *crtc;
4746
4747         if (!dev_priv) {
4748                 DRM_ERROR("called with no initialization\n");
4749                 return -EINVAL;
4750         }
4751
4752         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4753                         DRM_MODE_OBJECT_CRTC);
4754
4755         if (!drmmode_obj) {
4756                 DRM_ERROR("no such CRTC id\n");
4757                 return -EINVAL;
4758         }
4759
4760         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4761         pipe_from_crtc_id->pipe = crtc->pipe;
4762
4763         return 0;
4764 }
4765
4766 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4767 {
4768         struct drm_crtc *crtc = NULL;
4769
4770         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4771                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4772                 if (intel_crtc->pipe == pipe)
4773                         break;
4774         }
4775         return crtc;
4776 }
4777
4778 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4779 {
4780         int index_mask = 0;
4781         struct drm_encoder *encoder;
4782         int entry = 0;
4783
4784         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4785                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4786                 if (type_mask & intel_encoder->clone_mask)
4787                         index_mask |= (1 << entry);
4788                 entry++;
4789         }
4790         return index_mask;
4791 }
4792
4793
4794 static void intel_setup_outputs(struct drm_device *dev)
4795 {
4796         struct drm_i915_private *dev_priv = dev->dev_private;
4797         struct drm_encoder *encoder;
4798
4799         intel_crt_init(dev);
4800
4801         /* Set up integrated LVDS */
4802         if (IS_MOBILE(dev) && !IS_I830(dev))
4803                 intel_lvds_init(dev);
4804
4805         if (HAS_PCH_SPLIT(dev)) {
4806                 int found;
4807
4808                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4809                         intel_dp_init(dev, DP_A);
4810
4811                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4812                         /* PCH SDVOB multiplex with HDMIB */
4813                         found = intel_sdvo_init(dev, PCH_SDVOB);
4814                         if (!found)
4815                                 intel_hdmi_init(dev, HDMIB);
4816                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4817                                 intel_dp_init(dev, PCH_DP_B);
4818                 }
4819
4820                 if (I915_READ(HDMIC) & PORT_DETECTED)
4821                         intel_hdmi_init(dev, HDMIC);
4822
4823                 if (I915_READ(HDMID) & PORT_DETECTED)
4824                         intel_hdmi_init(dev, HDMID);
4825
4826                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4827                         intel_dp_init(dev, PCH_DP_C);
4828
4829                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4830                         intel_dp_init(dev, PCH_DP_D);
4831
4832         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4833                 bool found = false;
4834
4835                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4836                         DRM_DEBUG_KMS("probing SDVOB\n");
4837                         found = intel_sdvo_init(dev, SDVOB);
4838                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4839                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4840                                 intel_hdmi_init(dev, SDVOB);
4841                         }
4842
4843                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4844                                 DRM_DEBUG_KMS("probing DP_B\n");
4845                                 intel_dp_init(dev, DP_B);
4846                         }
4847                 }
4848
4849                 /* Before G4X SDVOC doesn't have its own detect register */
4850
4851                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4852                         DRM_DEBUG_KMS("probing SDVOC\n");
4853                         found = intel_sdvo_init(dev, SDVOC);
4854                 }
4855
4856                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4857
4858                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4859                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4860                                 intel_hdmi_init(dev, SDVOC);
4861                         }
4862                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4863                                 DRM_DEBUG_KMS("probing DP_C\n");
4864                                 intel_dp_init(dev, DP_C);
4865                         }
4866                 }
4867
4868                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4869                     (I915_READ(DP_D) & DP_DETECTED)) {
4870                         DRM_DEBUG_KMS("probing DP_D\n");
4871                         intel_dp_init(dev, DP_D);
4872                 }
4873         } else if (IS_GEN2(dev))
4874                 intel_dvo_init(dev);
4875
4876         if (SUPPORTS_TV(dev))
4877                 intel_tv_init(dev);
4878
4879         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4880                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4881
4882                 encoder->possible_crtcs = intel_encoder->crtc_mask;
4883                 encoder->possible_clones = intel_encoder_clones(dev,
4884                                                 intel_encoder->clone_mask);
4885         }
4886 }
4887
4888 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4889 {
4890         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4891         struct drm_device *dev = fb->dev;
4892
4893         if (fb->fbdev)
4894                 intelfb_remove(dev, fb);
4895
4896         drm_framebuffer_cleanup(fb);
4897         drm_gem_object_unreference_unlocked(intel_fb->obj);
4898
4899         kfree(intel_fb);
4900 }
4901
4902 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4903                                                 struct drm_file *file_priv,
4904                                                 unsigned int *handle)
4905 {
4906         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4907         struct drm_gem_object *object = intel_fb->obj;
4908
4909         return drm_gem_handle_create(file_priv, object, handle);
4910 }
4911
4912 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4913         .destroy = intel_user_framebuffer_destroy,
4914         .create_handle = intel_user_framebuffer_create_handle,
4915 };
4916
4917 int intel_framebuffer_create(struct drm_device *dev,
4918                              struct drm_mode_fb_cmd *mode_cmd,
4919                              struct drm_framebuffer **fb,
4920                              struct drm_gem_object *obj)
4921 {
4922         struct intel_framebuffer *intel_fb;
4923         int ret;
4924
4925         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4926         if (!intel_fb)
4927                 return -ENOMEM;
4928
4929         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4930         if (ret) {
4931                 DRM_ERROR("framebuffer init failed %d\n", ret);
4932                 return ret;
4933         }
4934
4935         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4936
4937         intel_fb->obj = obj;
4938
4939         *fb = &intel_fb->base;
4940
4941         return 0;
4942 }
4943
4944
4945 static struct drm_framebuffer *
4946 intel_user_framebuffer_create(struct drm_device *dev,
4947                               struct drm_file *filp,
4948                               struct drm_mode_fb_cmd *mode_cmd)
4949 {
4950         struct drm_gem_object *obj;
4951         struct drm_framebuffer *fb;
4952         int ret;
4953
4954         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4955         if (!obj)
4956                 return NULL;
4957
4958         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4959         if (ret) {
4960                 drm_gem_object_unreference_unlocked(obj);
4961                 return NULL;
4962         }
4963
4964         return fb;
4965 }
4966
4967 static const struct drm_mode_config_funcs intel_mode_funcs = {
4968         .fb_create = intel_user_framebuffer_create,
4969         .fb_changed = intelfb_probe,
4970 };
4971
4972 static struct drm_gem_object *
4973 intel_alloc_power_context(struct drm_device *dev)
4974 {
4975         struct drm_gem_object *pwrctx;
4976         int ret;
4977
4978         pwrctx = drm_gem_object_alloc(dev, 4096);
4979         if (!pwrctx) {
4980                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4981                 return NULL;
4982         }
4983
4984         mutex_lock(&dev->struct_mutex);
4985         ret = i915_gem_object_pin(pwrctx, 4096);
4986         if (ret) {
4987                 DRM_ERROR("failed to pin power context: %d\n", ret);
4988                 goto err_unref;
4989         }
4990
4991         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4992         if (ret) {
4993                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4994                 goto err_unpin;
4995         }
4996         mutex_unlock(&dev->struct_mutex);
4997
4998         return pwrctx;
4999
5000 err_unpin:
5001         i915_gem_object_unpin(pwrctx);
5002 err_unref:
5003         drm_gem_object_unreference(pwrctx);
5004         mutex_unlock(&dev->struct_mutex);
5005         return NULL;
5006 }
5007
5008 void ironlake_enable_drps(struct drm_device *dev)
5009 {
5010         struct drm_i915_private *dev_priv = dev->dev_private;
5011         u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
5012         u8 fmax, fmin, fstart, vstart;
5013         int i = 0;
5014
5015         /* 100ms RC evaluation intervals */
5016         I915_WRITE(RCUPEI, 100000);
5017         I915_WRITE(RCDNEI, 100000);
5018
5019         /* Set max/min thresholds to 90ms and 80ms respectively */
5020         I915_WRITE(RCBMAXAVG, 90000);
5021         I915_WRITE(RCBMINAVG, 80000);
5022
5023         I915_WRITE(MEMIHYST, 1);
5024
5025         /* Set up min, max, and cur for interrupt handling */
5026         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5027         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5028         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5029                 MEMMODE_FSTART_SHIFT;
5030         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5031                 PXVFREQ_PX_SHIFT;
5032
5033         dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
5034         dev_priv->min_delay = fmin;
5035         dev_priv->cur_delay = fstart;
5036
5037         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5038
5039         /*
5040          * Interrupts will be enabled in ironlake_irq_postinstall
5041          */
5042
5043         I915_WRITE(VIDSTART, vstart);
5044         POSTING_READ(VIDSTART);
5045
5046         rgvmodectl |= MEMMODE_SWMODE_EN;
5047         I915_WRITE(MEMMODECTL, rgvmodectl);
5048
5049         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5050                 if (i++ > 100) {
5051                         DRM_ERROR("stuck trying to change perf mode\n");
5052                         break;
5053                 }
5054                 msleep(1);
5055         }
5056         msleep(1);
5057
5058         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5059                 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5060         I915_WRITE(MEMSWCTL, rgvswctl);
5061         POSTING_READ(MEMSWCTL);
5062
5063         rgvswctl |= MEMCTL_CMD_STS;
5064         I915_WRITE(MEMSWCTL, rgvswctl);
5065 }
5066
5067 void ironlake_disable_drps(struct drm_device *dev)
5068 {
5069         struct drm_i915_private *dev_priv = dev->dev_private;
5070         u32 rgvswctl;
5071         u8 fstart;
5072
5073         /* Ack interrupts, disable EFC interrupt */
5074         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5075         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5076         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5077         I915_WRITE(DEIIR, DE_PCU_EVENT);
5078         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5079
5080         /* Go back to the starting frequency */
5081         fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
5082                 MEMMODE_FSTART_SHIFT;
5083         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5084                 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5085         I915_WRITE(MEMSWCTL, rgvswctl);
5086         msleep(1);
5087         rgvswctl |= MEMCTL_CMD_STS;
5088         I915_WRITE(MEMSWCTL, rgvswctl);
5089         msleep(1);
5090
5091 }
5092
5093 void intel_init_clock_gating(struct drm_device *dev)
5094 {
5095         struct drm_i915_private *dev_priv = dev->dev_private;
5096
5097         /*
5098          * Disable clock gating reported to work incorrectly according to the
5099          * specs, but enable as much else as we can.
5100          */
5101         if (HAS_PCH_SPLIT(dev)) {
5102                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5103
5104                 if (IS_IRONLAKE(dev)) {
5105                         /* Required for FBC */
5106                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5107                         /* Required for CxSR */
5108                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5109
5110                         I915_WRITE(PCH_3DCGDIS0,
5111                                    MARIUNIT_CLOCK_GATE_DISABLE |
5112                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5113                 }
5114
5115                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5116
5117                 /*
5118                  * According to the spec the following bits should be set in
5119                  * order to enable memory self-refresh
5120                  * The bit 22/21 of 0x42004
5121                  * The bit 5 of 0x42020
5122                  * The bit 15 of 0x45000
5123                  */
5124                 if (IS_IRONLAKE(dev)) {
5125                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5126                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5127                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5128                         I915_WRITE(ILK_DSPCLK_GATE,
5129                                         (I915_READ(ILK_DSPCLK_GATE) |
5130                                                 ILK_DPARB_CLK_GATE));
5131                         I915_WRITE(DISP_ARB_CTL,
5132                                         (I915_READ(DISP_ARB_CTL) |
5133                                                 DISP_FBC_WM_DIS));
5134                 }
5135                 return;
5136         } else if (IS_G4X(dev)) {
5137                 uint32_t dspclk_gate;
5138                 I915_WRITE(RENCLK_GATE_D1, 0);
5139                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5140                        GS_UNIT_CLOCK_GATE_DISABLE |
5141                        CL_UNIT_CLOCK_GATE_DISABLE);
5142                 I915_WRITE(RAMCLK_GATE_D, 0);
5143                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5144                         OVRUNIT_CLOCK_GATE_DISABLE |
5145                         OVCUNIT_CLOCK_GATE_DISABLE;
5146                 if (IS_GM45(dev))
5147                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5148                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5149         } else if (IS_I965GM(dev)) {
5150                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5151                 I915_WRITE(RENCLK_GATE_D2, 0);
5152                 I915_WRITE(DSPCLK_GATE_D, 0);
5153                 I915_WRITE(RAMCLK_GATE_D, 0);
5154                 I915_WRITE16(DEUC, 0);
5155         } else if (IS_I965G(dev)) {
5156                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5157                        I965_RCC_CLOCK_GATE_DISABLE |
5158                        I965_RCPB_CLOCK_GATE_DISABLE |
5159                        I965_ISC_CLOCK_GATE_DISABLE |
5160                        I965_FBC_CLOCK_GATE_DISABLE);
5161                 I915_WRITE(RENCLK_GATE_D2, 0);
5162         } else if (IS_I9XX(dev)) {
5163                 u32 dstate = I915_READ(D_STATE);
5164
5165                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5166                         DSTATE_DOT_CLOCK_GATING;
5167                 I915_WRITE(D_STATE, dstate);
5168         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5169                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5170         } else if (IS_I830(dev)) {
5171                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5172         }
5173
5174         /*
5175          * GPU can automatically power down the render unit if given a page
5176          * to save state.
5177          */
5178         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5179                 struct drm_i915_gem_object *obj_priv = NULL;
5180
5181                 if (dev_priv->pwrctx) {
5182                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5183                 } else {
5184                         struct drm_gem_object *pwrctx;
5185
5186                         pwrctx = intel_alloc_power_context(dev);
5187                         if (pwrctx) {
5188                                 dev_priv->pwrctx = pwrctx;
5189                                 obj_priv = to_intel_bo(pwrctx);
5190                         }
5191                 }
5192
5193                 if (obj_priv) {
5194                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5195                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5196                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5197                 }
5198         }
5199 }
5200
5201 /* Set up chip specific display functions */
5202 static void intel_init_display(struct drm_device *dev)
5203 {
5204         struct drm_i915_private *dev_priv = dev->dev_private;
5205
5206         /* We always want a DPMS function */
5207         if (HAS_PCH_SPLIT(dev))
5208                 dev_priv->display.dpms = ironlake_crtc_dpms;
5209         else
5210                 dev_priv->display.dpms = i9xx_crtc_dpms;
5211
5212         /* Only mobile has FBC, leave pointers NULL for other chips */
5213         if (IS_MOBILE(dev)) {
5214                 if (IS_GM45(dev)) {
5215                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5216                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5217                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5218                 } else if (IS_I965GM(dev)) {
5219                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5220                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5221                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5222                 }
5223                 /* 855GM needs testing */
5224         }
5225
5226         /* Returns the core display clock speed */
5227         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5228                 dev_priv->display.get_display_clock_speed =
5229                         i945_get_display_clock_speed;
5230         else if (IS_I915G(dev))
5231                 dev_priv->display.get_display_clock_speed =
5232                         i915_get_display_clock_speed;
5233         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5234                 dev_priv->display.get_display_clock_speed =
5235                         i9xx_misc_get_display_clock_speed;
5236         else if (IS_I915GM(dev))
5237                 dev_priv->display.get_display_clock_speed =
5238                         i915gm_get_display_clock_speed;
5239         else if (IS_I865G(dev))
5240                 dev_priv->display.get_display_clock_speed =
5241                         i865_get_display_clock_speed;
5242         else if (IS_I85X(dev))
5243                 dev_priv->display.get_display_clock_speed =
5244                         i855_get_display_clock_speed;
5245         else /* 852, 830 */
5246                 dev_priv->display.get_display_clock_speed =
5247                         i830_get_display_clock_speed;
5248
5249         /* For FIFO watermark updates */
5250         if (HAS_PCH_SPLIT(dev)) {
5251                 if (IS_IRONLAKE(dev)) {
5252                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5253                                 dev_priv->display.update_wm = ironlake_update_wm;
5254                         else {
5255                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5256                                               "Disable CxSR\n");
5257                                 dev_priv->display.update_wm = NULL;
5258                         }
5259                 } else
5260                         dev_priv->display.update_wm = NULL;
5261         } else if (IS_PINEVIEW(dev)) {
5262                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5263                                             dev_priv->fsb_freq,
5264                                             dev_priv->mem_freq)) {
5265                         DRM_INFO("failed to find known CxSR latency "
5266                                  "(found fsb freq %d, mem freq %d), "
5267                                  "disabling CxSR\n",
5268                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5269                         /* Disable CxSR and never update its watermark again */
5270                         pineview_disable_cxsr(dev);
5271                         dev_priv->display.update_wm = NULL;
5272                 } else
5273                         dev_priv->display.update_wm = pineview_update_wm;
5274         } else if (IS_G4X(dev))
5275                 dev_priv->display.update_wm = g4x_update_wm;
5276         else if (IS_I965G(dev))
5277                 dev_priv->display.update_wm = i965_update_wm;
5278         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
5279                 dev_priv->display.update_wm = i9xx_update_wm;
5280                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5281         } else {
5282                 if (IS_I85X(dev))
5283                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5284                 else if (IS_845G(dev))
5285                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5286                 else
5287                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5288                 dev_priv->display.update_wm = i830_update_wm;
5289         }
5290 }
5291
5292 void intel_modeset_init(struct drm_device *dev)
5293 {
5294         struct drm_i915_private *dev_priv = dev->dev_private;
5295         int num_pipe;
5296         int i;
5297
5298         drm_mode_config_init(dev);
5299
5300         dev->mode_config.min_width = 0;
5301         dev->mode_config.min_height = 0;
5302
5303         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5304
5305         intel_init_display(dev);
5306
5307         if (IS_I965G(dev)) {
5308                 dev->mode_config.max_width = 8192;
5309                 dev->mode_config.max_height = 8192;
5310         } else if (IS_I9XX(dev)) {
5311                 dev->mode_config.max_width = 4096;
5312                 dev->mode_config.max_height = 4096;
5313         } else {
5314                 dev->mode_config.max_width = 2048;
5315                 dev->mode_config.max_height = 2048;
5316         }
5317
5318         /* set memory base */
5319         if (IS_I9XX(dev))
5320                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5321         else
5322                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5323
5324         if (IS_MOBILE(dev) || IS_I9XX(dev))
5325                 num_pipe = 2;
5326         else
5327                 num_pipe = 1;
5328         DRM_DEBUG_KMS("%d display pipe%s available.\n",
5329                   num_pipe, num_pipe > 1 ? "s" : "");
5330
5331         for (i = 0; i < num_pipe; i++) {
5332                 intel_crtc_init(dev, i);
5333         }
5334
5335         intel_setup_outputs(dev);
5336
5337         intel_init_clock_gating(dev);
5338
5339         if (IS_IRONLAKE_M(dev))
5340                 ironlake_enable_drps(dev);
5341
5342         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5343         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5344                     (unsigned long)dev);
5345
5346         intel_setup_overlay(dev);
5347 }
5348
5349 void intel_modeset_cleanup(struct drm_device *dev)
5350 {
5351         struct drm_i915_private *dev_priv = dev->dev_private;
5352         struct drm_crtc *crtc;
5353         struct intel_crtc *intel_crtc;
5354
5355         mutex_lock(&dev->struct_mutex);
5356
5357         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5358                 /* Skip inactive CRTCs */
5359                 if (!crtc->fb)
5360                         continue;
5361
5362                 intel_crtc = to_intel_crtc(crtc);
5363                 intel_increase_pllclock(crtc, false);
5364                 del_timer_sync(&intel_crtc->idle_timer);
5365         }
5366
5367         del_timer_sync(&dev_priv->idle_timer);
5368
5369         if (dev_priv->display.disable_fbc)
5370                 dev_priv->display.disable_fbc(dev);
5371
5372         if (dev_priv->pwrctx) {
5373                 struct drm_i915_gem_object *obj_priv;
5374
5375                 obj_priv = to_intel_bo(dev_priv->pwrctx);
5376                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5377                 I915_READ(PWRCTXA);
5378                 i915_gem_object_unpin(dev_priv->pwrctx);
5379                 drm_gem_object_unreference(dev_priv->pwrctx);
5380         }
5381
5382         if (IS_IRONLAKE_M(dev))
5383                 ironlake_disable_drps(dev);
5384
5385         mutex_unlock(&dev->struct_mutex);
5386
5387         drm_mode_config_cleanup(dev);
5388 }
5389
5390
5391 /*
5392  * Return which encoder is currently attached for connector.
5393  */
5394 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5395 {
5396         struct drm_mode_object *obj;
5397         struct drm_encoder *encoder;
5398         int i;
5399
5400         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5401                 if (connector->encoder_ids[i] == 0)
5402                         break;
5403
5404                 obj = drm_mode_object_find(connector->dev,
5405                                            connector->encoder_ids[i],
5406                                            DRM_MODE_OBJECT_ENCODER);
5407                 if (!obj)
5408                         continue;
5409
5410                 encoder = obj_to_encoder(obj);
5411                 return encoder;
5412         }
5413         return NULL;
5414 }
5415
5416 /*
5417  * set vga decode state - true == enable VGA decode
5418  */
5419 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5420 {
5421         struct drm_i915_private *dev_priv = dev->dev_private;
5422         u16 gmch_ctrl;
5423
5424         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5425         if (state)
5426                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5427         else
5428                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5429         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5430         return 0;
5431 }