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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 710              clock.m1++) {
 711                 for (clock.m2 = limit->m2.min;
 712                      clock.m2 <= limit->m2.max; clock.m2++) {
 713                         /* m1 is always 0 in IGD */
 714                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 715                                 break;
 716                         for (clock.n = limit->n.min;
 717                              clock.n <= limit->n.max; clock.n++) {
 718                                 for (clock.p1 = limit->p1.min;
 719                                         clock.p1 <= limit->p1.max; clock.p1++) {
 720                                         int this_err;
 721
 722                                         intel_clock(dev, refclk, &clock);
 723
 724                                         if (!intel_PLL_is_valid(crtc, &clock))
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740
 741 static bool
 742 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 743                             int target, int refclk, intel_clock_t *best_clock)
 744
 745 {
 746         struct drm_device *dev = crtc->dev;
 747         intel_clock_t clock;
 748         int err = target;
 749         bool found = false;
 750
 751         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 752
 753         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 754                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 755                         /* m1 is always 0 in IGD */
 756                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 757                                 break;
 758                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 759                              clock.n++) {
 760                                 int this_err;
 761
 762                                 intel_clock(dev, refclk, &clock);
 763
 764                                 if (!intel_PLL_is_valid(crtc, &clock))
 765                                         continue;
 766
 767                                 this_err = abs(clock.dot - target);
 768                                 if (this_err < err) {
 769                                         *best_clock = clock;
 770                                         err = this_err;
 771                                         found = true;
 772                                 }
 773                         }
 774                 }
 775         }
 776
 777         return found;
 778 }
 779
 780 static bool
 781 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 782                         int target, int refclk, intel_clock_t *best_clock)
 783 {
 784         struct drm_device *dev = crtc->dev;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         intel_clock_t clock;
 787         int max_n;
 788         bool found;
 789         /* approximately equals target * 0.00488 */
 790         int err_most = (target >> 8) + (target >> 10);
 791         found = false;
 792
 793         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 794                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 795                     LVDS_CLKB_POWER_UP)
 796                         clock.p2 = limit->p2.p2_fast;
 797                 else
 798                         clock.p2 = limit->p2.p2_slow;
 799         } else {
 800                 if (target < limit->p2.dot_limit)
 801                         clock.p2 = limit->p2.p2_slow;
 802                 else
 803                         clock.p2 = limit->p2.p2_fast;
 804         }
 805
 806         memset(best_clock, 0, sizeof(*best_clock));
 807         max_n = limit->n.max;
 808         /* based on hardware requriment prefer smaller n to precision */
 809         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 810                 /* based on hardware requirment prefere larger m1,m2 */
 811                 for (clock.m1 = limit->m1.max;
 812                      clock.m1 >= limit->m1.min; clock.m1--) {
 813                         for (clock.m2 = limit->m2.max;
 814                              clock.m2 >= limit->m2.min; clock.m2--) {
 815                                 for (clock.p1 = limit->p1.max;
 816                                      clock.p1 >= limit->p1.min; clock.p1--) {
 817                                         int this_err;
 818
 819                                         intel_clock(dev, refclk, &clock);
 820                                         if (!intel_PLL_is_valid(crtc, &clock))
 821                                                 continue;
 822                                         this_err = abs(clock.dot - target) ;
 823                                         if (this_err < err_most) {
 824                                                 *best_clock = clock;
 825                                                 err_most = this_err;
 826                                                 max_n = clock.n;
 827                                                 found = true;
 828                                         }
 829                                 }
 830                         }
 831                 }
 832         }
 833         return found;
 834 }
 835
 836 static bool
 837 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 838                       int target, int refclk, intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->dev;
 841         intel_clock_t clock;
 842         if (target < 200000) {
 843                 clock.n = 1;
 844                 clock.p1 = 2;
 845                 clock.p2 = 10;
 846                 clock.m1 = 12;
 847                 clock.m2 = 9;
 848         } else {
 849                 clock.n = 2;
 850                 clock.p1 = 1;
 851                 clock.p2 = 10;
 852                 clock.m1 = 14;
 853                 clock.m2 = 8;
 854         }
 855         intel_clock(dev, refclk, &clock);
 856         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 857         return true;
 858 }
 859
 860 static bool
 861 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 862                         int target, int refclk, intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc->dev;
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         intel_clock_t clock;
 867         int err_most = 47;
 868         int err_min = 10000;
 869
 870         /* eDP has only 2 clock choice, no n/m/p setting */
 871         if (HAS_eDP)
 872                 return true;
 873
 874         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 875                 return intel_find_pll_igdng_dp(limit, crtc, target,
 876                                                refclk, best_clock);
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 880                     LVDS_CLKB_POWER_UP)
 881                         clock.p2 = limit->p2.p2_fast;
 882                 else
 883                         clock.p2 = limit->p2.p2_slow;
 884         } else {
 885                 if (target < limit->p2.dot_limit)
 886                         clock.p2 = limit->p2.p2_slow;
 887                 else
 888                         clock.p2 = limit->p2.p2_fast;
 889         }
 890
 891         memset(best_clock, 0, sizeof(*best_clock));
 892         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 893                 /* based on hardware requriment prefer smaller n to precision */
 894                 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
 895                         /* based on hardware requirment prefere larger m1,m2 */
 896                         for (clock.m1 = limit->m1.max;
 897                              clock.m1 >= limit->m1.min; clock.m1--) {
 898                                 for (clock.m2 = limit->m2.max;
 899                                      clock.m2 >= limit->m2.min; clock.m2--) {
 900                                         int this_err;
 901
 902                                         intel_clock(dev, refclk, &clock);
 903                                         if (!intel_PLL_is_valid(crtc, &clock))
 904                                                 continue;
 905                                         this_err = abs((10000 - (target*10000/clock.dot)));
 906                                         if (this_err < err_most) {
 907                                                 *best_clock = clock;
 908                                                 /* found on first matching */
 909                                                 goto out;
 910                                         } else if (this_err < err_min) {
 911                                                 *best_clock = clock;
 912                                                 err_min = this_err;
 913                                         }
 914                                 }
 915                         }
 916                 }
 917         }
 918 out:
 919         return true;
 920 }
 921
 922 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 923 static bool
 924 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 925                       int target, int refclk, intel_clock_t *best_clock)
 926 {
 927     intel_clock_t clock;
 928     if (target < 200000) {
 929         clock.p1 = 2;
 930         clock.p2 = 10;
 931         clock.n = 2;
 932         clock.m1 = 23;
 933         clock.m2 = 8;
 934     } else {
 935         clock.p1 = 1;
 936         clock.p2 = 10;
 937         clock.n = 1;
 938         clock.m1 = 14;
 939         clock.m2 = 2;
 940     }
 941     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 942     clock.p = (clock.p1 * clock.p2);
 943     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 944     clock.vco = 0;
 945     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 946     return true;
 947 }
 948
 949 void
 950 intel_wait_for_vblank(struct drm_device *dev)
 951 {
 952         /* Wait for 20ms, i.e. one cycle at 50hz. */
 953         msleep(20);
 954 }
 955
 956 /* Parameters have changed, update FBC info */
 957 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 958 {
 959         struct drm_device *dev = crtc->dev;
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         struct drm_framebuffer *fb = crtc->fb;
 962         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 963         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 965         int plane, i;
 966         u32 fbc_ctl, fbc_ctl2;
 967
 968         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 969
 970         if (fb->pitch < dev_priv->cfb_pitch)
 971                 dev_priv->cfb_pitch = fb->pitch;
 972
 973         /* FBC_CTL wants 64B units */
 974         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 975         dev_priv->cfb_fence = obj_priv->fence_reg;
 976         dev_priv->cfb_plane = intel_crtc->plane;
 977         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 978
 979         /* Clear old tags */
 980         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 981                 I915_WRITE(FBC_TAG + (i * 4), 0);
 982
 983         /* Set it up... */
 984         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 985         if (obj_priv->tiling_mode != I915_TILING_NONE)
 986                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 987         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 988         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 989
 990         /* enable it... */
 991         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 992         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 993         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 994         if (obj_priv->tiling_mode != I915_TILING_NONE)
 995                 fbc_ctl |= dev_priv->cfb_fence;
 996         I915_WRITE(FBC_CONTROL, fbc_ctl);
 997
 998         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
 999                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1000 }
1001
1002 void i8xx_disable_fbc(struct drm_device *dev)
1003 {
1004         struct drm_i915_private *dev_priv = dev->dev_private;
1005         u32 fbc_ctl;
1006
1007         if (!I915_HAS_FBC(dev))
1008                 return;
1009
1010         /* Disable compression */
1011         fbc_ctl = I915_READ(FBC_CONTROL);
1012         fbc_ctl &= ~FBC_CTL_EN;
1013         I915_WRITE(FBC_CONTROL, fbc_ctl);
1014
1015         /* Wait for compressing bit to clear */
1016         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1017                 ; /* nothing */
1018
1019         intel_wait_for_vblank(dev);
1020
1021         DRM_DEBUG_KMS("disabled FBC\n");
1022 }
1023
1024 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1025 {
1026         struct drm_device *dev = crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028
1029         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1030 }
1031
1032 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1033 {
1034         struct drm_device *dev = crtc->dev;
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         struct drm_framebuffer *fb = crtc->fb;
1037         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1038         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1040         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1041                      DPFC_CTL_PLANEB);
1042         unsigned long stall_watermark = 200;
1043         u32 dpfc_ctl;
1044
1045         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1046         dev_priv->cfb_fence = obj_priv->fence_reg;
1047         dev_priv->cfb_plane = intel_crtc->plane;
1048
1049         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1050         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1051                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1052                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1053         } else {
1054                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1055         }
1056
1057         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1058         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1059                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1060                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1061         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1062
1063         /* enable it... */
1064         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1065
1066         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1067 }
1068
1069 void g4x_disable_fbc(struct drm_device *dev)
1070 {
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         u32 dpfc_ctl;
1073
1074         /* Disable compression */
1075         dpfc_ctl = I915_READ(DPFC_CONTROL);
1076         dpfc_ctl &= ~DPFC_CTL_EN;
1077         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1078         intel_wait_for_vblank(dev);
1079
1080         DRM_DEBUG_KMS("disabled FBC\n");
1081 }
1082
1083 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1084 {
1085         struct drm_device *dev = crtc->dev;
1086         struct drm_i915_private *dev_priv = dev->dev_private;
1087
1088         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1089 }
1090
1091 /**
1092  * intel_update_fbc - enable/disable FBC as needed
1093  * @crtc: CRTC to point the compressor at
1094  * @mode: mode in use
1095  *
1096  * Set up the framebuffer compression hardware at mode set time.  We
1097  * enable it if possible:
1098  *   - plane A only (on pre-965)
1099  *   - no pixel mulitply/line duplication
1100  *   - no alpha buffer discard
1101  *   - no dual wide
1102  *   - framebuffer <= 2048 in width, 1536 in height
1103  *
1104  * We can't assume that any compression will take place (worst case),
1105  * so the compressed buffer has to be the same size as the uncompressed
1106  * one.  It also must reside (along with the line length buffer) in
1107  * stolen memory.
1108  *
1109  * We need to enable/disable FBC on a global basis.
1110  */
1111 static void intel_update_fbc(struct drm_crtc *crtc,
1112                              struct drm_display_mode *mode)
1113 {
1114         struct drm_device *dev = crtc->dev;
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         struct drm_framebuffer *fb = crtc->fb;
1117         struct intel_framebuffer *intel_fb;
1118         struct drm_i915_gem_object *obj_priv;
1119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1120         int plane = intel_crtc->plane;
1121
1122         if (!i915_powersave)
1123                 return;
1124
1125         if (!dev_priv->display.fbc_enabled ||
1126             !dev_priv->display.enable_fbc ||
1127             !dev_priv->display.disable_fbc)
1128                 return;
1129
1130         if (!crtc->fb)
1131                 return;
1132
1133         intel_fb = to_intel_framebuffer(fb);
1134         obj_priv = intel_fb->obj->driver_private;
1135
1136         /*
1137          * If FBC is already on, we just have to verify that we can
1138          * keep it that way...
1139          * Need to disable if:
1140          *   - changing FBC params (stride, fence, mode)
1141          *   - new fb is too large to fit in compressed buffer
1142          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1143          */
1144         if (intel_fb->obj->size > dev_priv->cfb_size) {
1145                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1146                                 "compression\n");
1147                 goto out_disable;
1148         }
1149         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1150             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1151                 DRM_DEBUG_KMS("mode incompatible with compression, "
1152                                 "disabling\n");
1153                 goto out_disable;
1154         }
1155         if ((mode->hdisplay > 2048) ||
1156             (mode->vdisplay > 1536)) {
1157                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1158                 goto out_disable;
1159         }
1160         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1161                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1162                 goto out_disable;
1163         }
1164         if (obj_priv->tiling_mode != I915_TILING_X) {
1165                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1166                 goto out_disable;
1167         }
1168
1169         if (dev_priv->display.fbc_enabled(crtc)) {
1170                 /* We can re-enable it in this case, but need to update pitch */
1171                 if (fb->pitch > dev_priv->cfb_pitch)
1172                         dev_priv->display.disable_fbc(dev);
1173                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1174                         dev_priv->display.disable_fbc(dev);
1175                 if (plane != dev_priv->cfb_plane)
1176                         dev_priv->display.disable_fbc(dev);
1177         }
1178
1179         if (!dev_priv->display.fbc_enabled(crtc)) {
1180                 /* Now try to turn it back on if possible */
1181                 dev_priv->display.enable_fbc(crtc, 500);
1182         }
1183
1184         return;
1185
1186 out_disable:
1187         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1188         /* Multiple disables should be harmless */
1189         if (dev_priv->display.fbc_enabled(crtc))
1190                 dev_priv->display.disable_fbc(dev);
1191 }
1192
1193 static int
1194 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1195 {
1196         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1197         u32 alignment;
1198         int ret;
1199
1200         switch (obj_priv->tiling_mode) {
1201         case I915_TILING_NONE:
1202                 alignment = 64 * 1024;
1203                 break;
1204         case I915_TILING_X:
1205                 /* pin() will align the object as required by fence */
1206                 alignment = 0;
1207                 break;
1208         case I915_TILING_Y:
1209                 /* FIXME: Is this true? */
1210                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1211                 return -EINVAL;
1212         default:
1213                 BUG();
1214         }
1215
1216         alignment = 256 * 1024;
1217         ret = i915_gem_object_pin(obj, alignment);
1218         if (ret != 0)
1219                 return ret;
1220
1221         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1222          * fence, whereas 965+ only requires a fence if using
1223          * framebuffer compression.  For simplicity, we always install
1224          * a fence as the cost is not that onerous.
1225          */
1226         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1227             obj_priv->tiling_mode != I915_TILING_NONE) {
1228                 ret = i915_gem_object_get_fence_reg(obj);
1229                 if (ret != 0) {
1230                         i915_gem_object_unpin(obj);
1231                         return ret;
1232                 }
1233         }
1234
1235         return 0;
1236 }
1237
1238 static int
1239 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1240                     struct drm_framebuffer *old_fb)
1241 {
1242         struct drm_device *dev = crtc->dev;
1243         struct drm_i915_private *dev_priv = dev->dev_private;
1244         struct drm_i915_master_private *master_priv;
1245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1246         struct intel_framebuffer *intel_fb;
1247         struct drm_i915_gem_object *obj_priv;
1248         struct drm_gem_object *obj;
1249         int pipe = intel_crtc->pipe;
1250         int plane = intel_crtc->plane;
1251         unsigned long Start, Offset;
1252         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1253         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1254         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1255         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1256         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1257         u32 dspcntr;
1258         int ret;
1259
1260         /* no fb bound */
1261         if (!crtc->fb) {
1262                 DRM_DEBUG_KMS("No FB bound\n");
1263                 return 0;
1264         }
1265
1266         switch (plane) {
1267         case 0:
1268         case 1:
1269                 break;
1270         default:
1271                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1272                 return -EINVAL;
1273         }
1274
1275         intel_fb = to_intel_framebuffer(crtc->fb);
1276         obj = intel_fb->obj;
1277         obj_priv = obj->driver_private;
1278
1279         mutex_lock(&dev->struct_mutex);
1280         ret = intel_pin_and_fence_fb_obj(dev, obj);
1281         if (ret != 0) {
1282                 mutex_unlock(&dev->struct_mutex);
1283                 return ret;
1284         }
1285
1286         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1287         if (ret != 0) {
1288                 i915_gem_object_unpin(obj);
1289                 mutex_unlock(&dev->struct_mutex);
1290                 return ret;
1291         }
1292
1293         dspcntr = I915_READ(dspcntr_reg);
1294         /* Mask out pixel format bits in case we change it */
1295         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1296         switch (crtc->fb->bits_per_pixel) {
1297         case 8:
1298                 dspcntr |= DISPPLANE_8BPP;
1299                 break;
1300         case 16:
1301                 if (crtc->fb->depth == 15)
1302                         dspcntr |= DISPPLANE_15_16BPP;
1303                 else
1304                         dspcntr |= DISPPLANE_16BPP;
1305                 break;
1306         case 24:
1307         case 32:
1308                 if (crtc->fb->depth == 30)
1309                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1310                 else
1311                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1312                 break;
1313         default:
1314                 DRM_ERROR("Unknown color depth\n");
1315                 i915_gem_object_unpin(obj);
1316                 mutex_unlock(&dev->struct_mutex);
1317                 return -EINVAL;
1318         }
1319         if (IS_I965G(dev)) {
1320                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1321                         dspcntr |= DISPPLANE_TILED;
1322                 else
1323                         dspcntr &= ~DISPPLANE_TILED;
1324         }
1325
1326         if (IS_IGDNG(dev))
1327                 /* must disable */
1328                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1329
1330         I915_WRITE(dspcntr_reg, dspcntr);
1331
1332         Start = obj_priv->gtt_offset;
1333         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1334
1335         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1336         I915_WRITE(dspstride, crtc->fb->pitch);
1337         if (IS_I965G(dev)) {
1338                 I915_WRITE(dspbase, Offset);
1339                 I915_READ(dspbase);
1340                 I915_WRITE(dspsurf, Start);
1341                 I915_READ(dspsurf);
1342                 I915_WRITE(dsptileoff, (y << 16) | x);
1343         } else {
1344                 I915_WRITE(dspbase, Start + Offset);
1345                 I915_READ(dspbase);
1346         }
1347
1348         if ((IS_I965G(dev) || plane == 0))
1349                 intel_update_fbc(crtc, &crtc->mode);
1350
1351         intel_wait_for_vblank(dev);
1352
1353         if (old_fb) {
1354                 intel_fb = to_intel_framebuffer(old_fb);
1355                 obj_priv = intel_fb->obj->driver_private;
1356                 i915_gem_object_unpin(intel_fb->obj);
1357         }
1358         intel_increase_pllclock(crtc, true);
1359
1360         mutex_unlock(&dev->struct_mutex);
1361
1362         if (!dev->primary->master)
1363                 return 0;
1364
1365         master_priv = dev->primary->master->driver_priv;
1366         if (!master_priv->sarea_priv)
1367                 return 0;
1368
1369         if (pipe) {
1370                 master_priv->sarea_priv->pipeB_x = x;
1371                 master_priv->sarea_priv->pipeB_y = y;
1372         } else {
1373                 master_priv->sarea_priv->pipeA_x = x;
1374                 master_priv->sarea_priv->pipeA_y = y;
1375         }
1376
1377         return 0;
1378 }
1379
1380 /* Disable the VGA plane that we never use */
1381 static void i915_disable_vga (struct drm_device *dev)
1382 {
1383         struct drm_i915_private *dev_priv = dev->dev_private;
1384         u8 sr1;
1385         u32 vga_reg;
1386
1387         if (IS_IGDNG(dev))
1388                 vga_reg = CPU_VGACNTRL;
1389         else
1390                 vga_reg = VGACNTRL;
1391
1392         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1393                 return;
1394
1395         I915_WRITE8(VGA_SR_INDEX, 1);
1396         sr1 = I915_READ8(VGA_SR_DATA);
1397         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1398         udelay(100);
1399
1400         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1401 }
1402
1403 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1404 {
1405         struct drm_device *dev = crtc->dev;
1406         struct drm_i915_private *dev_priv = dev->dev_private;
1407         u32 dpa_ctl;
1408
1409         DRM_DEBUG_KMS("\n");
1410         dpa_ctl = I915_READ(DP_A);
1411         dpa_ctl &= ~DP_PLL_ENABLE;
1412         I915_WRITE(DP_A, dpa_ctl);
1413 }
1414
1415 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1416 {
1417         struct drm_device *dev = crtc->dev;
1418         struct drm_i915_private *dev_priv = dev->dev_private;
1419         u32 dpa_ctl;
1420
1421         dpa_ctl = I915_READ(DP_A);
1422         dpa_ctl |= DP_PLL_ENABLE;
1423         I915_WRITE(DP_A, dpa_ctl);
1424         udelay(200);
1425 }
1426
1427
1428 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1429 {
1430         struct drm_device *dev = crtc->dev;
1431         struct drm_i915_private *dev_priv = dev->dev_private;
1432         u32 dpa_ctl;
1433
1434         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1435         dpa_ctl = I915_READ(DP_A);
1436         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1437
1438         if (clock < 200000) {
1439                 u32 temp;
1440                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1441                 /* workaround for 160Mhz:
1442                    1) program 0x4600c bits 15:0 = 0x8124
1443                    2) program 0x46010 bit 0 = 1
1444                    3) program 0x46034 bit 24 = 1
1445                    4) program 0x64000 bit 14 = 1
1446                    */
1447                 temp = I915_READ(0x4600c);
1448                 temp &= 0xffff0000;
1449                 I915_WRITE(0x4600c, temp | 0x8124);
1450
1451                 temp = I915_READ(0x46010);
1452                 I915_WRITE(0x46010, temp | 1);
1453
1454                 temp = I915_READ(0x46034);
1455                 I915_WRITE(0x46034, temp | (1 << 24));
1456         } else {
1457                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1458         }
1459         I915_WRITE(DP_A, dpa_ctl);
1460
1461         udelay(500);
1462 }
1463
1464 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1465 {
1466         struct drm_device *dev = crtc->dev;
1467         struct drm_i915_private *dev_priv = dev->dev_private;
1468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1469         int pipe = intel_crtc->pipe;
1470         int plane = intel_crtc->plane;
1471         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1472         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1473         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1474         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1475         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1476         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1477         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1478         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1479         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1480         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1481         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1482         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1483         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1484         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1485         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1486         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1487         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1488         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1489         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1490         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1491         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1492         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1493         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1494         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1495         u32 temp;
1496         int tries = 5, j, n;
1497
1498         /* XXX: When our outputs are all unaware of DPMS modes other than off
1499          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1500          */
1501         switch (mode) {
1502         case DRM_MODE_DPMS_ON:
1503         case DRM_MODE_DPMS_STANDBY:
1504         case DRM_MODE_DPMS_SUSPEND:
1505                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1506
1507                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1508                         temp = I915_READ(PCH_LVDS);
1509                         if ((temp & LVDS_PORT_EN) == 0) {
1510                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1511                                 POSTING_READ(PCH_LVDS);
1512                         }
1513                 }
1514
1515                 if (HAS_eDP) {
1516                         /* enable eDP PLL */
1517                         igdng_enable_pll_edp(crtc);
1518                 } else {
1519                         /* enable PCH DPLL */
1520                         temp = I915_READ(pch_dpll_reg);
1521                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1522                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1523                                 I915_READ(pch_dpll_reg);
1524                         }
1525
1526                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1527                         temp = I915_READ(fdi_rx_reg);
1528                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1529                                         FDI_SEL_PCDCLK |
1530                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1531                         I915_READ(fdi_rx_reg);
1532                         udelay(200);
1533
1534                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1535                         temp = I915_READ(fdi_tx_reg);
1536                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1537                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1538                                 I915_READ(fdi_tx_reg);
1539                                 udelay(100);
1540                         }
1541                 }
1542
1543                 /* Enable panel fitting for LVDS */
1544                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1545                         temp = I915_READ(pf_ctl_reg);
1546                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1547
1548                         /* currently full aspect */
1549                         I915_WRITE(pf_win_pos, 0);
1550
1551                         I915_WRITE(pf_win_size,
1552                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1553                                    (dev_priv->panel_fixed_mode->vdisplay));
1554                 }
1555
1556                 /* Enable CPU pipe */
1557                 temp = I915_READ(pipeconf_reg);
1558                 if ((temp & PIPEACONF_ENABLE) == 0) {
1559                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1560                         I915_READ(pipeconf_reg);
1561                         udelay(100);
1562                 }
1563
1564                 /* configure and enable CPU plane */
1565                 temp = I915_READ(dspcntr_reg);
1566                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1567                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1568                         /* Flush the plane changes */
1569                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1570                 }
1571
1572                 if (!HAS_eDP) {
1573                         /* enable CPU FDI TX and PCH FDI RX */
1574                         temp = I915_READ(fdi_tx_reg);
1575                         temp |= FDI_TX_ENABLE;
1576                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1577                         temp &= ~FDI_LINK_TRAIN_NONE;
1578                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1579                         I915_WRITE(fdi_tx_reg, temp);
1580                         I915_READ(fdi_tx_reg);
1581
1582                         temp = I915_READ(fdi_rx_reg);
1583                         temp &= ~FDI_LINK_TRAIN_NONE;
1584                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1585                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1586                         I915_READ(fdi_rx_reg);
1587
1588                         udelay(150);
1589
1590                         /* Train FDI. */
1591                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1592                            for train result */
1593                         temp = I915_READ(fdi_rx_imr_reg);
1594                         temp &= ~FDI_RX_SYMBOL_LOCK;
1595                         temp &= ~FDI_RX_BIT_LOCK;
1596                         I915_WRITE(fdi_rx_imr_reg, temp);
1597                         I915_READ(fdi_rx_imr_reg);
1598                         udelay(150);
1599
1600                         temp = I915_READ(fdi_rx_iir_reg);
1601                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1602
1603                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1604                                 for (j = 0; j < tries; j++) {
1605                                         temp = I915_READ(fdi_rx_iir_reg);
1606                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1607                                                                 temp);
1608                                         if (temp & FDI_RX_BIT_LOCK)
1609                                                 break;
1610                                         udelay(200);
1611                                 }
1612                                 if (j != tries)
1613                                         I915_WRITE(fdi_rx_iir_reg,
1614                                                         temp | FDI_RX_BIT_LOCK);
1615                                 else
1616                                         DRM_DEBUG_KMS("train 1 fail\n");
1617                         } else {
1618                                 I915_WRITE(fdi_rx_iir_reg,
1619                                                 temp | FDI_RX_BIT_LOCK);
1620                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1621                         }
1622                         temp = I915_READ(fdi_tx_reg);
1623                         temp &= ~FDI_LINK_TRAIN_NONE;
1624                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1625                         I915_WRITE(fdi_tx_reg, temp);
1626
1627                         temp = I915_READ(fdi_rx_reg);
1628                         temp &= ~FDI_LINK_TRAIN_NONE;
1629                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1630                         I915_WRITE(fdi_rx_reg, temp);
1631
1632                         udelay(150);
1633
1634                         temp = I915_READ(fdi_rx_iir_reg);
1635                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1636
1637                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1638                                 for (j = 0; j < tries; j++) {
1639                                         temp = I915_READ(fdi_rx_iir_reg);
1640                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1641                                                                 temp);
1642                                         if (temp & FDI_RX_SYMBOL_LOCK)
1643                                                 break;
1644                                         udelay(200);
1645                                 }
1646                                 if (j != tries) {
1647                                         I915_WRITE(fdi_rx_iir_reg,
1648                                                         temp | FDI_RX_SYMBOL_LOCK);
1649                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1650                                 } else
1651                                         DRM_DEBUG_KMS("train 2 fail\n");
1652                         } else {
1653                                 I915_WRITE(fdi_rx_iir_reg,
1654                                                 temp | FDI_RX_SYMBOL_LOCK);
1655                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1656                         }
1657                         DRM_DEBUG_KMS("train done\n");
1658
1659                         /* set transcoder timing */
1660                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1661                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1662                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1663
1664                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1665                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1666                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1667
1668                         /* enable PCH transcoder */
1669                         temp = I915_READ(transconf_reg);
1670                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1671                         I915_READ(transconf_reg);
1672
1673                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1674                                 ;
1675
1676                         /* enable normal */
1677
1678                         temp = I915_READ(fdi_tx_reg);
1679                         temp &= ~FDI_LINK_TRAIN_NONE;
1680                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1681                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1682                         I915_READ(fdi_tx_reg);
1683
1684                         temp = I915_READ(fdi_rx_reg);
1685                         temp &= ~FDI_LINK_TRAIN_NONE;
1686                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1687                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1688                         I915_READ(fdi_rx_reg);
1689
1690                         /* wait one idle pattern time */
1691                         udelay(100);
1692
1693                 }
1694
1695                 intel_crtc_load_lut(crtc);
1696
1697         break;
1698         case DRM_MODE_DPMS_OFF:
1699                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1700
1701                 /* Disable display plane */
1702                 temp = I915_READ(dspcntr_reg);
1703                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1704                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1705                         /* Flush the plane changes */
1706                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1707                         I915_READ(dspbase_reg);
1708                 }
1709
1710                 i915_disable_vga(dev);
1711
1712                 /* disable cpu pipe, disable after all planes disabled */
1713                 temp = I915_READ(pipeconf_reg);
1714                 if ((temp & PIPEACONF_ENABLE) != 0) {
1715                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1716                         I915_READ(pipeconf_reg);
1717                         n = 0;
1718                         /* wait for cpu pipe off, pipe state */
1719                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1720                                 n++;
1721                                 if (n < 60) {
1722                                         udelay(500);
1723                                         continue;
1724                                 } else {
1725                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1726                                                                 pipe);
1727                                         break;
1728                                 }
1729                         }
1730                 } else
1731                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1732
1733                 udelay(100);
1734
1735                 /* Disable PF */
1736                 temp = I915_READ(pf_ctl_reg);
1737                 if ((temp & PF_ENABLE) != 0) {
1738                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1739                         I915_READ(pf_ctl_reg);
1740                 }
1741                 I915_WRITE(pf_win_size, 0);
1742
1743                 /* disable CPU FDI tx and PCH FDI rx */
1744                 temp = I915_READ(fdi_tx_reg);
1745                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1746                 I915_READ(fdi_tx_reg);
1747
1748                 temp = I915_READ(fdi_rx_reg);
1749                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1750                 I915_READ(fdi_rx_reg);
1751
1752                 udelay(100);
1753
1754                 /* still set train pattern 1 */
1755                 temp = I915_READ(fdi_tx_reg);
1756                 temp &= ~FDI_LINK_TRAIN_NONE;
1757                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1758                 I915_WRITE(fdi_tx_reg, temp);
1759
1760                 temp = I915_READ(fdi_rx_reg);
1761                 temp &= ~FDI_LINK_TRAIN_NONE;
1762                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1763                 I915_WRITE(fdi_rx_reg, temp);
1764
1765                 udelay(100);
1766
1767                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1768                         temp = I915_READ(PCH_LVDS);
1769                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1770                         I915_READ(PCH_LVDS);
1771                         udelay(100);
1772                 }
1773
1774                 /* disable PCH transcoder */
1775                 temp = I915_READ(transconf_reg);
1776                 if ((temp & TRANS_ENABLE) != 0) {
1777                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1778                         I915_READ(transconf_reg);
1779                         n = 0;
1780                         /* wait for PCH transcoder off, transcoder state */
1781                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1782                                 n++;
1783                                 if (n < 60) {
1784                                         udelay(500);
1785                                         continue;
1786                                 } else {
1787                                         DRM_DEBUG_KMS("transcoder %d off "
1788                                                         "delay\n", pipe);
1789                                         break;
1790                                 }
1791                         }
1792                 }
1793
1794                 udelay(100);
1795
1796                 /* disable PCH DPLL */
1797                 temp = I915_READ(pch_dpll_reg);
1798                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1799                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1800                         I915_READ(pch_dpll_reg);
1801                 }
1802
1803                 if (HAS_eDP) {
1804                         igdng_disable_pll_edp(crtc);
1805                 }
1806
1807                 temp = I915_READ(fdi_rx_reg);
1808                 temp &= ~FDI_SEL_PCDCLK;
1809                 I915_WRITE(fdi_rx_reg, temp);
1810                 I915_READ(fdi_rx_reg);
1811
1812                 temp = I915_READ(fdi_rx_reg);
1813                 temp &= ~FDI_RX_PLL_ENABLE;
1814                 I915_WRITE(fdi_rx_reg, temp);
1815                 I915_READ(fdi_rx_reg);
1816
1817                 /* Disable CPU FDI TX PLL */
1818                 temp = I915_READ(fdi_tx_reg);
1819                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1820                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1821                         I915_READ(fdi_tx_reg);
1822                         udelay(100);
1823                 }
1824
1825                 /* Wait for the clocks to turn off. */
1826                 udelay(100);
1827                 break;
1828         }
1829 }
1830
1831 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1832 {
1833         struct intel_overlay *overlay;
1834         int ret;
1835
1836         if (!enable && intel_crtc->overlay) {
1837                 overlay = intel_crtc->overlay;
1838                 mutex_lock(&overlay->dev->struct_mutex);
1839                 for (;;) {
1840                         ret = intel_overlay_switch_off(overlay);
1841                         if (ret == 0)
1842                                 break;
1843
1844                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1845                         if (ret != 0) {
1846                                 /* overlay doesn't react anymore. Usually
1847                                  * results in a black screen and an unkillable
1848                                  * X server. */
1849                                 BUG();
1850                                 overlay->hw_wedged = HW_WEDGED;
1851                                 break;
1852                         }
1853                 }
1854                 mutex_unlock(&overlay->dev->struct_mutex);
1855         }
1856         /* Let userspace switch the overlay on again. In most cases userspace
1857          * has to recompute where to put it anyway. */
1858
1859         return;
1860 }
1861
1862 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1863 {
1864         struct drm_device *dev = crtc->dev;
1865         struct drm_i915_private *dev_priv = dev->dev_private;
1866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867         int pipe = intel_crtc->pipe;
1868         int plane = intel_crtc->plane;
1869         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1870         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1871         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1872         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1873         u32 temp;
1874
1875         /* XXX: When our outputs are all unaware of DPMS modes other than off
1876          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1877          */
1878         switch (mode) {
1879         case DRM_MODE_DPMS_ON:
1880         case DRM_MODE_DPMS_STANDBY:
1881         case DRM_MODE_DPMS_SUSPEND:
1882                 intel_update_watermarks(dev);
1883
1884                 /* Enable the DPLL */
1885                 temp = I915_READ(dpll_reg);
1886                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1887                         I915_WRITE(dpll_reg, temp);
1888                         I915_READ(dpll_reg);
1889                         /* Wait for the clocks to stabilize. */
1890                         udelay(150);
1891                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1892                         I915_READ(dpll_reg);
1893                         /* Wait for the clocks to stabilize. */
1894                         udelay(150);
1895                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1896                         I915_READ(dpll_reg);
1897                         /* Wait for the clocks to stabilize. */
1898                         udelay(150);
1899                 }
1900
1901                 /* Enable the pipe */
1902                 temp = I915_READ(pipeconf_reg);
1903                 if ((temp & PIPEACONF_ENABLE) == 0)
1904                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1905
1906                 /* Enable the plane */
1907                 temp = I915_READ(dspcntr_reg);
1908                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1909                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1910                         /* Flush the plane changes */
1911                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1912                 }
1913
1914                 intel_crtc_load_lut(crtc);
1915
1916                 if ((IS_I965G(dev) || plane == 0))
1917                         intel_update_fbc(crtc, &crtc->mode);
1918
1919                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1920                 intel_crtc_dpms_overlay(intel_crtc, true);
1921         break;
1922         case DRM_MODE_DPMS_OFF:
1923                 intel_update_watermarks(dev);
1924
1925                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1926                 intel_crtc_dpms_overlay(intel_crtc, false);
1927                 drm_vblank_off(dev, pipe);
1928
1929                 if (dev_priv->cfb_plane == plane &&
1930                     dev_priv->display.disable_fbc)
1931                         dev_priv->display.disable_fbc(dev);
1932
1933                 /* Disable the VGA plane that we never use */
1934                 i915_disable_vga(dev);
1935
1936                 /* Disable display plane */
1937                 temp = I915_READ(dspcntr_reg);
1938                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1939                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1940                         /* Flush the plane changes */
1941                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1942                         I915_READ(dspbase_reg);
1943                 }
1944
1945                 if (!IS_I9XX(dev)) {
1946                         /* Wait for vblank for the disable to take effect */
1947                         intel_wait_for_vblank(dev);
1948                 }
1949
1950                 /* Next, disable display pipes */
1951                 temp = I915_READ(pipeconf_reg);
1952                 if ((temp & PIPEACONF_ENABLE) != 0) {
1953                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1954                         I915_READ(pipeconf_reg);
1955                 }
1956
1957                 /* Wait for vblank for the disable to take effect. */
1958                 intel_wait_for_vblank(dev);
1959
1960                 temp = I915_READ(dpll_reg);
1961                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1962                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1963                         I915_READ(dpll_reg);
1964                 }
1965
1966                 /* Wait for the clocks to turn off. */
1967                 udelay(150);
1968                 break;
1969         }
1970 }
1971
1972 /**
1973  * Sets the power management mode of the pipe and plane.
1974  *
1975  * This code should probably grow support for turning the cursor off and back
1976  * on appropriately at the same time as we're turning the pipe off/on.
1977  */
1978 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1979 {
1980         struct drm_device *dev = crtc->dev;
1981         struct drm_i915_private *dev_priv = dev->dev_private;
1982         struct drm_i915_master_private *master_priv;
1983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984         int pipe = intel_crtc->pipe;
1985         bool enabled;
1986
1987         dev_priv->display.dpms(crtc, mode);
1988
1989         intel_crtc->dpms_mode = mode;
1990
1991         if (!dev->primary->master)
1992                 return;
1993
1994         master_priv = dev->primary->master->driver_priv;
1995         if (!master_priv->sarea_priv)
1996                 return;
1997
1998         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1999
2000         switch (pipe) {
2001         case 0:
2002                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2003                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2004                 break;
2005         case 1:
2006                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2007                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2008                 break;
2009         default:
2010                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2011                 break;
2012         }
2013 }
2014
2015 static void intel_crtc_prepare (struct drm_crtc *crtc)
2016 {
2017         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2018         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2019 }
2020
2021 static void intel_crtc_commit (struct drm_crtc *crtc)
2022 {
2023         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2024         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2025 }
2026
2027 void intel_encoder_prepare (struct drm_encoder *encoder)
2028 {
2029         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2030         /* lvds has its own version of prepare see intel_lvds_prepare */
2031         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2032 }
2033
2034 void intel_encoder_commit (struct drm_encoder *encoder)
2035 {
2036         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2037         /* lvds has its own version of commit see intel_lvds_commit */
2038         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2039 }
2040
2041 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2042                                   struct drm_display_mode *mode,
2043                                   struct drm_display_mode *adjusted_mode)
2044 {
2045         struct drm_device *dev = crtc->dev;
2046         if (IS_IGDNG(dev)) {
2047                 /* FDI link clock is fixed at 2.7G */
2048                 if (mode->clock * 3 > 27000 * 4)
2049                         return MODE_CLOCK_HIGH;
2050         }
2051         return true;
2052 }
2053
2054 static int i945_get_display_clock_speed(struct drm_device *dev)
2055 {
2056         return 400000;
2057 }
2058
2059 static int i915_get_display_clock_speed(struct drm_device *dev)
2060 {
2061         return 333000;
2062 }
2063
2064 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2065 {
2066         return 200000;
2067 }
2068
2069 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2070 {
2071         u16 gcfgc = 0;
2072
2073         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2074
2075         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2076                 return 133000;
2077         else {
2078                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2079                 case GC_DISPLAY_CLOCK_333_MHZ:
2080                         return 333000;
2081                 default:
2082                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2083                         return 190000;
2084                 }
2085         }
2086 }
2087
2088 static int i865_get_display_clock_speed(struct drm_device *dev)
2089 {
2090         return 266000;
2091 }
2092
2093 static int i855_get_display_clock_speed(struct drm_device *dev)
2094 {
2095         u16 hpllcc = 0;
2096         /* Assume that the hardware is in the high speed state.  This
2097          * should be the default.
2098          */
2099         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2100         case GC_CLOCK_133_200:
2101         case GC_CLOCK_100_200:
2102                 return 200000;
2103         case GC_CLOCK_166_250:
2104                 return 250000;
2105         case GC_CLOCK_100_133:
2106                 return 133000;
2107         }
2108
2109         /* Shouldn't happen */
2110         return 0;
2111 }
2112
2113 static int i830_get_display_clock_speed(struct drm_device *dev)
2114 {
2115         return 133000;
2116 }
2117
2118 /**
2119  * Return the pipe currently connected to the panel fitter,
2120  * or -1 if the panel fitter is not present or not in use
2121  */
2122 int intel_panel_fitter_pipe (struct drm_device *dev)
2123 {
2124         struct drm_i915_private *dev_priv = dev->dev_private;
2125         u32  pfit_control;
2126
2127         /* i830 doesn't have a panel fitter */
2128         if (IS_I830(dev))
2129                 return -1;
2130
2131         pfit_control = I915_READ(PFIT_CONTROL);
2132
2133         /* See if the panel fitter is in use */
2134         if ((pfit_control & PFIT_ENABLE) == 0)
2135                 return -1;
2136
2137         /* 965 can place panel fitter on either pipe */
2138         if (IS_I965G(dev))
2139                 return (pfit_control >> 29) & 0x3;
2140
2141         /* older chips can only use pipe 1 */
2142         return 1;
2143 }
2144
2145 struct fdi_m_n {
2146         u32        tu;
2147         u32        gmch_m;
2148         u32        gmch_n;
2149         u32        link_m;
2150         u32        link_n;
2151 };
2152
2153 static void
2154 fdi_reduce_ratio(u32 *num, u32 *den)
2155 {
2156         while (*num > 0xffffff || *den > 0xffffff) {
2157                 *num >>= 1;
2158                 *den >>= 1;
2159         }
2160 }
2161
2162 #define DATA_N 0x800000
2163 #define LINK_N 0x80000
2164
2165 static void
2166 igdng_compute_m_n(int bits_per_pixel, int nlanes,
2167                 int pixel_clock, int link_clock,
2168                 struct fdi_m_n *m_n)
2169 {
2170         u64 temp;
2171
2172         m_n->tu = 64; /* default size */
2173
2174         temp = (u64) DATA_N * pixel_clock;
2175         temp = div_u64(temp, link_clock);
2176         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2177         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2178         m_n->gmch_n = DATA_N;
2179         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2180
2181         temp = (u64) LINK_N * pixel_clock;
2182         m_n->link_m = div_u64(temp, link_clock);
2183         m_n->link_n = LINK_N;
2184         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2185 }
2186
2187
2188 struct intel_watermark_params {
2189         unsigned long fifo_size;
2190         unsigned long max_wm;
2191         unsigned long default_wm;
2192         unsigned long guard_size;
2193         unsigned long cacheline_size;
2194 };
2195
2196 /* IGD has different values for various configs */
2197 static struct intel_watermark_params igd_display_wm = {
2198         IGD_DISPLAY_FIFO,
2199         IGD_MAX_WM,
2200         IGD_DFT_WM,
2201         IGD_GUARD_WM,
2202         IGD_FIFO_LINE_SIZE
2203 };
2204 static struct intel_watermark_params igd_display_hplloff_wm = {
2205         IGD_DISPLAY_FIFO,
2206         IGD_MAX_WM,
2207         IGD_DFT_HPLLOFF_WM,
2208         IGD_GUARD_WM,
2209         IGD_FIFO_LINE_SIZE
2210 };
2211 static struct intel_watermark_params igd_cursor_wm = {
2212         IGD_CURSOR_FIFO,
2213         IGD_CURSOR_MAX_WM,
2214         IGD_CURSOR_DFT_WM,
2215         IGD_CURSOR_GUARD_WM,
2216         IGD_FIFO_LINE_SIZE,
2217 };
2218 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2219         IGD_CURSOR_FIFO,
2220         IGD_CURSOR_MAX_WM,
2221         IGD_CURSOR_DFT_WM,
2222         IGD_CURSOR_GUARD_WM,
2223         IGD_FIFO_LINE_SIZE
2224 };
2225 static struct intel_watermark_params g4x_wm_info = {
2226         G4X_FIFO_SIZE,
2227         G4X_MAX_WM,
2228         G4X_MAX_WM,
2229         2,
2230         G4X_FIFO_LINE_SIZE,
2231 };
2232 static struct intel_watermark_params i945_wm_info = {
2233         I945_FIFO_SIZE,
2234         I915_MAX_WM,
2235         1,
2236         2,
2237         I915_FIFO_LINE_SIZE
2238 };
2239 static struct intel_watermark_params i915_wm_info = {
2240         I915_FIFO_SIZE,
2241         I915_MAX_WM,
2242         1,
2243         2,
2244         I915_FIFO_LINE_SIZE
2245 };
2246 static struct intel_watermark_params i855_wm_info = {
2247         I855GM_FIFO_SIZE,
2248         I915_MAX_WM,
2249         1,
2250         2,
2251         I830_FIFO_LINE_SIZE
2252 };
2253 static struct intel_watermark_params i830_wm_info = {
2254         I830_FIFO_SIZE,
2255         I915_MAX_WM,
2256         1,
2257         2,
2258         I830_FIFO_LINE_SIZE
2259 };
2260
2261 /**
2262  * intel_calculate_wm - calculate watermark level
2263  * @clock_in_khz: pixel clock
2264  * @wm: chip FIFO params
2265  * @pixel_size: display pixel size
2266  * @latency_ns: memory latency for the platform
2267  *
2268  * Calculate the watermark level (the level at which the display plane will
2269  * start fetching from memory again).  Each chip has a different display
2270  * FIFO size and allocation, so the caller needs to figure that out and pass
2271  * in the correct intel_watermark_params structure.
2272  *
2273  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2274  * on the pixel size.  When it reaches the watermark level, it'll start
2275  * fetching FIFO line sized based chunks from memory until the FIFO fills
2276  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2277  * will occur, and a display engine hang could result.
2278  */
2279 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2280                                         struct intel_watermark_params *wm,
2281                                         int pixel_size,
2282                                         unsigned long latency_ns)
2283 {
2284         long entries_required, wm_size;
2285
2286         /*
2287          * Note: we need to make sure we don't overflow for various clock &
2288          * latency values.
2289          * clocks go from a few thousand to several hundred thousand.
2290          * latency is usually a few thousand
2291          */
2292         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2293                 1000;
2294         entries_required /= wm->cacheline_size;
2295
2296         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2297
2298         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2299
2300         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2301
2302         /* Don't promote wm_size to unsigned... */
2303         if (wm_size > (long)wm->max_wm)
2304                 wm_size = wm->max_wm;
2305         if (wm_size <= 0)
2306                 wm_size = wm->default_wm;
2307         return wm_size;
2308 }
2309
2310 struct cxsr_latency {
2311         int is_desktop;
2312         unsigned long fsb_freq;
2313         unsigned long mem_freq;
2314         unsigned long display_sr;
2315         unsigned long display_hpll_disable;
2316         unsigned long cursor_sr;
2317         unsigned long cursor_hpll_disable;
2318 };
2319
2320 static struct cxsr_latency cxsr_latency_table[] = {
2321         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2322         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2323         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2324
2325         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2326         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2327         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2328
2329         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2330         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2331         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2332
2333         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2334         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2335         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2336
2337         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2338         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2339         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2340
2341         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2342         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2343         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2344 };
2345
2346 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2347                                                    int mem)
2348 {
2349         int i;
2350         struct cxsr_latency *latency;
2351
2352         if (fsb == 0 || mem == 0)
2353                 return NULL;
2354
2355         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2356                 latency = &cxsr_latency_table[i];
2357                 if (is_desktop == latency->is_desktop &&
2358                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2359                         return latency;
2360         }
2361
2362         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2363
2364         return NULL;
2365 }
2366
2367 static void igd_disable_cxsr(struct drm_device *dev)
2368 {
2369         struct drm_i915_private *dev_priv = dev->dev_private;
2370         u32 reg;
2371
2372         /* deactivate cxsr */
2373         reg = I915_READ(DSPFW3);
2374         reg &= ~(IGD_SELF_REFRESH_EN);
2375         I915_WRITE(DSPFW3, reg);
2376         DRM_INFO("Big FIFO is disabled\n");
2377 }
2378
2379 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2380                             int pixel_size)
2381 {
2382         struct drm_i915_private *dev_priv = dev->dev_private;
2383         u32 reg;
2384         unsigned long wm;
2385         struct cxsr_latency *latency;
2386
2387         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2388                 dev_priv->mem_freq);
2389         if (!latency) {
2390                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2391                 igd_disable_cxsr(dev);
2392                 return;
2393         }
2394
2395         /* Display SR */
2396         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2397                                 latency->display_sr);
2398         reg = I915_READ(DSPFW1);
2399         reg &= 0x7fffff;
2400         reg |= wm << 23;
2401         I915_WRITE(DSPFW1, reg);
2402         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2403
2404         /* cursor SR */
2405         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2406                                 latency->cursor_sr);
2407         reg = I915_READ(DSPFW3);
2408         reg &= ~(0x3f << 24);
2409         reg |= (wm & 0x3f) << 24;
2410         I915_WRITE(DSPFW3, reg);
2411
2412         /* Display HPLL off SR */
2413         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2414                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2415         reg = I915_READ(DSPFW3);
2416         reg &= 0xfffffe00;
2417         reg |= wm & 0x1ff;
2418         I915_WRITE(DSPFW3, reg);
2419
2420         /* cursor HPLL off SR */
2421         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2422                                 latency->cursor_hpll_disable);
2423         reg = I915_READ(DSPFW3);
2424         reg &= ~(0x3f << 16);
2425         reg |= (wm & 0x3f) << 16;
2426         I915_WRITE(DSPFW3, reg);
2427         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2428
2429         /* activate cxsr */
2430         reg = I915_READ(DSPFW3);
2431         reg |= IGD_SELF_REFRESH_EN;
2432         I915_WRITE(DSPFW3, reg);
2433
2434         DRM_INFO("Big FIFO is enabled\n");
2435
2436         return;
2437 }
2438
2439 /*
2440  * Latency for FIFO fetches is dependent on several factors:
2441  *   - memory configuration (speed, channels)
2442  *   - chipset
2443  *   - current MCH state
2444  * It can be fairly high in some situations, so here we assume a fairly
2445  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2446  * set this value too high, the FIFO will fetch frequently to stay full)
2447  * and power consumption (set it too low to save power and we might see
2448  * FIFO underruns and display "flicker").
2449  *
2450  * A value of 5us seems to be a good balance; safe for very low end
2451  * platforms but not overly aggressive on lower latency configs.
2452  */
2453 const static int latency_ns = 5000;
2454
2455 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2456 {
2457         struct drm_i915_private *dev_priv = dev->dev_private;
2458         uint32_t dsparb = I915_READ(DSPARB);
2459         int size;
2460
2461         if (plane == 0)
2462                 size = dsparb & 0x7f;
2463         else
2464                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2465                         (dsparb & 0x7f);
2466
2467         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2468                         plane ? "B" : "A", size);
2469
2470         return size;
2471 }
2472
2473 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2474 {
2475         struct drm_i915_private *dev_priv = dev->dev_private;
2476         uint32_t dsparb = I915_READ(DSPARB);
2477         int size;
2478
2479         if (plane == 0)
2480                 size = dsparb & 0x1ff;
2481         else
2482                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2483                         (dsparb & 0x1ff);
2484         size >>= 1; /* Convert to cachelines */
2485
2486         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2487                         plane ? "B" : "A", size);
2488
2489         return size;
2490 }
2491
2492 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2493 {
2494         struct drm_i915_private *dev_priv = dev->dev_private;
2495         uint32_t dsparb = I915_READ(DSPARB);
2496         int size;
2497
2498         size = dsparb & 0x7f;
2499         size >>= 2; /* Convert to cachelines */
2500
2501         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2502                         plane ? "B" : "A",
2503                   size);
2504
2505         return size;
2506 }
2507
2508 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2509 {
2510         struct drm_i915_private *dev_priv = dev->dev_private;
2511         uint32_t dsparb = I915_READ(DSPARB);
2512         int size;
2513
2514         size = dsparb & 0x7f;
2515         size >>= 1; /* Convert to cachelines */
2516
2517         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2518                         plane ? "B" : "A", size);
2519
2520         return size;
2521 }
2522
2523 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2524                           int planeb_clock, int sr_hdisplay, int pixel_size)
2525 {
2526         struct drm_i915_private *dev_priv = dev->dev_private;
2527         int total_size, cacheline_size;
2528         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2529         struct intel_watermark_params planea_params, planeb_params;
2530         unsigned long line_time_us;
2531         int sr_clock, sr_entries = 0, entries_required;
2532
2533         /* Create copies of the base settings for each pipe */
2534         planea_params = planeb_params = g4x_wm_info;
2535
2536         /* Grab a couple of global values before we overwrite them */
2537         total_size = planea_params.fifo_size;
2538         cacheline_size = planea_params.cacheline_size;
2539
2540         /*
2541          * Note: we need to make sure we don't overflow for various clock &
2542          * latency values.
2543          * clocks go from a few thousand to several hundred thousand.
2544          * latency is usually a few thousand
2545          */
2546         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2547                 1000;
2548         entries_required /= G4X_FIFO_LINE_SIZE;
2549         planea_wm = entries_required + planea_params.guard_size;
2550
2551         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2552                 1000;
2553         entries_required /= G4X_FIFO_LINE_SIZE;
2554         planeb_wm = entries_required + planeb_params.guard_size;
2555
2556         cursora_wm = cursorb_wm = 16;
2557         cursor_sr = 32;
2558
2559         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2560
2561         /* Calc sr entries for one plane configs */
2562         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2563                 /* self-refresh has much higher latency */
2564                 const static int sr_latency_ns = 12000;
2565
2566                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2567                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2568
2569                 /* Use ns/us then divide to preserve precision */
2570                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2571                               pixel_size * sr_hdisplay) / 1000;
2572                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2573                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2574                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2575         }
2576
2577         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2578                   planea_wm, planeb_wm, sr_entries);
2579
2580         planea_wm &= 0x3f;
2581         planeb_wm &= 0x3f;
2582
2583         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2584                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2585                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2586         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2587                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2588         /* HPLL off in SR has some issues on G4x... disable it */
2589         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2590                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2591 }
2592
2593 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2594                            int planeb_clock, int sr_hdisplay, int pixel_size)
2595 {
2596         struct drm_i915_private *dev_priv = dev->dev_private;
2597         unsigned long line_time_us;
2598         int sr_clock, sr_entries, srwm = 1;
2599
2600         /* Calc sr entries for one plane configs */
2601         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2602                 /* self-refresh has much higher latency */
2603                 const static int sr_latency_ns = 12000;
2604
2605                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2606                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2607
2608                 /* Use ns/us then divide to preserve precision */
2609                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2610                               pixel_size * sr_hdisplay) / 1000;
2611                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2612                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2613                 srwm = I945_FIFO_SIZE - sr_entries;
2614                 if (srwm < 0)
2615                         srwm = 1;
2616                 srwm &= 0x3f;
2617                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2618         }
2619
2620         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2621                       srwm);
2622
2623         /* 965 has limitations... */
2624         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2625                    (8 << 0));
2626         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2627 }
2628
2629 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2630                            int planeb_clock, int sr_hdisplay, int pixel_size)
2631 {
2632         struct drm_i915_private *dev_priv = dev->dev_private;
2633         uint32_t fwater_lo;
2634         uint32_t fwater_hi;
2635         int total_size, cacheline_size, cwm, srwm = 1;
2636         int planea_wm, planeb_wm;
2637         struct intel_watermark_params planea_params, planeb_params;
2638         unsigned long line_time_us;
2639         int sr_clock, sr_entries = 0;
2640
2641         /* Create copies of the base settings for each pipe */
2642         if (IS_I965GM(dev) || IS_I945GM(dev))
2643                 planea_params = planeb_params = i945_wm_info;
2644         else if (IS_I9XX(dev))
2645                 planea_params = planeb_params = i915_wm_info;
2646         else
2647                 planea_params = planeb_params = i855_wm_info;
2648
2649         /* Grab a couple of global values before we overwrite them */
2650         total_size = planea_params.fifo_size;
2651         cacheline_size = planea_params.cacheline_size;
2652
2653         /* Update per-plane FIFO sizes */
2654         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2655         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2656
2657         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2658                                        pixel_size, latency_ns);
2659         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2660                                        pixel_size, latency_ns);
2661         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2662
2663         /*
2664          * Overlay gets an aggressive default since video jitter is bad.
2665          */
2666         cwm = 2;
2667
2668         /* Calc sr entries for one plane configs */
2669         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2670             (!planea_clock || !planeb_clock)) {
2671                 /* self-refresh has much higher latency */
2672                 const static int sr_latency_ns = 6000;
2673
2674                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2675                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2676
2677                 /* Use ns/us then divide to preserve precision */
2678                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2679                               pixel_size * sr_hdisplay) / 1000;
2680                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2681                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2682                 srwm = total_size - sr_entries;
2683                 if (srwm < 0)
2684                         srwm = 1;
2685                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2686         }
2687
2688         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2689                   planea_wm, planeb_wm, cwm, srwm);
2690
2691         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2692         fwater_hi = (cwm & 0x1f);
2693
2694         /* Set request length to 8 cachelines per fetch */
2695         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2696         fwater_hi = fwater_hi | (1 << 8);
2697
2698         I915_WRITE(FW_BLC, fwater_lo);
2699         I915_WRITE(FW_BLC2, fwater_hi);
2700 }
2701
2702 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2703                            int unused2, int pixel_size)
2704 {
2705         struct drm_i915_private *dev_priv = dev->dev_private;
2706         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2707         int planea_wm;
2708
2709         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2710
2711         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2712                                        pixel_size, latency_ns);
2713         fwater_lo |= (3<<8) | planea_wm;
2714
2715         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2716
2717         I915_WRITE(FW_BLC, fwater_lo);
2718 }
2719
2720 /**
2721  * intel_update_watermarks - update FIFO watermark values based on current modes
2722  *
2723  * Calculate watermark values for the various WM regs based on current mode
2724  * and plane configuration.
2725  *
2726  * There are several cases to deal with here:
2727  *   - normal (i.e. non-self-refresh)
2728  *   - self-refresh (SR) mode
2729  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2730  *   - lines are small relative to FIFO size (buffer can hold more than 2
2731  *     lines), so need to account for TLB latency
2732  *
2733  *   The normal calculation is:
2734  *     watermark = dotclock * bytes per pixel * latency
2735  *   where latency is platform & configuration dependent (we assume pessimal
2736  *   values here).
2737  *
2738  *   The SR calculation is:
2739  *     watermark = (trunc(latency/line time)+1) * surface width *
2740  *       bytes per pixel
2741  *   where
2742  *     line time = htotal / dotclock
2743  *   and latency is assumed to be high, as above.
2744  *
2745  * The final value programmed to the register should always be rounded up,
2746  * and include an extra 2 entries to account for clock crossings.
2747  *
2748  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2749  * to set the non-SR watermarks to 8.
2750   */
2751 static void intel_update_watermarks(struct drm_device *dev)
2752 {
2753         struct drm_i915_private *dev_priv = dev->dev_private;
2754         struct drm_crtc *crtc;
2755         struct intel_crtc *intel_crtc;
2756         int sr_hdisplay = 0;
2757         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2758         int enabled = 0, pixel_size = 0;
2759
2760         if (!dev_priv->display.update_wm)
2761                 return;
2762
2763         /* Get the clock config from both planes */
2764         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2765                 intel_crtc = to_intel_crtc(crtc);
2766                 if (crtc->enabled) {
2767                         enabled++;
2768                         if (intel_crtc->plane == 0) {
2769                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2770                                           intel_crtc->pipe, crtc->mode.clock);
2771                                 planea_clock = crtc->mode.clock;
2772                         } else {
2773                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2774                                           intel_crtc->pipe, crtc->mode.clock);
2775                                 planeb_clock = crtc->mode.clock;
2776                         }
2777                         sr_hdisplay = crtc->mode.hdisplay;
2778                         sr_clock = crtc->mode.clock;
2779                         if (crtc->fb)
2780                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2781                         else
2782                                 pixel_size = 4; /* by default */
2783                 }
2784         }
2785
2786         if (enabled <= 0)
2787                 return;
2788
2789         /* Single plane configs can enable self refresh */
2790         if (enabled == 1 && IS_IGD(dev))
2791                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2792         else if (IS_IGD(dev))
2793                 igd_disable_cxsr(dev);
2794
2795         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2796                                     sr_hdisplay, pixel_size);
2797 }
2798
2799 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2800                                struct drm_display_mode *mode,
2801                                struct drm_display_mode *adjusted_mode,
2802                                int x, int y,
2803                                struct drm_framebuffer *old_fb)
2804 {
2805         struct drm_device *dev = crtc->dev;
2806         struct drm_i915_private *dev_priv = dev->dev_private;
2807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2808         int pipe = intel_crtc->pipe;
2809         int plane = intel_crtc->plane;
2810         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2811         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2812         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2813         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2814         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2815         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2816         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2817         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2818         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2819         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2820         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2821         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2822         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2823         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2824         int refclk, num_outputs = 0;
2825         intel_clock_t clock, reduced_clock;
2826         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2827         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2828         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2829         bool is_edp = false;
2830         struct drm_mode_config *mode_config = &dev->mode_config;
2831         struct drm_connector *connector;
2832         const intel_limit_t *limit;
2833         int ret;
2834         struct fdi_m_n m_n = {0};
2835         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2836         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2837         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2838         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2839         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2840         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2841         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2842         int lvds_reg = LVDS;
2843         u32 temp;
2844         int sdvo_pixel_multiply;
2845         int target_clock;
2846
2847         drm_vblank_pre_modeset(dev, pipe);
2848
2849         list_for_each_entry(connector, &mode_config->connector_list, head) {
2850                 struct intel_output *intel_output = to_intel_output(connector);
2851
2852                 if (!connector->encoder || connector->encoder->crtc != crtc)
2853                         continue;
2854
2855                 switch (intel_output->type) {
2856                 case INTEL_OUTPUT_LVDS:
2857                         is_lvds = true;
2858                         break;
2859                 case INTEL_OUTPUT_SDVO:
2860                 case INTEL_OUTPUT_HDMI:
2861                         is_sdvo = true;
2862                         if (intel_output->needs_tv_clock)
2863                                 is_tv = true;
2864                         break;
2865                 case INTEL_OUTPUT_DVO:
2866                         is_dvo = true;
2867                         break;
2868                 case INTEL_OUTPUT_TVOUT:
2869                         is_tv = true;
2870                         break;
2871                 case INTEL_OUTPUT_ANALOG:
2872                         is_crt = true;
2873                         break;
2874                 case INTEL_OUTPUT_DISPLAYPORT:
2875                         is_dp = true;
2876                         break;
2877                 case INTEL_OUTPUT_EDP:
2878                         is_edp = true;
2879                         break;
2880                 }
2881
2882                 num_outputs++;
2883         }
2884
2885         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2886                 refclk = dev_priv->lvds_ssc_freq * 1000;
2887                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2888                                         refclk / 1000);
2889         } else if (IS_I9XX(dev)) {
2890                 refclk = 96000;
2891                 if (IS_IGDNG(dev))
2892                         refclk = 120000; /* 120Mhz refclk */
2893         } else {
2894                 refclk = 48000;
2895         }
2896
2897
2898         /*
2899          * Returns a set of divisors for the desired target clock with the given
2900          * refclk, or FALSE.  The returned values represent the clock equation:
2901          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2902          */
2903         limit = intel_limit(crtc);
2904         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2905         if (!ok) {
2906                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2907                 drm_vblank_post_modeset(dev, pipe);
2908                 return -EINVAL;
2909         }
2910
2911         if (is_lvds && limit->find_reduced_pll &&
2912                         dev_priv->lvds_downclock_avail) {
2913                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2914                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2915                                                             dev_priv->lvds_downclock,
2916                                                             refclk,
2917                                                             &reduced_clock);
2918                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2919                         /*
2920                          * If the different P is found, it means that we can't
2921                          * switch the display clock by using the FP0/FP1.
2922                          * In such case we will disable the LVDS downclock
2923                          * feature.
2924                          */
2925                         DRM_DEBUG_KMS("Different P is found for "
2926                                                 "LVDS clock/downclock\n");
2927                         has_reduced_clock = 0;
2928                 }
2929         }
2930         /* SDVO TV has fixed PLL values depend on its clock range,
2931            this mirrors vbios setting. */
2932         if (is_sdvo && is_tv) {
2933                 if (adjusted_mode->clock >= 100000
2934                                 && adjusted_mode->clock < 140500) {
2935                         clock.p1 = 2;
2936                         clock.p2 = 10;
2937                         clock.n = 3;
2938                         clock.m1 = 16;
2939                         clock.m2 = 8;
2940                 } else if (adjusted_mode->clock >= 140500
2941                                 && adjusted_mode->clock <= 200000) {
2942                         clock.p1 = 1;
2943                         clock.p2 = 10;
2944                         clock.n = 6;
2945                         clock.m1 = 12;
2946                         clock.m2 = 8;
2947                 }
2948         }
2949
2950         /* FDI link */
2951         if (IS_IGDNG(dev)) {
2952                 int lane, link_bw, bpp;
2953                 /* eDP doesn't require FDI link, so just set DP M/N
2954                    according to current link config */
2955                 if (is_edp) {
2956                         struct drm_connector *edp;
2957                         target_clock = mode->clock;
2958                         edp = intel_pipe_get_output(crtc);
2959                         intel_edp_link_config(to_intel_output(edp),
2960                                         &lane, &link_bw);
2961                 } else {
2962                         /* DP over FDI requires target mode clock
2963                            instead of link clock */
2964                         if (is_dp)
2965                                 target_clock = mode->clock;
2966                         else
2967                                 target_clock = adjusted_mode->clock;
2968                         lane = 4;
2969                         link_bw = 270000;
2970                 }
2971
2972                 /* determine panel color depth */
2973                 temp = I915_READ(pipeconf_reg);
2974
2975                 switch (temp & PIPE_BPC_MASK) {
2976                 case PIPE_8BPC:
2977                         bpp = 24;
2978                         break;
2979                 case PIPE_10BPC:
2980                         bpp = 30;
2981                         break;
2982                 case PIPE_6BPC:
2983                         bpp = 18;
2984                         break;
2985                 case PIPE_12BPC:
2986                         bpp = 36;
2987                         break;
2988                 default:
2989                         DRM_ERROR("unknown pipe bpc value\n");
2990                         bpp = 24;
2991                 }
2992
2993                 igdng_compute_m_n(bpp, lane, target_clock,
2994                                   link_bw, &m_n);
2995         }
2996
2997         /* Ironlake: try to setup display ref clock before DPLL
2998          * enabling. This is only under driver's control after
2999          * PCH B stepping, previous chipset stepping should be
3000          * ignoring this setting.
3001          */
3002         if (IS_IGDNG(dev)) {
3003                 temp = I915_READ(PCH_DREF_CONTROL);
3004                 /* Always enable nonspread source */
3005                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3006                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3007                 I915_WRITE(PCH_DREF_CONTROL, temp);
3008                 POSTING_READ(PCH_DREF_CONTROL);
3009
3010                 temp &= ~DREF_SSC_SOURCE_MASK;
3011                 temp |= DREF_SSC_SOURCE_ENABLE;
3012                 I915_WRITE(PCH_DREF_CONTROL, temp);
3013                 POSTING_READ(PCH_DREF_CONTROL);
3014
3015                 udelay(200);
3016
3017                 if (is_edp) {
3018                         if (dev_priv->lvds_use_ssc) {
3019                                 temp |= DREF_SSC1_ENABLE;
3020                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3021                                 POSTING_READ(PCH_DREF_CONTROL);
3022
3023                                 udelay(200);
3024
3025                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3026                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3027                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3028                                 POSTING_READ(PCH_DREF_CONTROL);
3029                         } else {
3030                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3031                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3032                                 POSTING_READ(PCH_DREF_CONTROL);
3033                         }
3034                 }
3035         }
3036
3037         if (IS_IGD(dev)) {
3038                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3039                 if (has_reduced_clock)
3040                         fp2 = (1 << reduced_clock.n) << 16 |
3041                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3042         } else {
3043                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3044                 if (has_reduced_clock)
3045                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3046                                 reduced_clock.m2;
3047         }
3048
3049         if (!IS_IGDNG(dev))
3050                 dpll = DPLL_VGA_MODE_DIS;
3051
3052         if (IS_I9XX(dev)) {
3053                 if (is_lvds)
3054                         dpll |= DPLLB_MODE_LVDS;
3055                 else
3056                         dpll |= DPLLB_MODE_DAC_SERIAL;
3057                 if (is_sdvo) {
3058                         dpll |= DPLL_DVO_HIGH_SPEED;
3059                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3060                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3061                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3062                         else if (IS_IGDNG(dev))
3063                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3064                 }
3065                 if (is_dp)
3066                         dpll |= DPLL_DVO_HIGH_SPEED;
3067
3068                 /* compute bitmask from p1 value */
3069                 if (IS_IGD(dev))
3070                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
3071                 else {
3072                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3073                         /* also FPA1 */
3074                         if (IS_IGDNG(dev))
3075                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3076                         if (IS_G4X(dev) && has_reduced_clock)
3077                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3078                 }
3079                 switch (clock.p2) {
3080                 case 5:
3081                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3082                         break;
3083                 case 7:
3084                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3085                         break;
3086                 case 10:
3087                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3088                         break;
3089                 case 14:
3090                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3091                         break;
3092                 }
3093                 if (IS_I965G(dev) && !IS_IGDNG(dev))
3094                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3095         } else {
3096                 if (is_lvds) {
3097                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3098                 } else {
3099                         if (clock.p1 == 2)
3100                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3101                         else
3102                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3103                         if (clock.p2 == 4)
3104                                 dpll |= PLL_P2_DIVIDE_BY_4;
3105                 }
3106         }
3107
3108         if (is_sdvo && is_tv)
3109                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3110         else if (is_tv)
3111                 /* XXX: just matching BIOS for now */
3112                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3113                 dpll |= 3;
3114         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3115                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3116         else
3117                 dpll |= PLL_REF_INPUT_DREFCLK;
3118
3119         /* setup pipeconf */
3120         pipeconf = I915_READ(pipeconf_reg);
3121
3122         /* Set up the display plane register */
3123         dspcntr = DISPPLANE_GAMMA_ENABLE;
3124
3125         /* IGDNG's plane is forced to pipe, bit 24 is to
3126            enable color space conversion */
3127         if (!IS_IGDNG(dev)) {
3128                 if (pipe == 0)
3129                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3130                 else
3131                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3132         }
3133
3134         if (pipe == 0 && !IS_I965G(dev)) {
3135                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3136                  * core speed.
3137                  *
3138                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3139                  * pipe == 0 check?
3140                  */
3141                 if (mode->clock >
3142                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3143                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3144                 else
3145                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3146         }
3147
3148         dspcntr |= DISPLAY_PLANE_ENABLE;
3149         pipeconf |= PIPEACONF_ENABLE;
3150         dpll |= DPLL_VCO_ENABLE;
3151
3152
3153         /* Disable the panel fitter if it was on our pipe */
3154         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3155                 I915_WRITE(PFIT_CONTROL, 0);
3156
3157         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3158         drm_mode_debug_printmodeline(mode);
3159
3160         /* assign to IGDNG registers */
3161         if (IS_IGDNG(dev)) {
3162                 fp_reg = pch_fp_reg;
3163                 dpll_reg = pch_dpll_reg;
3164         }
3165
3166         if (is_edp) {
3167                 igdng_disable_pll_edp(crtc);
3168         } else if ((dpll & DPLL_VCO_ENABLE)) {
3169                 I915_WRITE(fp_reg, fp);
3170                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3171                 I915_READ(dpll_reg);
3172                 udelay(150);
3173         }
3174
3175         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3176          * This is an exception to the general rule that mode_set doesn't turn
3177          * things on.
3178          */
3179         if (is_lvds) {
3180                 u32 lvds;
3181
3182                 if (IS_IGDNG(dev))
3183                         lvds_reg = PCH_LVDS;
3184
3185                 lvds = I915_READ(lvds_reg);
3186                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3187                 /* set the corresponsding LVDS_BORDER bit */
3188                 lvds |= dev_priv->lvds_border_bits;
3189                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3190                  * set the DPLLs for dual-channel mode or not.
3191                  */
3192                 if (clock.p2 == 7)
3193                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3194                 else
3195                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3196
3197                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3198                  * appropriately here, but we need to look more thoroughly into how
3199                  * panels behave in the two modes.
3200                  */
3201
3202                 I915_WRITE(lvds_reg, lvds);
3203                 I915_READ(lvds_reg);
3204         }
3205         if (is_dp)
3206                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3207
3208         if (!is_edp) {
3209                 I915_WRITE(fp_reg, fp);
3210                 I915_WRITE(dpll_reg, dpll);
3211                 I915_READ(dpll_reg);
3212                 /* Wait for the clocks to stabilize. */
3213                 udelay(150);
3214
3215                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
3216                         if (is_sdvo) {
3217                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3218                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3219                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3220                         } else
3221                                 I915_WRITE(dpll_md_reg, 0);
3222                 } else {
3223                         /* write it again -- the BIOS does, after all */
3224                         I915_WRITE(dpll_reg, dpll);
3225                 }
3226                 I915_READ(dpll_reg);
3227                 /* Wait for the clocks to stabilize. */
3228                 udelay(150);
3229         }
3230
3231         if (is_lvds && has_reduced_clock && i915_powersave) {
3232                 I915_WRITE(fp_reg + 4, fp2);
3233                 intel_crtc->lowfreq_avail = true;
3234                 if (HAS_PIPE_CXSR(dev)) {
3235                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3236                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3237                 }
3238         } else {
3239                 I915_WRITE(fp_reg + 4, fp);
3240                 intel_crtc->lowfreq_avail = false;
3241                 if (HAS_PIPE_CXSR(dev)) {
3242                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3243                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3244                 }
3245         }
3246
3247         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3248                    ((adjusted_mode->crtc_htotal - 1) << 16));
3249         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3250                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3251         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3252                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3253         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3254                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3255         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3256                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3257         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3258                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3259         /* pipesrc and dspsize control the size that is scaled from, which should
3260          * always be the user's requested size.
3261          */
3262         if (!IS_IGDNG(dev)) {
3263                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3264                                 (mode->hdisplay - 1));
3265                 I915_WRITE(dsppos_reg, 0);
3266         }
3267         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3268
3269         if (IS_IGDNG(dev)) {
3270                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3271                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3272                 I915_WRITE(link_m1_reg, m_n.link_m);
3273                 I915_WRITE(link_n1_reg, m_n.link_n);
3274
3275                 if (is_edp) {
3276                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
3277                 } else {
3278                         /* enable FDI RX PLL too */
3279                         temp = I915_READ(fdi_rx_reg);
3280                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3281                         udelay(200);
3282                 }
3283         }
3284
3285         I915_WRITE(pipeconf_reg, pipeconf);
3286         I915_READ(pipeconf_reg);
3287
3288         intel_wait_for_vblank(dev);
3289
3290         if (IS_IGDNG(dev)) {
3291                 /* enable address swizzle for tiling buffer */
3292                 temp = I915_READ(DISP_ARB_CTL);
3293                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3294         }
3295
3296         I915_WRITE(dspcntr_reg, dspcntr);
3297
3298         /* Flush the plane changes */
3299         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3300
3301         if ((IS_I965G(dev) || plane == 0))
3302                 intel_update_fbc(crtc, &crtc->mode);
3303
3304         intel_update_watermarks(dev);
3305
3306         drm_vblank_post_modeset(dev, pipe);
3307
3308         return ret;
3309 }
3310
3311 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3312 void intel_crtc_load_lut(struct drm_crtc *crtc)
3313 {
3314         struct drm_device *dev = crtc->dev;
3315         struct drm_i915_private *dev_priv = dev->dev_private;
3316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3317         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3318         int i;
3319
3320         /* The clocks have to be on to load the palette. */
3321         if (!crtc->enabled)
3322                 return;
3323
3324         /* use legacy palette for IGDNG */
3325         if (IS_IGDNG(dev))
3326                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3327                                                    LGC_PALETTE_B;
3328
3329         for (i = 0; i < 256; i++) {
3330                 I915_WRITE(palreg + 4 * i,
3331                            (intel_crtc->lut_r[i] << 16) |
3332                            (intel_crtc->lut_g[i] << 8) |
3333                            intel_crtc->lut_b[i]);
3334         }
3335 }
3336
3337 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3338                                  struct drm_file *file_priv,
3339                                  uint32_t handle,
3340                                  uint32_t width, uint32_t height)
3341 {
3342         struct drm_device *dev = crtc->dev;
3343         struct drm_i915_private *dev_priv = dev->dev_private;
3344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3345         struct drm_gem_object *bo;
3346         struct drm_i915_gem_object *obj_priv;
3347         int pipe = intel_crtc->pipe;
3348         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3349         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3350         uint32_t temp = I915_READ(control);
3351         size_t addr;
3352         int ret;
3353
3354         DRM_DEBUG_KMS("\n");
3355
3356         /* if we want to turn off the cursor ignore width and height */
3357         if (!handle) {
3358                 DRM_DEBUG_KMS("cursor off\n");
3359                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3360                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3361                         temp |= CURSOR_MODE_DISABLE;
3362                 } else {
3363                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3364                 }
3365                 addr = 0;
3366                 bo = NULL;
3367                 mutex_lock(&dev->struct_mutex);
3368                 goto finish;
3369         }
3370
3371         /* Currently we only support 64x64 cursors */
3372         if (width != 64 || height != 64) {
3373                 DRM_ERROR("we currently only support 64x64 cursors\n");
3374                 return -EINVAL;
3375         }
3376
3377         bo = drm_gem_object_lookup(dev, file_priv, handle);
3378         if (!bo)
3379                 return -ENOENT;
3380
3381         obj_priv = bo->driver_private;
3382
3383         if (bo->size < width * height * 4) {
3384                 DRM_ERROR("buffer is to small\n");
3385                 ret = -ENOMEM;
3386                 goto fail;
3387         }
3388
3389         /* we only need to pin inside GTT if cursor is non-phy */
3390         mutex_lock(&dev->struct_mutex);
3391         if (!dev_priv->cursor_needs_physical) {
3392                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3393                 if (ret) {
3394                         DRM_ERROR("failed to pin cursor bo\n");
3395                         goto fail_locked;
3396                 }
3397                 addr = obj_priv->gtt_offset;
3398         } else {
3399                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3400                 if (ret) {
3401                         DRM_ERROR("failed to attach phys object\n");
3402                         goto fail_locked;
3403                 }
3404                 addr = obj_priv->phys_obj->handle->busaddr;
3405         }
3406
3407         if (!IS_I9XX(dev))
3408                 I915_WRITE(CURSIZE, (height << 12) | width);
3409
3410         /* Hooray for CUR*CNTR differences */
3411         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3412                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3413                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3414                 temp |= (pipe << 28); /* Connect to correct pipe */
3415         } else {
3416                 temp &= ~(CURSOR_FORMAT_MASK);
3417                 temp |= CURSOR_ENABLE;
3418                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3419         }
3420
3421  finish:
3422         I915_WRITE(control, temp);
3423         I915_WRITE(base, addr);
3424
3425         if (intel_crtc->cursor_bo) {
3426                 if (dev_priv->cursor_needs_physical) {
3427                         if (intel_crtc->cursor_bo != bo)
3428                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3429                 } else
3430                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3431                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3432         }
3433
3434         mutex_unlock(&dev->struct_mutex);
3435
3436         intel_crtc->cursor_addr = addr;
3437         intel_crtc->cursor_bo = bo;
3438
3439         return 0;
3440 fail:
3441         mutex_lock(&dev->struct_mutex);
3442 fail_locked:
3443         drm_gem_object_unreference(bo);
3444         mutex_unlock(&dev->struct_mutex);
3445         return ret;
3446 }
3447
3448 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3449 {
3450         struct drm_device *dev = crtc->dev;
3451         struct drm_i915_private *dev_priv = dev->dev_private;
3452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3453         struct intel_framebuffer *intel_fb;
3454         int pipe = intel_crtc->pipe;
3455         uint32_t temp = 0;
3456         uint32_t adder;
3457
3458         if (crtc->fb) {
3459                 intel_fb = to_intel_framebuffer(crtc->fb);
3460                 intel_mark_busy(dev, intel_fb->obj);
3461         }
3462
3463         if (x < 0) {
3464                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3465                 x = -x;
3466         }
3467         if (y < 0) {
3468                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3469                 y = -y;
3470         }
3471
3472         temp |= x << CURSOR_X_SHIFT;
3473         temp |= y << CURSOR_Y_SHIFT;
3474
3475         adder = intel_crtc->cursor_addr;
3476         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3477         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3478
3479         return 0;
3480 }
3481
3482 /** Sets the color ramps on behalf of RandR */
3483 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3484                                  u16 blue, int regno)
3485 {
3486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3487
3488         intel_crtc->lut_r[regno] = red >> 8;
3489         intel_crtc->lut_g[regno] = green >> 8;
3490         intel_crtc->lut_b[regno] = blue >> 8;
3491 }
3492
3493 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3494                              u16 *blue, int regno)
3495 {
3496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497
3498         *red = intel_crtc->lut_r[regno] << 8;
3499         *green = intel_crtc->lut_g[regno] << 8;
3500         *blue = intel_crtc->lut_b[regno] << 8;
3501 }
3502
3503 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3504                                  u16 *blue, uint32_t size)
3505 {
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         int i;
3508
3509         if (size != 256)
3510                 return;
3511
3512         for (i = 0; i < 256; i++) {
3513                 intel_crtc->lut_r[i] = red[i] >> 8;
3514                 intel_crtc->lut_g[i] = green[i] >> 8;
3515                 intel_crtc->lut_b[i] = blue[i] >> 8;
3516         }
3517
3518         intel_crtc_load_lut(crtc);
3519 }
3520
3521 /**
3522  * Get a pipe with a simple mode set on it for doing load-based monitor
3523  * detection.
3524  *
3525  * It will be up to the load-detect code to adjust the pipe as appropriate for
3526  * its requirements.  The pipe will be connected to no other outputs.
3527  *
3528  * Currently this code will only succeed if there is a pipe with no outputs
3529  * configured for it.  In the future, it could choose to temporarily disable
3530  * some outputs to free up a pipe for its use.
3531  *
3532  * \return crtc, or NULL if no pipes are available.
3533  */
3534
3535 /* VESA 640x480x72Hz mode to set on the pipe */
3536 static struct drm_display_mode load_detect_mode = {
3537         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3538                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3539 };
3540
3541 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3542                                             struct drm_display_mode *mode,
3543                                             int *dpms_mode)
3544 {
3545         struct intel_crtc *intel_crtc;
3546         struct drm_crtc *possible_crtc;
3547         struct drm_crtc *supported_crtc =NULL;
3548         struct drm_encoder *encoder = &intel_output->enc;
3549         struct drm_crtc *crtc = NULL;
3550         struct drm_device *dev = encoder->dev;
3551         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3552         struct drm_crtc_helper_funcs *crtc_funcs;
3553         int i = -1;
3554
3555         /*
3556          * Algorithm gets a little messy:
3557          *   - if the connector already has an assigned crtc, use it (but make
3558          *     sure it's on first)
3559          *   - try to find the first unused crtc that can drive this connector,
3560          *     and use that if we find one
3561          *   - if there are no unused crtcs available, try to use the first
3562          *     one we found that supports the connector
3563          */
3564
3565         /* See if we already have a CRTC for this connector */
3566         if (encoder->crtc) {
3567                 crtc = encoder->crtc;
3568                 /* Make sure the crtc and connector are running */
3569                 intel_crtc = to_intel_crtc(crtc);
3570                 *dpms_mode = intel_crtc->dpms_mode;
3571                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3572                         crtc_funcs = crtc->helper_private;
3573                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3574                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3575                 }
3576                 return crtc;
3577         }
3578
3579         /* Find an unused one (if possible) */
3580         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3581                 i++;
3582                 if (!(encoder->possible_crtcs & (1 << i)))
3583                         continue;
3584                 if (!possible_crtc->enabled) {
3585                         crtc = possible_crtc;
3586                         break;
3587                 }
3588                 if (!supported_crtc)
3589                         supported_crtc = possible_crtc;
3590         }
3591
3592         /*
3593          * If we didn't find an unused CRTC, don't use any.
3594          */
3595         if (!crtc) {
3596                 return NULL;
3597         }
3598
3599         encoder->crtc = crtc;
3600         intel_output->base.encoder = encoder;
3601         intel_output->load_detect_temp = true;
3602
3603         intel_crtc = to_intel_crtc(crtc);
3604         *dpms_mode = intel_crtc->dpms_mode;
3605
3606         if (!crtc->enabled) {
3607                 if (!mode)
3608                         mode = &load_detect_mode;
3609                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3610         } else {
3611                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3612                         crtc_funcs = crtc->helper_private;
3613                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3614                 }
3615
3616                 /* Add this connector to the crtc */
3617                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3618                 encoder_funcs->commit(encoder);
3619         }
3620         /* let the connector get through one full cycle before testing */
3621         intel_wait_for_vblank(dev);
3622
3623         return crtc;
3624 }
3625
3626 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3627 {
3628         struct drm_encoder *encoder = &intel_output->enc;
3629         struct drm_device *dev = encoder->dev;
3630         struct drm_crtc *crtc = encoder->crtc;
3631         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3632         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3633
3634         if (intel_output->load_detect_temp) {
3635                 encoder->crtc = NULL;
3636                 intel_output->base.encoder = NULL;
3637                 intel_output->load_detect_temp = false;
3638                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3639                 drm_helper_disable_unused_functions(dev);
3640         }
3641
3642         /* Switch crtc and output back off if necessary */
3643         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3644                 if (encoder->crtc == crtc)
3645                         encoder_funcs->dpms(encoder, dpms_mode);
3646                 crtc_funcs->dpms(crtc, dpms_mode);
3647         }
3648 }
3649
3650 /* Returns the clock of the currently programmed mode of the given pipe. */
3651 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3652 {
3653         struct drm_i915_private *dev_priv = dev->dev_private;
3654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655         int pipe = intel_crtc->pipe;
3656         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3657         u32 fp;
3658         intel_clock_t clock;
3659
3660         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3661                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3662         else
3663                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3664
3665         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3666         if (IS_IGD(dev)) {
3667                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3668                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3669         } else {
3670                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3671                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3672         }
3673
3674         if (IS_I9XX(dev)) {
3675                 if (IS_IGD(dev))
3676                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3677                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3678                 else
3679                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3680                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3681
3682                 switch (dpll & DPLL_MODE_MASK) {
3683                 case DPLLB_MODE_DAC_SERIAL:
3684                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3685                                 5 : 10;
3686                         break;
3687                 case DPLLB_MODE_LVDS:
3688                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3689                                 7 : 14;
3690                         break;
3691                 default:
3692                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3693                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3694                         return 0;
3695                 }
3696
3697                 /* XXX: Handle the 100Mhz refclk */
3698                 intel_clock(dev, 96000, &clock);
3699         } else {
3700                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3701
3702                 if (is_lvds) {
3703                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3704                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3705                         clock.p2 = 14;
3706
3707                         if ((dpll & PLL_REF_INPUT_MASK) ==
3708                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3709                                 /* XXX: might not be 66MHz */
3710                                 intel_clock(dev, 66000, &clock);
3711                         } else
3712                                 intel_clock(dev, 48000, &clock);
3713                 } else {
3714                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3715                                 clock.p1 = 2;
3716                         else {
3717                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3718                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3719                         }
3720                         if (dpll & PLL_P2_DIVIDE_BY_4)
3721                                 clock.p2 = 4;
3722                         else
3723                                 clock.p2 = 2;
3724
3725                         intel_clock(dev, 48000, &clock);
3726                 }
3727         }
3728
3729         /* XXX: It would be nice to validate the clocks, but we can't reuse
3730          * i830PllIsValid() because it relies on the xf86_config connector
3731          * configuration being accurate, which it isn't necessarily.
3732          */
3733
3734         return clock.dot;
3735 }
3736
3737 /** Returns the currently programmed mode of the given pipe. */
3738 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3739                                              struct drm_crtc *crtc)
3740 {
3741         struct drm_i915_private *dev_priv = dev->dev_private;
3742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743         int pipe = intel_crtc->pipe;
3744         struct drm_display_mode *mode;
3745         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3746         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3747         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3748         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3749
3750         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3751         if (!mode)
3752                 return NULL;
3753
3754         mode->clock = intel_crtc_clock_get(dev, crtc);
3755         mode->hdisplay = (htot & 0xffff) + 1;
3756         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3757         mode->hsync_start = (hsync & 0xffff) + 1;
3758         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3759         mode->vdisplay = (vtot & 0xffff) + 1;
3760         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3761         mode->vsync_start = (vsync & 0xffff) + 1;
3762         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3763
3764         drm_mode_set_name(mode);
3765         drm_mode_set_crtcinfo(mode, 0);
3766
3767         return mode;
3768 }
3769
3770 #define GPU_IDLE_TIMEOUT 500 /* ms */
3771
3772 /* When this timer fires, we've been idle for awhile */
3773 static void intel_gpu_idle_timer(unsigned long arg)
3774 {
3775         struct drm_device *dev = (struct drm_device *)arg;
3776         drm_i915_private_t *dev_priv = dev->dev_private;
3777
3778         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3779
3780         dev_priv->busy = false;
3781
3782         queue_work(dev_priv->wq, &dev_priv->idle_work);
3783 }
3784
3785 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3786 {
3787         drm_i915_private_t *dev_priv = dev->dev_private;
3788
3789         if (IS_IGDNG(dev))
3790                 return;
3791
3792         if (!dev_priv->render_reclock_avail) {
3793                 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3794                 return;
3795         }
3796
3797         /* Restore render clock frequency to original value */
3798         if (IS_G4X(dev) || IS_I9XX(dev))
3799                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3800         else if (IS_I85X(dev))
3801                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3802         DRM_DEBUG_DRIVER("increasing render clock frequency\n");
3803
3804         /* Schedule downclock */
3805         if (schedule)
3806                 mod_timer(&dev_priv->idle_timer, jiffies +
3807                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3808 }
3809
3810 void intel_decrease_renderclock(struct drm_device *dev)
3811 {
3812         drm_i915_private_t *dev_priv = dev->dev_private;
3813
3814         if (IS_IGDNG(dev))
3815                 return;
3816
3817         if (!dev_priv->render_reclock_avail) {
3818                 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3819                 return;
3820         }
3821
3822         if (IS_G4X(dev)) {
3823                 u16 gcfgc;
3824
3825                 /* Adjust render clock... */
3826                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3827
3828                 /* Down to minimum... */
3829                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3830                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3831
3832                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3833         } else if (IS_I965G(dev)) {
3834                 u16 gcfgc;
3835
3836                 /* Adjust render clock... */
3837                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3838
3839                 /* Down to minimum... */
3840                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3841                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3842
3843                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3844         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3845                 u16 gcfgc;
3846
3847                 /* Adjust render clock... */
3848                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3849
3850                 /* Down to minimum... */
3851                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3852                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3853
3854                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3855         } else if (IS_I915G(dev)) {
3856                 u16 gcfgc;
3857
3858                 /* Adjust render clock... */
3859                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3860
3861                 /* Down to minimum... */
3862                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3863                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3864
3865                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3866         } else if (IS_I85X(dev)) {
3867                 u16 hpllcc;
3868
3869                 /* Adjust render clock... */
3870                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3871
3872                 /* Up to maximum... */
3873                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3874                 hpllcc |= GC_CLOCK_133_200;
3875
3876                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3877         }
3878         DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
3879 }
3880
3881 /* Note that no increase function is needed for this - increase_renderclock()
3882  *  will also rewrite these bits
3883  */
3884 void intel_decrease_displayclock(struct drm_device *dev)
3885 {
3886         if (IS_IGDNG(dev))
3887                 return;
3888
3889         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3890             IS_I915GM(dev)) {
3891                 u16 gcfgc;
3892
3893                 /* Adjust render clock... */
3894                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3895
3896                 /* Down to minimum... */
3897                 gcfgc &= ~0xf0;
3898                 gcfgc |= 0x80;
3899
3900                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3901         }
3902 }
3903
3904 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3905
3906 static void intel_crtc_idle_timer(unsigned long arg)
3907 {
3908         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3909         struct drm_crtc *crtc = &intel_crtc->base;
3910         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3911
3912         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3913
3914         intel_crtc->busy = false;
3915
3916         queue_work(dev_priv->wq, &dev_priv->idle_work);
3917 }
3918
3919 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3920 {
3921         struct drm_device *dev = crtc->dev;
3922         drm_i915_private_t *dev_priv = dev->dev_private;
3923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3924         int pipe = intel_crtc->pipe;
3925         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3926         int dpll = I915_READ(dpll_reg);
3927
3928         if (IS_IGDNG(dev))
3929                 return;
3930
3931         if (!dev_priv->lvds_downclock_avail)
3932                 return;
3933
3934         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3935                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3936
3937                 /* Unlock panel regs */
3938                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3939
3940                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3941                 I915_WRITE(dpll_reg, dpll);
3942                 dpll = I915_READ(dpll_reg);
3943                 intel_wait_for_vblank(dev);
3944                 dpll = I915_READ(dpll_reg);
3945                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3946                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3947
3948                 /* ...and lock them again */
3949                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3950         }
3951
3952         /* Schedule downclock */
3953         if (schedule)
3954                 mod_timer(&intel_crtc->idle_timer, jiffies +
3955                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3956 }
3957
3958 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3959 {
3960         struct drm_device *dev = crtc->dev;
3961         drm_i915_private_t *dev_priv = dev->dev_private;
3962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3963         int pipe = intel_crtc->pipe;
3964         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3965         int dpll = I915_READ(dpll_reg);
3966
3967         if (IS_IGDNG(dev))
3968                 return;
3969
3970         if (!dev_priv->lvds_downclock_avail)
3971                 return;
3972
3973         /*
3974          * Since this is called by a timer, we should never get here in
3975          * the manual case.
3976          */
3977         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3978                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3979
3980                 /* Unlock panel regs */
3981                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3982
3983                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3984                 I915_WRITE(dpll_reg, dpll);
3985                 dpll = I915_READ(dpll_reg);
3986                 intel_wait_for_vblank(dev);
3987                 dpll = I915_READ(dpll_reg);
3988                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3989                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3990
3991                 /* ...and lock them again */
3992                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3993         }
3994
3995 }
3996
3997 /**
3998  * intel_idle_update - adjust clocks for idleness
3999  * @work: work struct
4000  *
4001  * Either the GPU or display (or both) went idle.  Check the busy status
4002  * here and adjust the CRTC and GPU clocks as necessary.
4003  */
4004 static void intel_idle_update(struct work_struct *work)
4005 {
4006         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4007                                                     idle_work);
4008         struct drm_device *dev = dev_priv->dev;
4009         struct drm_crtc *crtc;
4010         struct intel_crtc *intel_crtc;
4011
4012         if (!i915_powersave)
4013                 return;
4014
4015         mutex_lock(&dev->struct_mutex);
4016
4017         /* GPU isn't processing, downclock it. */
4018         if (!dev_priv->busy) {
4019                 intel_decrease_renderclock(dev);
4020                 intel_decrease_displayclock(dev);
4021         }
4022
4023         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4024                 /* Skip inactive CRTCs */
4025                 if (!crtc->fb)
4026                         continue;
4027
4028                 intel_crtc = to_intel_crtc(crtc);
4029                 if (!intel_crtc->busy)
4030                         intel_decrease_pllclock(crtc);
4031         }
4032
4033         mutex_unlock(&dev->struct_mutex);
4034 }
4035
4036 /**
4037  * intel_mark_busy - mark the GPU and possibly the display busy
4038  * @dev: drm device
4039  * @obj: object we're operating on
4040  *
4041  * Callers can use this function to indicate that the GPU is busy processing
4042  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4043  * buffer), we'll also mark the display as busy, so we know to increase its
4044  * clock frequency.
4045  */
4046 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4047 {
4048         drm_i915_private_t *dev_priv = dev->dev_private;
4049         struct drm_crtc *crtc = NULL;
4050         struct intel_framebuffer *intel_fb;
4051         struct intel_crtc *intel_crtc;
4052
4053         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4054                 return;
4055
4056         if (!dev_priv->busy) {
4057                 dev_priv->busy = true;
4058                 intel_increase_renderclock(dev, true);
4059         } else {
4060                 mod_timer(&dev_priv->idle_timer, jiffies +
4061                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4062         }
4063
4064         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4065                 if (!crtc->fb)
4066                         continue;
4067
4068                 intel_crtc = to_intel_crtc(crtc);
4069                 intel_fb = to_intel_framebuffer(crtc->fb);
4070                 if (intel_fb->obj == obj) {
4071                         if (!intel_crtc->busy) {
4072                                 /* Non-busy -> busy, upclock */
4073                                 intel_increase_pllclock(crtc, true);
4074                                 intel_crtc->busy = true;
4075                         } else {
4076                                 /* Busy -> busy, put off timer */
4077                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4078                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4079                         }
4080                 }
4081         }
4082 }
4083
4084 static void intel_crtc_destroy(struct drm_crtc *crtc)
4085 {
4086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4087
4088         drm_crtc_cleanup(crtc);
4089         kfree(intel_crtc);
4090 }
4091
4092 struct intel_unpin_work {
4093         struct work_struct work;
4094         struct drm_device *dev;
4095         struct drm_gem_object *obj;
4096         struct drm_pending_vblank_event *event;
4097         int pending;
4098 };
4099
4100 static void intel_unpin_work_fn(struct work_struct *__work)
4101 {
4102         struct intel_unpin_work *work =
4103                 container_of(__work, struct intel_unpin_work, work);
4104
4105         mutex_lock(&work->dev->struct_mutex);
4106         i915_gem_object_unpin(work->obj);
4107         drm_gem_object_unreference(work->obj);
4108         mutex_unlock(&work->dev->struct_mutex);
4109         kfree(work);
4110 }
4111
4112 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4113 {
4114         drm_i915_private_t *dev_priv = dev->dev_private;
4115         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117         struct intel_unpin_work *work;
4118         struct drm_i915_gem_object *obj_priv;
4119         struct drm_pending_vblank_event *e;
4120         struct timeval now;
4121         unsigned long flags;
4122
4123         /* Ignore early vblank irqs */
4124         if (intel_crtc == NULL)
4125                 return;
4126
4127         spin_lock_irqsave(&dev->event_lock, flags);
4128         work = intel_crtc->unpin_work;
4129         if (work == NULL || !work->pending) {
4130                 spin_unlock_irqrestore(&dev->event_lock, flags);
4131                 return;
4132         }
4133
4134         intel_crtc->unpin_work = NULL;
4135         drm_vblank_put(dev, intel_crtc->pipe);
4136
4137         if (work->event) {
4138                 e = work->event;
4139                 do_gettimeofday(&now);
4140                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4141                 e->event.tv_sec = now.tv_sec;
4142                 e->event.tv_usec = now.tv_usec;
4143                 list_add_tail(&e->base.link,
4144                               &e->base.file_priv->event_list);
4145                 wake_up_interruptible(&e->base.file_priv->event_wait);
4146         }
4147
4148         spin_unlock_irqrestore(&dev->event_lock, flags);
4149
4150         obj_priv = work->obj->driver_private;
4151         if (atomic_dec_and_test(&obj_priv->pending_flip))
4152                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4153         schedule_work(&work->work);
4154 }
4155
4156 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4157 {
4158         drm_i915_private_t *dev_priv = dev->dev_private;
4159         struct intel_crtc *intel_crtc =
4160                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4161         unsigned long flags;
4162
4163         spin_lock_irqsave(&dev->event_lock, flags);
4164         if (intel_crtc->unpin_work)
4165                 intel_crtc->unpin_work->pending = 1;
4166         spin_unlock_irqrestore(&dev->event_lock, flags);
4167 }
4168
4169 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4170                                 struct drm_framebuffer *fb,
4171                                 struct drm_pending_vblank_event *event)
4172 {
4173         struct drm_device *dev = crtc->dev;
4174         struct drm_i915_private *dev_priv = dev->dev_private;
4175         struct intel_framebuffer *intel_fb;
4176         struct drm_i915_gem_object *obj_priv;
4177         struct drm_gem_object *obj;
4178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179         struct intel_unpin_work *work;
4180         unsigned long flags;
4181         int ret;
4182         RING_LOCALS;
4183
4184         work = kzalloc(sizeof *work, GFP_KERNEL);
4185         if (work == NULL)
4186                 return -ENOMEM;
4187
4188         mutex_lock(&dev->struct_mutex);
4189
4190         work->event = event;
4191         work->dev = crtc->dev;
4192         intel_fb = to_intel_framebuffer(crtc->fb);
4193         work->obj = intel_fb->obj;
4194         INIT_WORK(&work->work, intel_unpin_work_fn);
4195
4196         /* We borrow the event spin lock for protecting unpin_work */
4197         spin_lock_irqsave(&dev->event_lock, flags);
4198         if (intel_crtc->unpin_work) {
4199                 spin_unlock_irqrestore(&dev->event_lock, flags);
4200                 kfree(work);
4201                 mutex_unlock(&dev->struct_mutex);
4202                 return -EBUSY;
4203         }
4204         intel_crtc->unpin_work = work;
4205         spin_unlock_irqrestore(&dev->event_lock, flags);
4206
4207         intel_fb = to_intel_framebuffer(fb);
4208         obj = intel_fb->obj;
4209
4210         ret = intel_pin_and_fence_fb_obj(dev, obj);
4211         if (ret != 0) {
4212                 kfree(work);
4213                 mutex_unlock(&dev->struct_mutex);
4214                 return ret;
4215         }
4216
4217         /* Reference the old fb object for the scheduled work. */
4218         drm_gem_object_reference(work->obj);
4219
4220         crtc->fb = fb;
4221         i915_gem_object_flush_write_domain(obj);
4222         drm_vblank_get(dev, intel_crtc->pipe);
4223         obj_priv = obj->driver_private;
4224         atomic_inc(&obj_priv->pending_flip);
4225
4226         BEGIN_LP_RING(4);
4227         OUT_RING(MI_DISPLAY_FLIP |
4228                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4229         OUT_RING(fb->pitch);
4230         OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4231         OUT_RING((fb->width << 16) | fb->height);
4232         ADVANCE_LP_RING();
4233
4234         mutex_unlock(&dev->struct_mutex);
4235
4236         return 0;
4237 }
4238
4239 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4240         .dpms = intel_crtc_dpms,
4241         .mode_fixup = intel_crtc_mode_fixup,
4242         .mode_set = intel_crtc_mode_set,
4243         .mode_set_base = intel_pipe_set_base,
4244         .prepare = intel_crtc_prepare,
4245         .commit = intel_crtc_commit,
4246         .load_lut = intel_crtc_load_lut,
4247 };
4248
4249 static const struct drm_crtc_funcs intel_crtc_funcs = {
4250         .cursor_set = intel_crtc_cursor_set,
4251         .cursor_move = intel_crtc_cursor_move,
4252         .gamma_set = intel_crtc_gamma_set,
4253         .set_config = drm_crtc_helper_set_config,
4254         .destroy = intel_crtc_destroy,
4255         .page_flip = intel_crtc_page_flip,
4256 };
4257
4258
4259 static void intel_crtc_init(struct drm_device *dev, int pipe)
4260 {
4261         struct intel_crtc *intel_crtc;
4262         int i;
4263
4264         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4265         if (intel_crtc == NULL)
4266                 return;
4267
4268         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4269
4270         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4271         intel_crtc->pipe = pipe;
4272         intel_crtc->plane = pipe;
4273         for (i = 0; i < 256; i++) {
4274                 intel_crtc->lut_r[i] = i;
4275                 intel_crtc->lut_g[i] = i;
4276                 intel_crtc->lut_b[i] = i;
4277         }
4278
4279         /* Swap pipes & planes for FBC on pre-965 */
4280         intel_crtc->pipe = pipe;
4281         intel_crtc->plane = pipe;
4282         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4283                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4284                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4285         }
4286
4287         intel_crtc->cursor_addr = 0;
4288         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4289         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4290
4291         intel_crtc->busy = false;
4292
4293         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4294                     (unsigned long)intel_crtc);
4295 }
4296
4297 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4298                                 struct drm_file *file_priv)
4299 {
4300         drm_i915_private_t *dev_priv = dev->dev_private;
4301         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4302         struct drm_mode_object *drmmode_obj;
4303         struct intel_crtc *crtc;
4304
4305         if (!dev_priv) {
4306                 DRM_ERROR("called with no initialization\n");
4307                 return -EINVAL;
4308         }
4309
4310         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4311                         DRM_MODE_OBJECT_CRTC);
4312
4313         if (!drmmode_obj) {
4314                 DRM_ERROR("no such CRTC id\n");
4315                 return -EINVAL;
4316         }
4317
4318         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4319         pipe_from_crtc_id->pipe = crtc->pipe;
4320
4321         return 0;
4322 }
4323
4324 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4325 {
4326         struct drm_crtc *crtc = NULL;
4327
4328         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4329                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4330                 if (intel_crtc->pipe == pipe)
4331                         break;
4332         }
4333         return crtc;
4334 }
4335
4336 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4337 {
4338         int index_mask = 0;
4339         struct drm_connector *connector;
4340         int entry = 0;
4341
4342         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4343                 struct intel_output *intel_output = to_intel_output(connector);
4344                 if (type_mask & intel_output->clone_mask)
4345                         index_mask |= (1 << entry);
4346                 entry++;
4347         }
4348         return index_mask;
4349 }
4350
4351
4352 static void intel_setup_outputs(struct drm_device *dev)
4353 {
4354         struct drm_i915_private *dev_priv = dev->dev_private;
4355         struct drm_connector *connector;
4356
4357         intel_crt_init(dev);
4358
4359         /* Set up integrated LVDS */
4360         if (IS_MOBILE(dev) && !IS_I830(dev))
4361                 intel_lvds_init(dev);
4362
4363         if (IS_IGDNG(dev)) {
4364                 int found;
4365
4366                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4367                         intel_dp_init(dev, DP_A);
4368
4369                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4370                         /* check SDVOB */
4371                         /* found = intel_sdvo_init(dev, HDMIB); */
4372                         found = 0;
4373                         if (!found)
4374                                 intel_hdmi_init(dev, HDMIB);
4375                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4376                                 intel_dp_init(dev, PCH_DP_B);
4377                 }
4378
4379                 if (I915_READ(HDMIC) & PORT_DETECTED)
4380                         intel_hdmi_init(dev, HDMIC);
4381
4382                 if (I915_READ(HDMID) & PORT_DETECTED)
4383                         intel_hdmi_init(dev, HDMID);
4384
4385                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4386                         intel_dp_init(dev, PCH_DP_C);
4387
4388                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4389                         intel_dp_init(dev, PCH_DP_D);
4390
4391         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4392                 bool found = false;
4393
4394                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4395                         found = intel_sdvo_init(dev, SDVOB);
4396                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4397                                 intel_hdmi_init(dev, SDVOB);
4398
4399                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
4400                                 intel_dp_init(dev, DP_B);
4401                 }
4402
4403                 /* Before G4X SDVOC doesn't have its own detect register */
4404
4405                 if (I915_READ(SDVOB) & SDVO_DETECTED)
4406                         found = intel_sdvo_init(dev, SDVOC);
4407
4408                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4409
4410                         if (SUPPORTS_INTEGRATED_HDMI(dev))
4411                                 intel_hdmi_init(dev, SDVOC);
4412                         if (SUPPORTS_INTEGRATED_DP(dev))
4413                                 intel_dp_init(dev, DP_C);
4414                 }
4415
4416                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4417                         intel_dp_init(dev, DP_D);
4418         } else if (IS_I8XX(dev))
4419                 intel_dvo_init(dev);
4420
4421         if (SUPPORTS_TV(dev))
4422                 intel_tv_init(dev);
4423
4424         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4425                 struct intel_output *intel_output = to_intel_output(connector);
4426                 struct drm_encoder *encoder = &intel_output->enc;
4427
4428                 encoder->possible_crtcs = intel_output->crtc_mask;
4429                 encoder->possible_clones = intel_connector_clones(dev,
4430                                                 intel_output->clone_mask);
4431         }
4432 }
4433
4434 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4435 {
4436         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4437         struct drm_device *dev = fb->dev;
4438
4439         if (fb->fbdev)
4440                 intelfb_remove(dev, fb);
4441
4442         drm_framebuffer_cleanup(fb);
4443         mutex_lock(&dev->struct_mutex);
4444         drm_gem_object_unreference(intel_fb->obj);
4445         mutex_unlock(&dev->struct_mutex);
4446
4447         kfree(intel_fb);
4448 }
4449
4450 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4451                                                 struct drm_file *file_priv,
4452                                                 unsigned int *handle)
4453 {
4454         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4455         struct drm_gem_object *object = intel_fb->obj;
4456
4457         return drm_gem_handle_create(file_priv, object, handle);
4458 }
4459
4460 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4461         .destroy = intel_user_framebuffer_destroy,
4462         .create_handle = intel_user_framebuffer_create_handle,
4463 };
4464
4465 int intel_framebuffer_create(struct drm_device *dev,
4466                              struct drm_mode_fb_cmd *mode_cmd,
4467                              struct drm_framebuffer **fb,
4468                              struct drm_gem_object *obj)
4469 {
4470         struct intel_framebuffer *intel_fb;
4471         int ret;
4472
4473         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4474         if (!intel_fb)
4475                 return -ENOMEM;
4476
4477         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4478         if (ret) {
4479                 DRM_ERROR("framebuffer init failed %d\n", ret);
4480                 return ret;
4481         }
4482
4483         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4484
4485         intel_fb->obj = obj;
4486
4487         *fb = &intel_fb->base;
4488
4489         return 0;
4490 }
4491
4492
4493 static struct drm_framebuffer *
4494 intel_user_framebuffer_create(struct drm_device *dev,
4495                               struct drm_file *filp,
4496                               struct drm_mode_fb_cmd *mode_cmd)
4497 {
4498         struct drm_gem_object *obj;
4499         struct drm_framebuffer *fb;
4500         int ret;
4501
4502         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4503         if (!obj)
4504                 return NULL;
4505
4506         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4507         if (ret) {
4508                 mutex_lock(&dev->struct_mutex);
4509                 drm_gem_object_unreference(obj);
4510                 mutex_unlock(&dev->struct_mutex);
4511                 return NULL;
4512         }
4513
4514         return fb;
4515 }
4516
4517 static const struct drm_mode_config_funcs intel_mode_funcs = {
4518         .fb_create = intel_user_framebuffer_create,
4519         .fb_changed = intelfb_probe,
4520 };
4521
4522 void intel_init_clock_gating(struct drm_device *dev)
4523 {
4524         struct drm_i915_private *dev_priv = dev->dev_private;
4525
4526         /*
4527          * Disable clock gating reported to work incorrectly according to the
4528          * specs, but enable as much else as we can.
4529          */
4530         if (IS_IGDNG(dev)) {
4531                 return;
4532         } else if (IS_G4X(dev)) {
4533                 uint32_t dspclk_gate;
4534                 I915_WRITE(RENCLK_GATE_D1, 0);
4535                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4536                        GS_UNIT_CLOCK_GATE_DISABLE |
4537                        CL_UNIT_CLOCK_GATE_DISABLE);
4538                 I915_WRITE(RAMCLK_GATE_D, 0);
4539                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4540                         OVRUNIT_CLOCK_GATE_DISABLE |
4541                         OVCUNIT_CLOCK_GATE_DISABLE;
4542                 if (IS_GM45(dev))
4543                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4544                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4545         } else if (IS_I965GM(dev)) {
4546                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4547                 I915_WRITE(RENCLK_GATE_D2, 0);
4548                 I915_WRITE(DSPCLK_GATE_D, 0);
4549                 I915_WRITE(RAMCLK_GATE_D, 0);
4550                 I915_WRITE16(DEUC, 0);
4551         } else if (IS_I965G(dev)) {
4552                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4553                        I965_RCC_CLOCK_GATE_DISABLE |
4554                        I965_RCPB_CLOCK_GATE_DISABLE |
4555                        I965_ISC_CLOCK_GATE_DISABLE |
4556                        I965_FBC_CLOCK_GATE_DISABLE);
4557                 I915_WRITE(RENCLK_GATE_D2, 0);
4558         } else if (IS_I9XX(dev)) {
4559                 u32 dstate = I915_READ(D_STATE);
4560
4561                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4562                         DSTATE_DOT_CLOCK_GATING;
4563                 I915_WRITE(D_STATE, dstate);
4564         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4565                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4566         } else if (IS_I830(dev)) {
4567                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4568         }
4569
4570         /*
4571          * GPU can automatically power down the render unit if given a page
4572          * to save state.
4573          */
4574         if (I915_HAS_RC6(dev)) {
4575                 struct drm_gem_object *pwrctx;
4576                 struct drm_i915_gem_object *obj_priv;
4577                 int ret;
4578
4579                 pwrctx = drm_gem_object_alloc(dev, 4096);
4580                 if (!pwrctx) {
4581                         DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4582                         goto out;
4583                 }
4584
4585                 ret = i915_gem_object_pin(pwrctx, 4096);
4586                 if (ret) {
4587                         DRM_ERROR("failed to pin power context: %d\n", ret);
4588                         drm_gem_object_unreference(pwrctx);
4589                         goto out;
4590                 }
4591
4592                 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4593
4594                 obj_priv = pwrctx->driver_private;
4595
4596                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4597                 I915_WRITE(MCHBAR_RENDER_STANDBY,
4598                            I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4599
4600                 dev_priv->pwrctx = pwrctx;
4601         }
4602
4603 out:
4604         return;
4605 }
4606
4607 /* Set up chip specific display functions */
4608 static void intel_init_display(struct drm_device *dev)
4609 {
4610         struct drm_i915_private *dev_priv = dev->dev_private;
4611
4612         /* We always want a DPMS function */
4613         if (IS_IGDNG(dev))
4614                 dev_priv->display.dpms = igdng_crtc_dpms;
4615         else
4616                 dev_priv->display.dpms = i9xx_crtc_dpms;
4617
4618         /* Only mobile has FBC, leave pointers NULL for other chips */
4619         if (IS_MOBILE(dev)) {
4620                 if (IS_GM45(dev)) {
4621                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4622                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4623                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4624                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4625                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4626                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4627                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4628                 }
4629                 /* 855GM needs testing */
4630         }
4631
4632         /* Returns the core display clock speed */
4633         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_IGDGM(dev)))
4634                 dev_priv->display.get_display_clock_speed =
4635                         i945_get_display_clock_speed;
4636         else if (IS_I915G(dev))
4637                 dev_priv->display.get_display_clock_speed =
4638                         i915_get_display_clock_speed;
4639         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4640                 dev_priv->display.get_display_clock_speed =
4641                         i9xx_misc_get_display_clock_speed;
4642         else if (IS_I915GM(dev))
4643                 dev_priv->display.get_display_clock_speed =
4644                         i915gm_get_display_clock_speed;
4645         else if (IS_I865G(dev))
4646                 dev_priv->display.get_display_clock_speed =
4647                         i865_get_display_clock_speed;
4648         else if (IS_I85X(dev))
4649                 dev_priv->display.get_display_clock_speed =
4650                         i855_get_display_clock_speed;
4651         else /* 852, 830 */
4652                 dev_priv->display.get_display_clock_speed =
4653                         i830_get_display_clock_speed;
4654
4655         /* For FIFO watermark updates */
4656         if (IS_IGDNG(dev))
4657                 dev_priv->display.update_wm = NULL;
4658         else if (IS_G4X(dev))
4659                 dev_priv->display.update_wm = g4x_update_wm;
4660         else if (IS_I965G(dev))
4661                 dev_priv->display.update_wm = i965_update_wm;
4662         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4663                 dev_priv->display.update_wm = i9xx_update_wm;
4664                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4665         } else {
4666                 if (IS_I85X(dev))
4667                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4668                 else if (IS_845G(dev))
4669                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4670                 else
4671                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4672                 dev_priv->display.update_wm = i830_update_wm;
4673         }
4674 }
4675
4676 void intel_modeset_init(struct drm_device *dev)
4677 {
4678         struct drm_i915_private *dev_priv = dev->dev_private;
4679         int num_pipe;
4680         int i;
4681
4682         drm_mode_config_init(dev);
4683
4684         dev->mode_config.min_width = 0;
4685         dev->mode_config.min_height = 0;
4686
4687         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4688
4689         intel_init_display(dev);
4690
4691         if (IS_I965G(dev)) {
4692                 dev->mode_config.max_width = 8192;
4693                 dev->mode_config.max_height = 8192;
4694         } else if (IS_I9XX(dev)) {
4695                 dev->mode_config.max_width = 4096;
4696                 dev->mode_config.max_height = 4096;
4697         } else {
4698                 dev->mode_config.max_width = 2048;
4699                 dev->mode_config.max_height = 2048;
4700         }
4701
4702         /* set memory base */
4703         if (IS_I9XX(dev))
4704                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4705         else
4706                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4707
4708         if (IS_MOBILE(dev) || IS_I9XX(dev))
4709                 num_pipe = 2;
4710         else
4711                 num_pipe = 1;
4712         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4713                   num_pipe, num_pipe > 1 ? "s" : "");
4714
4715         if (IS_I85X(dev))
4716                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4717         else if (IS_I9XX(dev) || IS_G4X(dev))
4718                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4719
4720         for (i = 0; i < num_pipe; i++) {
4721                 intel_crtc_init(dev, i);
4722         }
4723
4724         intel_setup_outputs(dev);
4725
4726         intel_init_clock_gating(dev);
4727
4728         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4729         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4730                     (unsigned long)dev);
4731
4732         intel_setup_overlay(dev);
4733 }
4734
4735 void intel_modeset_cleanup(struct drm_device *dev)
4736 {
4737         struct drm_i915_private *dev_priv = dev->dev_private;
4738         struct drm_crtc *crtc;
4739         struct intel_crtc *intel_crtc;
4740
4741         mutex_lock(&dev->struct_mutex);
4742
4743         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4744                 /* Skip inactive CRTCs */
4745                 if (!crtc->fb)
4746                         continue;
4747
4748                 intel_crtc = to_intel_crtc(crtc);
4749                 intel_increase_pllclock(crtc, false);
4750                 del_timer_sync(&intel_crtc->idle_timer);
4751         }
4752
4753         intel_increase_renderclock(dev, false);
4754         del_timer_sync(&dev_priv->idle_timer);
4755
4756         if (dev_priv->display.disable_fbc)
4757                 dev_priv->display.disable_fbc(dev);
4758
4759         if (dev_priv->pwrctx) {
4760                 struct drm_i915_gem_object *obj_priv;
4761
4762                 obj_priv = dev_priv->pwrctx->driver_private;
4763                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4764                 I915_READ(PWRCTXA);
4765                 i915_gem_object_unpin(dev_priv->pwrctx);
4766                 drm_gem_object_unreference(dev_priv->pwrctx);
4767         }
4768
4769         mutex_unlock(&dev->struct_mutex);
4770
4771         drm_mode_config_cleanup(dev);
4772 }
4773
4774
4775 /* current intel driver doesn't take advantage of encoders
4776    always give back the encoder for the connector
4777 */
4778 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4779 {
4780         struct intel_output *intel_output = to_intel_output(connector);
4781
4782         return &intel_output->enc;
4783 }
4784
4785 /*
4786  * set vga decode state - true == enable VGA decode
4787  */
4788 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4789 {
4790         struct drm_i915_private *dev_priv = dev->dev_private;
4791         u16 gmch_ctrl;
4792
4793         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4794         if (state)
4795                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4796         else
4797                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4798         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4799         return 0;
4800 }