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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "drm_dp_helper.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73 };
  74
  75 #define I8XX_DOT_MIN              25000
  76 #define I8XX_DOT_MAX             350000
  77 #define I8XX_VCO_MIN             930000
  78 #define I8XX_VCO_MAX            1400000
  79 #define I8XX_N_MIN                    3
  80 #define I8XX_N_MAX                   16
  81 #define I8XX_M_MIN                   96
  82 #define I8XX_M_MAX                  140
  83 #define I8XX_M1_MIN                  18
  84 #define I8XX_M1_MAX                  26
  85 #define I8XX_M2_MIN                   6
  86 #define I8XX_M2_MAX                  16
  87 #define I8XX_P_MIN                    4
  88 #define I8XX_P_MAX                  128
  89 #define I8XX_P1_MIN                   2
  90 #define I8XX_P1_MAX                  33
  91 #define I8XX_P1_LVDS_MIN              1
  92 #define I8XX_P1_LVDS_MAX              6
  93 #define I8XX_P2_SLOW                  4
  94 #define I8XX_P2_FAST                  2
  95 #define I8XX_P2_LVDS_SLOW             14
  96 #define I8XX_P2_LVDS_FAST             7
  97 #define I8XX_P2_SLOW_LIMIT       165000
  98
  99 #define I9XX_DOT_MIN              20000
 100 #define I9XX_DOT_MAX             400000
 101 #define I9XX_VCO_MIN            1400000
 102 #define I9XX_VCO_MAX            2800000
 103 #define PINEVIEW_VCO_MIN                1700000
 104 #define PINEVIEW_VCO_MAX                3500000
 105 #define I9XX_N_MIN                    1
 106 #define I9XX_N_MAX                    6
 107 /* Pineview's Ncounter is a ring counter */
 108 #define PINEVIEW_N_MIN                3
 109 #define PINEVIEW_N_MAX                6
 110 #define I9XX_M_MIN                   70
 111 #define I9XX_M_MAX                  120
 112 #define PINEVIEW_M_MIN                2
 113 #define PINEVIEW_M_MAX              256
 114 #define I9XX_M1_MIN                  10
 115 #define I9XX_M1_MAX                  22
 116 #define I9XX_M2_MIN                   5
 117 #define I9XX_M2_MAX                   9
 118 /* Pineview M1 is reserved, and must be 0 */
 119 #define PINEVIEW_M1_MIN               0
 120 #define PINEVIEW_M1_MAX               0
 121 #define PINEVIEW_M2_MIN               0
 122 #define PINEVIEW_M2_MAX               254
 123 #define I9XX_P_SDVO_DAC_MIN           5
 124 #define I9XX_P_SDVO_DAC_MAX          80
 125 #define I9XX_P_LVDS_MIN               7
 126 #define I9XX_P_LVDS_MAX              98
 127 #define PINEVIEW_P_LVDS_MIN                   7
 128 #define PINEVIEW_P_LVDS_MAX                  112
 129 #define I9XX_P1_MIN                   1
 130 #define I9XX_P1_MAX                   8
 131 #define I9XX_P2_SDVO_DAC_SLOW                10
 132 #define I9XX_P2_SDVO_DAC_FAST                 5
 133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 134 #define I9XX_P2_LVDS_SLOW                    14
 135 #define I9XX_P2_LVDS_FAST                     7
 136 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 137
 138 /*The parameter is for SDVO on G4x platform*/
 139 #define G4X_DOT_SDVO_MIN           25000
 140 #define G4X_DOT_SDVO_MAX           270000
 141 #define G4X_VCO_MIN                1750000
 142 #define G4X_VCO_MAX                3500000
 143 #define G4X_N_SDVO_MIN             1
 144 #define G4X_N_SDVO_MAX             4
 145 #define G4X_M_SDVO_MIN             104
 146 #define G4X_M_SDVO_MAX             138
 147 #define G4X_M1_SDVO_MIN            17
 148 #define G4X_M1_SDVO_MAX            23
 149 #define G4X_M2_SDVO_MIN            5
 150 #define G4X_M2_SDVO_MAX            11
 151 #define G4X_P_SDVO_MIN             10
 152 #define G4X_P_SDVO_MAX             30
 153 #define G4X_P1_SDVO_MIN            1
 154 #define G4X_P1_SDVO_MAX            3
 155 #define G4X_P2_SDVO_SLOW           10
 156 #define G4X_P2_SDVO_FAST           10
 157 #define G4X_P2_SDVO_LIMIT          270000
 158
 159 /*The parameter is for HDMI_DAC on G4x platform*/
 160 #define G4X_DOT_HDMI_DAC_MIN           22000
 161 #define G4X_DOT_HDMI_DAC_MAX           400000
 162 #define G4X_N_HDMI_DAC_MIN             1
 163 #define G4X_N_HDMI_DAC_MAX             4
 164 #define G4X_M_HDMI_DAC_MIN             104
 165 #define G4X_M_HDMI_DAC_MAX             138
 166 #define G4X_M1_HDMI_DAC_MIN            16
 167 #define G4X_M1_HDMI_DAC_MAX            23
 168 #define G4X_M2_HDMI_DAC_MIN            5
 169 #define G4X_M2_HDMI_DAC_MAX            11
 170 #define G4X_P_HDMI_DAC_MIN             5
 171 #define G4X_P_HDMI_DAC_MAX             80
 172 #define G4X_P1_HDMI_DAC_MIN            1
 173 #define G4X_P1_HDMI_DAC_MAX            8
 174 #define G4X_P2_HDMI_DAC_SLOW           10
 175 #define G4X_P2_HDMI_DAC_FAST           5
 176 #define G4X_P2_HDMI_DAC_LIMIT          165000
 177
 178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 196
 197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 215
 216 /*The parameter is for DISPLAY PORT on G4x platform*/
 217 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 218 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 219 #define G4X_N_DISPLAY_PORT_MIN             1
 220 #define G4X_N_DISPLAY_PORT_MAX             2
 221 #define G4X_M_DISPLAY_PORT_MIN             97
 222 #define G4X_M_DISPLAY_PORT_MAX             108
 223 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 224 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 225 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 226 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 227 #define G4X_P_DISPLAY_PORT_MIN             10
 228 #define G4X_P_DISPLAY_PORT_MAX             20
 229 #define G4X_P1_DISPLAY_PORT_MIN            1
 230 #define G4X_P1_DISPLAY_PORT_MAX            2
 231 #define G4X_P2_DISPLAY_PORT_SLOW           10
 232 #define G4X_P2_DISPLAY_PORT_FAST           10
 233 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 234
 235 /* Ironlake / Sandybridge */
 236 /* as we calculate clock using (register_value + 2) for
 237    N/M1/M2, so here the range value for them is (actual_value-2).
 238  */
 239 #define IRONLAKE_DOT_MIN         25000
 240 #define IRONLAKE_DOT_MAX         350000
 241 #define IRONLAKE_VCO_MIN         1760000
 242 #define IRONLAKE_VCO_MAX         3510000
 243 #define IRONLAKE_M1_MIN          12
 244 #define IRONLAKE_M1_MAX          22
 245 #define IRONLAKE_M2_MIN          5
 246 #define IRONLAKE_M2_MAX          9
 247 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 248
 249 /* We have parameter ranges for different type of outputs. */
 250
 251 /* DAC & HDMI Refclk 120Mhz */
 252 #define IRONLAKE_DAC_N_MIN      1
 253 #define IRONLAKE_DAC_N_MAX      5
 254 #define IRONLAKE_DAC_M_MIN      79
 255 #define IRONLAKE_DAC_M_MAX      127
 256 #define IRONLAKE_DAC_P_MIN      5
 257 #define IRONLAKE_DAC_P_MAX      80
 258 #define IRONLAKE_DAC_P1_MIN     1
 259 #define IRONLAKE_DAC_P1_MAX     8
 260 #define IRONLAKE_DAC_P2_SLOW    10
 261 #define IRONLAKE_DAC_P2_FAST    5
 262
 263 /* LVDS single-channel 120Mhz refclk */
 264 #define IRONLAKE_LVDS_S_N_MIN   1
 265 #define IRONLAKE_LVDS_S_N_MAX   3
 266 #define IRONLAKE_LVDS_S_M_MIN   79
 267 #define IRONLAKE_LVDS_S_M_MAX   118
 268 #define IRONLAKE_LVDS_S_P_MIN   28
 269 #define IRONLAKE_LVDS_S_P_MAX   112
 270 #define IRONLAKE_LVDS_S_P1_MIN  2
 271 #define IRONLAKE_LVDS_S_P1_MAX  8
 272 #define IRONLAKE_LVDS_S_P2_SLOW 14
 273 #define IRONLAKE_LVDS_S_P2_FAST 14
 274
 275 /* LVDS dual-channel 120Mhz refclk */
 276 #define IRONLAKE_LVDS_D_N_MIN   1
 277 #define IRONLAKE_LVDS_D_N_MAX   3
 278 #define IRONLAKE_LVDS_D_M_MIN   79
 279 #define IRONLAKE_LVDS_D_M_MAX   127
 280 #define IRONLAKE_LVDS_D_P_MIN   14
 281 #define IRONLAKE_LVDS_D_P_MAX   56
 282 #define IRONLAKE_LVDS_D_P1_MIN  2
 283 #define IRONLAKE_LVDS_D_P1_MAX  8
 284 #define IRONLAKE_LVDS_D_P2_SLOW 7
 285 #define IRONLAKE_LVDS_D_P2_FAST 7
 286
 287 /* LVDS single-channel 100Mhz refclk */
 288 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 289 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 290 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 291 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 292 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 293 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 294 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 295 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 296 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 297 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 298
 299 /* LVDS dual-channel 100Mhz refclk */
 300 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 301 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 302 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 303 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 304 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 305 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 306 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 307 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 308 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 309 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 310
 311 /* DisplayPort */
 312 #define IRONLAKE_DP_N_MIN               1
 313 #define IRONLAKE_DP_N_MAX               2
 314 #define IRONLAKE_DP_M_MIN               81
 315 #define IRONLAKE_DP_M_MAX               90
 316 #define IRONLAKE_DP_P_MIN               10
 317 #define IRONLAKE_DP_P_MAX               20
 318 #define IRONLAKE_DP_P2_FAST             10
 319 #define IRONLAKE_DP_P2_SLOW             10
 320 #define IRONLAKE_DP_P2_LIMIT            0
 321 #define IRONLAKE_DP_P1_MIN              1
 322 #define IRONLAKE_DP_P1_MAX              2
 323
 324 static bool
 325 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 326                     int target, int refclk, intel_clock_t *best_clock);
 327 static bool
 328 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 329                         int target, int refclk, intel_clock_t *best_clock);
 330
 331 static bool
 332 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 333                       int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 336                            int target, int refclk, intel_clock_t *best_clock);
 337
 338 static const intel_limit_t intel_limits_i8xx_dvo = {
 339         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 340         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 341         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 342         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 343         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 344         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 345         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 346         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 347         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 348                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 349         .find_pll = intel_find_best_PLL,
 350 };
 351
 352 static const intel_limit_t intel_limits_i8xx_lvds = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i9xx_sdvo = {
 367         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 368         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 369         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 370         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 371         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 372         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 373         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 374         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 375         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 376                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_lvds = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         /* The single-channel range is 25-112Mhz, and dual-channel
 390          * is 80-224Mhz.  Prefer single channel as much as possible.
 391          */
 392         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397     /* below parameter and function is for G4X Chipset Family*/
 398 static const intel_limit_t intel_limits_g4x_sdvo = {
 399         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 400         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 401         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 402         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 403         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 404         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 405         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 406         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 407         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 408                  .p2_slow = G4X_P2_SDVO_SLOW,
 409                  .p2_fast = G4X_P2_SDVO_FAST
 410         },
 411         .find_pll = intel_g4x_find_best_PLL,
 412 };
 413
 414 static const intel_limit_t intel_limits_g4x_hdmi = {
 415         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 416         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 417         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 418         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 419         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 420         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 421         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 422         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 423         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 424                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 425                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 426         },
 427         .find_pll = intel_g4x_find_best_PLL,
 428 };
 429
 430 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 431         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 432                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 433         .vco = { .min = G4X_VCO_MIN,
 434                  .max = G4X_VCO_MAX },
 435         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 436                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 437         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 438                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 439         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 440                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 441         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 442                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 443         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 444                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 445         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 447         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 448                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 449                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 450         },
 451         .find_pll = intel_g4x_find_best_PLL,
 452 };
 453
 454 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 455         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 456                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 457         .vco = { .min = G4X_VCO_MIN,
 458                  .max = G4X_VCO_MAX },
 459         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 460                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 461         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 462                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 463         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 464                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 465         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 466                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 467         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 468                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 469         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 471         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 472                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 473                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 474         },
 475         .find_pll = intel_g4x_find_best_PLL,
 476 };
 477
 478 static const intel_limit_t intel_limits_g4x_display_port = {
 479         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 480                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 481         .vco = { .min = G4X_VCO_MIN,
 482                  .max = G4X_VCO_MAX},
 483         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 484                  .max = G4X_N_DISPLAY_PORT_MAX },
 485         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 486                  .max = G4X_M_DISPLAY_PORT_MAX },
 487         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 488                  .max = G4X_M1_DISPLAY_PORT_MAX },
 489         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 490                  .max = G4X_M2_DISPLAY_PORT_MAX },
 491         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 492                  .max = G4X_P_DISPLAY_PORT_MAX },
 493         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 494                  .max = G4X_P1_DISPLAY_PORT_MAX},
 495         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 496                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 497                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 498         .find_pll = intel_find_pll_g4x_dp,
 499 };
 500
 501 static const intel_limit_t intel_limits_pineview_sdvo = {
 502         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 503         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 504         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 505         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 506         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 507         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 508         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 509         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 510         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 511                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 512         .find_pll = intel_find_best_PLL,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_lvds = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         /* Pineview only supports single-channel mode. */
 525         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 526                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 527         .find_pll = intel_find_best_PLL,
 528 };
 529
 530 static const intel_limit_t intel_limits_ironlake_dac = {
 531         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 532         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 533         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 534         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 535         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 536         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 537         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 538         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 539         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 540                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 541                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 542         .find_pll = intel_g4x_find_best_PLL,
 543 };
 544
 545 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 546         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 547         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 548         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 549         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 550         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 551         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 552         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 553         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 554         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 555                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 556                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 557         .find_pll = intel_g4x_find_best_PLL,
 558 };
 559
 560 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 561         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 562         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 563         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 564         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 565         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 566         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 567         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 568         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 569         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 570                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 571                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 572         .find_pll = intel_g4x_find_best_PLL,
 573 };
 574
 575 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 576         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 577         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 578         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 579         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 580         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 581         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 582         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 583         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 584         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 585                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 586                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 587         .find_pll = intel_g4x_find_best_PLL,
 588 };
 589
 590 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 591         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 592         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 593         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 594         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 595         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 596         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 597         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 598         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 599         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 600                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 601                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 602         .find_pll = intel_g4x_find_best_PLL,
 603 };
 604
 605 static const intel_limit_t intel_limits_ironlake_display_port = {
 606         .dot = { .min = IRONLAKE_DOT_MIN,
 607                  .max = IRONLAKE_DOT_MAX },
 608         .vco = { .min = IRONLAKE_VCO_MIN,
 609                  .max = IRONLAKE_VCO_MAX},
 610         .n   = { .min = IRONLAKE_DP_N_MIN,
 611                  .max = IRONLAKE_DP_N_MAX },
 612         .m   = { .min = IRONLAKE_DP_M_MIN,
 613                  .max = IRONLAKE_DP_M_MAX },
 614         .m1  = { .min = IRONLAKE_M1_MIN,
 615                  .max = IRONLAKE_M1_MAX },
 616         .m2  = { .min = IRONLAKE_M2_MIN,
 617                  .max = IRONLAKE_M2_MAX },
 618         .p   = { .min = IRONLAKE_DP_P_MIN,
 619                  .max = IRONLAKE_DP_P_MAX },
 620         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 621                  .max = IRONLAKE_DP_P1_MAX},
 622         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 623                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 624                  .p2_fast = IRONLAKE_DP_P2_FAST },
 625         .find_pll = intel_find_pll_ironlake_dp,
 626 };
 627
 628 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         struct drm_i915_private *dev_priv = dev->dev_private;
 632         const intel_limit_t *limit;
 633         int refclk = 120;
 634
 635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 636                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 637                         refclk = 100;
 638
 639                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 640                     LVDS_CLKB_POWER_UP) {
 641                         /* LVDS dual channel */
 642                         if (refclk == 100)
 643                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 644                         else
 645                                 limit = &intel_limits_ironlake_dual_lvds;
 646                 } else {
 647                         if (refclk == 100)
 648                                 limit = &intel_limits_ironlake_single_lvds_100m;
 649                         else
 650                                 limit = &intel_limits_ironlake_single_lvds;
 651                 }
 652         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 653                         HAS_eDP)
 654                 limit = &intel_limits_ironlake_display_port;
 655         else
 656                 limit = &intel_limits_ironlake_dac;
 657
 658         return limit;
 659 }
 660
 661 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 662 {
 663         struct drm_device *dev = crtc->dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         const intel_limit_t *limit;
 666
 667         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 668                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 669                     LVDS_CLKB_POWER_UP)
 670                         /* LVDS with dual channel */
 671                         limit = &intel_limits_g4x_dual_channel_lvds;
 672                 else
 673                         /* LVDS with dual channel */
 674                         limit = &intel_limits_g4x_single_channel_lvds;
 675         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 676                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 677                 limit = &intel_limits_g4x_hdmi;
 678         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 679                 limit = &intel_limits_g4x_sdvo;
 680         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 681                 limit = &intel_limits_g4x_display_port;
 682         } else /* The option is for other outputs */
 683                 limit = &intel_limits_i9xx_sdvo;
 684
 685         return limit;
 686 }
 687
 688 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         const intel_limit_t *limit;
 692
 693         if (HAS_PCH_SPLIT(dev))
 694                 limit = intel_ironlake_limit(crtc);
 695         else if (IS_G4X(dev)) {
 696                 limit = intel_g4x_limit(crtc);
 697         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 698                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 699                         limit = &intel_limits_i9xx_lvds;
 700                 else
 701                         limit = &intel_limits_i9xx_sdvo;
 702         } else if (IS_PINEVIEW(dev)) {
 703                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 704                         limit = &intel_limits_pineview_lvds;
 705                 else
 706                         limit = &intel_limits_pineview_sdvo;
 707         } else {
 708                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 709                         limit = &intel_limits_i8xx_lvds;
 710                 else
 711                         limit = &intel_limits_i8xx_dvo;
 712         }
 713         return limit;
 714 }
 715
 716 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 717 static void pineview_clock(int refclk, intel_clock_t *clock)
 718 {
 719         clock->m = clock->m2 + 2;
 720         clock->p = clock->p1 * clock->p2;
 721         clock->vco = refclk * clock->m / clock->n;
 722         clock->dot = clock->vco / clock->p;
 723 }
 724
 725 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 726 {
 727         if (IS_PINEVIEW(dev)) {
 728                 pineview_clock(refclk, clock);
 729                 return;
 730         }
 731         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 732         clock->p = clock->p1 * clock->p2;
 733         clock->vco = refclk * clock->m / (clock->n + 2);
 734         clock->dot = clock->vco / clock->p;
 735 }
 736
 737 /**
 738  * Returns whether any output on the specified pipe is of the specified type
 739  */
 740 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 741 {
 742     struct drm_device *dev = crtc->dev;
 743     struct drm_mode_config *mode_config = &dev->mode_config;
 744     struct drm_encoder *l_entry;
 745
 746     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 747             if (l_entry && l_entry->crtc == crtc) {
 748                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 749                     if (intel_encoder->type == type)
 750                             return true;
 751             }
 752     }
 753     return false;
 754 }
 755
 756 static struct drm_connector *
 757 intel_pipe_get_connector (struct drm_crtc *crtc)
 758 {
 759     struct drm_device *dev = crtc->dev;
 760     struct drm_mode_config *mode_config = &dev->mode_config;
 761     struct drm_connector *l_entry, *ret = NULL;
 762
 763     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 764             if (l_entry->encoder &&
 765                 l_entry->encoder->crtc == crtc) {
 766                     ret = l_entry;
 767                     break;
 768             }
 769     }
 770     return ret;
 771 }
 772
 773 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 774 /**
 775  * Returns whether the given set of divisors are valid for a given refclk with
 776  * the given connectors.
 777  */
 778
 779 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 780 {
 781         const intel_limit_t *limit = intel_limit (crtc);
 782         struct drm_device *dev = crtc->dev;
 783
 784         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 785                 INTELPllInvalid ("p1 out of range\n");
 786         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 787                 INTELPllInvalid ("p out of range\n");
 788         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 789                 INTELPllInvalid ("m2 out of range\n");
 790         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 791                 INTELPllInvalid ("m1 out of range\n");
 792         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 793                 INTELPllInvalid ("m1 <= m2\n");
 794         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 795                 INTELPllInvalid ("m out of range\n");
 796         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 797                 INTELPllInvalid ("n out of range\n");
 798         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 799                 INTELPllInvalid ("vco out of range\n");
 800         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 801          * connector, etc., rather than just a single range.
 802          */
 803         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 804                 INTELPllInvalid ("dot out of range\n");
 805
 806         return true;
 807 }
 808
 809 static bool
 810 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 811                     int target, int refclk, intel_clock_t *best_clock)
 812
 813 {
 814         struct drm_device *dev = crtc->dev;
 815         struct drm_i915_private *dev_priv = dev->dev_private;
 816         intel_clock_t clock;
 817         int err = target;
 818
 819         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 820             (I915_READ(LVDS)) != 0) {
 821                 /*
 822                  * For LVDS, if the panel is on, just rely on its current
 823                  * settings for dual-channel.  We haven't figured out how to
 824                  * reliably set up different single/dual channel state, if we
 825                  * even can.
 826                  */
 827                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 828                     LVDS_CLKB_POWER_UP)
 829                         clock.p2 = limit->p2.p2_fast;
 830                 else
 831                         clock.p2 = limit->p2.p2_slow;
 832         } else {
 833                 if (target < limit->p2.dot_limit)
 834                         clock.p2 = limit->p2.p2_slow;
 835                 else
 836                         clock.p2 = limit->p2.p2_fast;
 837         }
 838
 839         memset (best_clock, 0, sizeof (*best_clock));
 840
 841         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 842              clock.m1++) {
 843                 for (clock.m2 = limit->m2.min;
 844                      clock.m2 <= limit->m2.max; clock.m2++) {
 845                         /* m1 is always 0 in Pineview */
 846                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 847                                 break;
 848                         for (clock.n = limit->n.min;
 849                              clock.n <= limit->n.max; clock.n++) {
 850                                 for (clock.p1 = limit->p1.min;
 851                                         clock.p1 <= limit->p1.max; clock.p1++) {
 852                                         int this_err;
 853
 854                                         intel_clock(dev, refclk, &clock);
 855
 856                                         if (!intel_PLL_is_valid(crtc, &clock))
 857                                                 continue;
 858
 859                                         this_err = abs(clock.dot - target);
 860                                         if (this_err < err) {
 861                                                 *best_clock = clock;
 862                                                 err = this_err;
 863                                         }
 864                                 }
 865                         }
 866                 }
 867         }
 868
 869         return (err != target);
 870 }
 871
 872 static bool
 873 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 874                         int target, int refclk, intel_clock_t *best_clock)
 875 {
 876         struct drm_device *dev = crtc->dev;
 877         struct drm_i915_private *dev_priv = dev->dev_private;
 878         intel_clock_t clock;
 879         int max_n;
 880         bool found;
 881         /* approximately equals target * 0.00488 */
 882         int err_most = (target >> 8) + (target >> 10);
 883         found = false;
 884
 885         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 886                 int lvds_reg;
 887
 888                 if (HAS_PCH_SPLIT(dev))
 889                         lvds_reg = PCH_LVDS;
 890                 else
 891                         lvds_reg = LVDS;
 892                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 893                     LVDS_CLKB_POWER_UP)
 894                         clock.p2 = limit->p2.p2_fast;
 895                 else
 896                         clock.p2 = limit->p2.p2_slow;
 897         } else {
 898                 if (target < limit->p2.dot_limit)
 899                         clock.p2 = limit->p2.p2_slow;
 900                 else
 901                         clock.p2 = limit->p2.p2_fast;
 902         }
 903
 904         memset(best_clock, 0, sizeof(*best_clock));
 905         max_n = limit->n.max;
 906         /* based on hardware requriment prefer smaller n to precision */
 907         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 908                 /* based on hardware requirment prefere larger m1,m2 */
 909                 for (clock.m1 = limit->m1.max;
 910                      clock.m1 >= limit->m1.min; clock.m1--) {
 911                         for (clock.m2 = limit->m2.max;
 912                              clock.m2 >= limit->m2.min; clock.m2--) {
 913                                 for (clock.p1 = limit->p1.max;
 914                                      clock.p1 >= limit->p1.min; clock.p1--) {
 915                                         int this_err;
 916
 917                                         intel_clock(dev, refclk, &clock);
 918                                         if (!intel_PLL_is_valid(crtc, &clock))
 919                                                 continue;
 920                                         this_err = abs(clock.dot - target) ;
 921                                         if (this_err < err_most) {
 922                                                 *best_clock = clock;
 923                                                 err_most = this_err;
 924                                                 max_n = clock.n;
 925                                                 found = true;
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         return found;
 932 }
 933
 934 static bool
 935 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 936                            int target, int refclk, intel_clock_t *best_clock)
 937 {
 938         struct drm_device *dev = crtc->dev;
 939         intel_clock_t clock;
 940
 941         /* return directly when it is eDP */
 942         if (HAS_eDP)
 943                 return true;
 944
 945         if (target < 200000) {
 946                 clock.n = 1;
 947                 clock.p1 = 2;
 948                 clock.p2 = 10;
 949                 clock.m1 = 12;
 950                 clock.m2 = 9;
 951         } else {
 952                 clock.n = 2;
 953                 clock.p1 = 1;
 954                 clock.p2 = 10;
 955                 clock.m1 = 14;
 956                 clock.m2 = 8;
 957         }
 958         intel_clock(dev, refclk, &clock);
 959         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 960         return true;
 961 }
 962
 963 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 964 static bool
 965 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 966                       int target, int refclk, intel_clock_t *best_clock)
 967 {
 968     intel_clock_t clock;
 969     if (target < 200000) {
 970         clock.p1 = 2;
 971         clock.p2 = 10;
 972         clock.n = 2;
 973         clock.m1 = 23;
 974         clock.m2 = 8;
 975     } else {
 976         clock.p1 = 1;
 977         clock.p2 = 10;
 978         clock.n = 1;
 979         clock.m1 = 14;
 980         clock.m2 = 2;
 981     }
 982     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 983     clock.p = (clock.p1 * clock.p2);
 984     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 985     clock.vco = 0;
 986     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 987     return true;
 988 }
 989
 990 void
 991 intel_wait_for_vblank(struct drm_device *dev)
 992 {
 993         /* Wait for 20ms, i.e. one cycle at 50hz. */
 994         msleep(20);
 995 }
 996
 997 /* Parameters have changed, update FBC info */
 998 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 999 {
1000         struct drm_device *dev = crtc->dev;
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002         struct drm_framebuffer *fb = crtc->fb;
1003         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1004         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1006         int plane, i;
1007         u32 fbc_ctl, fbc_ctl2;
1008
1009         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1010
1011         if (fb->pitch < dev_priv->cfb_pitch)
1012                 dev_priv->cfb_pitch = fb->pitch;
1013
1014         /* FBC_CTL wants 64B units */
1015         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1016         dev_priv->cfb_fence = obj_priv->fence_reg;
1017         dev_priv->cfb_plane = intel_crtc->plane;
1018         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1019
1020         /* Clear old tags */
1021         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1022                 I915_WRITE(FBC_TAG + (i * 4), 0);
1023
1024         /* Set it up... */
1025         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1026         if (obj_priv->tiling_mode != I915_TILING_NONE)
1027                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1028         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1029         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1030
1031         /* enable it... */
1032         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1033         if (IS_I945GM(dev))
1034                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1035         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1036         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1037         if (obj_priv->tiling_mode != I915_TILING_NONE)
1038                 fbc_ctl |= dev_priv->cfb_fence;
1039         I915_WRITE(FBC_CONTROL, fbc_ctl);
1040
1041         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1042                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1043 }
1044
1045 void i8xx_disable_fbc(struct drm_device *dev)
1046 {
1047         struct drm_i915_private *dev_priv = dev->dev_private;
1048         u32 fbc_ctl;
1049
1050         if (!I915_HAS_FBC(dev))
1051                 return;
1052
1053         /* Disable compression */
1054         fbc_ctl = I915_READ(FBC_CONTROL);
1055         fbc_ctl &= ~FBC_CTL_EN;
1056         I915_WRITE(FBC_CONTROL, fbc_ctl);
1057
1058         /* Wait for compressing bit to clear */
1059         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1060                 ; /* nothing */
1061
1062         intel_wait_for_vblank(dev);
1063
1064         DRM_DEBUG_KMS("disabled FBC\n");
1065 }
1066
1067 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1068 {
1069         struct drm_device *dev = crtc->dev;
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071
1072         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1073 }
1074
1075 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1076 {
1077         struct drm_device *dev = crtc->dev;
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079         struct drm_framebuffer *fb = crtc->fb;
1080         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1081         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1083         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1084                      DPFC_CTL_PLANEB);
1085         unsigned long stall_watermark = 200;
1086         u32 dpfc_ctl;
1087
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj_priv->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091
1092         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1093         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1094                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1095                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1096         } else {
1097                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1098         }
1099
1100         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1101         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1102                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1103                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1104         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1105
1106         /* enable it... */
1107         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1108
1109         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1110 }
1111
1112 void g4x_disable_fbc(struct drm_device *dev)
1113 {
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         u32 dpfc_ctl;
1116
1117         /* Disable compression */
1118         dpfc_ctl = I915_READ(DPFC_CONTROL);
1119         dpfc_ctl &= ~DPFC_CTL_EN;
1120         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1121         intel_wait_for_vblank(dev);
1122
1123         DRM_DEBUG_KMS("disabled FBC\n");
1124 }
1125
1126 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1127 {
1128         struct drm_device *dev = crtc->dev;
1129         struct drm_i915_private *dev_priv = dev->dev_private;
1130
1131         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1132 }
1133
1134 /**
1135  * intel_update_fbc - enable/disable FBC as needed
1136  * @crtc: CRTC to point the compressor at
1137  * @mode: mode in use
1138  *
1139  * Set up the framebuffer compression hardware at mode set time.  We
1140  * enable it if possible:
1141  *   - plane A only (on pre-965)
1142  *   - no pixel mulitply/line duplication
1143  *   - no alpha buffer discard
1144  *   - no dual wide
1145  *   - framebuffer <= 2048 in width, 1536 in height
1146  *
1147  * We can't assume that any compression will take place (worst case),
1148  * so the compressed buffer has to be the same size as the uncompressed
1149  * one.  It also must reside (along with the line length buffer) in
1150  * stolen memory.
1151  *
1152  * We need to enable/disable FBC on a global basis.
1153  */
1154 static void intel_update_fbc(struct drm_crtc *crtc,
1155                              struct drm_display_mode *mode)
1156 {
1157         struct drm_device *dev = crtc->dev;
1158         struct drm_i915_private *dev_priv = dev->dev_private;
1159         struct drm_framebuffer *fb = crtc->fb;
1160         struct intel_framebuffer *intel_fb;
1161         struct drm_i915_gem_object *obj_priv;
1162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1163         int plane = intel_crtc->plane;
1164
1165         if (!i915_powersave)
1166                 return;
1167
1168         if (!dev_priv->display.fbc_enabled ||
1169             !dev_priv->display.enable_fbc ||
1170             !dev_priv->display.disable_fbc)
1171                 return;
1172
1173         if (!crtc->fb)
1174                 return;
1175
1176         intel_fb = to_intel_framebuffer(fb);
1177         obj_priv = to_intel_bo(intel_fb->obj);
1178
1179         /*
1180          * If FBC is already on, we just have to verify that we can
1181          * keep it that way...
1182          * Need to disable if:
1183          *   - changing FBC params (stride, fence, mode)
1184          *   - new fb is too large to fit in compressed buffer
1185          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1186          */
1187         if (intel_fb->obj->size > dev_priv->cfb_size) {
1188                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1189                                 "compression\n");
1190                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1191                 goto out_disable;
1192         }
1193         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1194             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1195                 DRM_DEBUG_KMS("mode incompatible with compression, "
1196                                 "disabling\n");
1197                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1198                 goto out_disable;
1199         }
1200         if ((mode->hdisplay > 2048) ||
1201             (mode->vdisplay > 1536)) {
1202                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1203                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1204                 goto out_disable;
1205         }
1206         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1207                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1208                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1209                 goto out_disable;
1210         }
1211         if (obj_priv->tiling_mode != I915_TILING_X) {
1212                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1213                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1214                 goto out_disable;
1215         }
1216
1217         if (dev_priv->display.fbc_enabled(crtc)) {
1218                 /* We can re-enable it in this case, but need to update pitch */
1219                 if (fb->pitch > dev_priv->cfb_pitch)
1220                         dev_priv->display.disable_fbc(dev);
1221                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1222                         dev_priv->display.disable_fbc(dev);
1223                 if (plane != dev_priv->cfb_plane)
1224                         dev_priv->display.disable_fbc(dev);
1225         }
1226
1227         if (!dev_priv->display.fbc_enabled(crtc)) {
1228                 /* Now try to turn it back on if possible */
1229                 dev_priv->display.enable_fbc(crtc, 500);
1230         }
1231
1232         return;
1233
1234 out_disable:
1235         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1236         /* Multiple disables should be harmless */
1237         if (dev_priv->display.fbc_enabled(crtc))
1238                 dev_priv->display.disable_fbc(dev);
1239 }
1240
1241 static int
1242 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1243 {
1244         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1245         u32 alignment;
1246         int ret;
1247
1248         switch (obj_priv->tiling_mode) {
1249         case I915_TILING_NONE:
1250                 alignment = 64 * 1024;
1251                 break;
1252         case I915_TILING_X:
1253                 /* pin() will align the object as required by fence */
1254                 alignment = 0;
1255                 break;
1256         case I915_TILING_Y:
1257                 /* FIXME: Is this true? */
1258                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1259                 return -EINVAL;
1260         default:
1261                 BUG();
1262         }
1263
1264         ret = i915_gem_object_pin(obj, alignment);
1265         if (ret != 0)
1266                 return ret;
1267
1268         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1269          * fence, whereas 965+ only requires a fence if using
1270          * framebuffer compression.  For simplicity, we always install
1271          * a fence as the cost is not that onerous.
1272          */
1273         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1274             obj_priv->tiling_mode != I915_TILING_NONE) {
1275                 ret = i915_gem_object_get_fence_reg(obj);
1276                 if (ret != 0) {
1277                         i915_gem_object_unpin(obj);
1278                         return ret;
1279                 }
1280         }
1281
1282         return 0;
1283 }
1284
1285 static int
1286 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1287                     struct drm_framebuffer *old_fb)
1288 {
1289         struct drm_device *dev = crtc->dev;
1290         struct drm_i915_private *dev_priv = dev->dev_private;
1291         struct drm_i915_master_private *master_priv;
1292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1293         struct intel_framebuffer *intel_fb;
1294         struct drm_i915_gem_object *obj_priv;
1295         struct drm_gem_object *obj;
1296         int pipe = intel_crtc->pipe;
1297         int plane = intel_crtc->plane;
1298         unsigned long Start, Offset;
1299         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1300         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1301         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1302         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1303         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1304         u32 dspcntr;
1305         int ret;
1306
1307         /* no fb bound */
1308         if (!crtc->fb) {
1309                 DRM_DEBUG_KMS("No FB bound\n");
1310                 return 0;
1311         }
1312
1313         switch (plane) {
1314         case 0:
1315         case 1:
1316                 break;
1317         default:
1318                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1319                 return -EINVAL;
1320         }
1321
1322         intel_fb = to_intel_framebuffer(crtc->fb);
1323         obj = intel_fb->obj;
1324         obj_priv = to_intel_bo(obj);
1325
1326         mutex_lock(&dev->struct_mutex);
1327         ret = intel_pin_and_fence_fb_obj(dev, obj);
1328         if (ret != 0) {
1329                 mutex_unlock(&dev->struct_mutex);
1330                 return ret;
1331         }
1332
1333         ret = i915_gem_object_set_to_display_plane(obj);
1334         if (ret != 0) {
1335                 i915_gem_object_unpin(obj);
1336                 mutex_unlock(&dev->struct_mutex);
1337                 return ret;
1338         }
1339
1340         dspcntr = I915_READ(dspcntr_reg);
1341         /* Mask out pixel format bits in case we change it */
1342         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1343         switch (crtc->fb->bits_per_pixel) {
1344         case 8:
1345                 dspcntr |= DISPPLANE_8BPP;
1346                 break;
1347         case 16:
1348                 if (crtc->fb->depth == 15)
1349                         dspcntr |= DISPPLANE_15_16BPP;
1350                 else
1351                         dspcntr |= DISPPLANE_16BPP;
1352                 break;
1353         case 24:
1354         case 32:
1355                 if (crtc->fb->depth == 30)
1356                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1357                 else
1358                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1359                 break;
1360         default:
1361                 DRM_ERROR("Unknown color depth\n");
1362                 i915_gem_object_unpin(obj);
1363                 mutex_unlock(&dev->struct_mutex);
1364                 return -EINVAL;
1365         }
1366         if (IS_I965G(dev)) {
1367                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1368                         dspcntr |= DISPPLANE_TILED;
1369                 else
1370                         dspcntr &= ~DISPPLANE_TILED;
1371         }
1372
1373         if (HAS_PCH_SPLIT(dev))
1374                 /* must disable */
1375                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1376
1377         I915_WRITE(dspcntr_reg, dspcntr);
1378
1379         Start = obj_priv->gtt_offset;
1380         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1381
1382         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1383         I915_WRITE(dspstride, crtc->fb->pitch);
1384         if (IS_I965G(dev)) {
1385                 I915_WRITE(dspbase, Offset);
1386                 I915_READ(dspbase);
1387                 I915_WRITE(dspsurf, Start);
1388                 I915_READ(dspsurf);
1389                 I915_WRITE(dsptileoff, (y << 16) | x);
1390         } else {
1391                 I915_WRITE(dspbase, Start + Offset);
1392                 I915_READ(dspbase);
1393         }
1394
1395         if ((IS_I965G(dev) || plane == 0))
1396                 intel_update_fbc(crtc, &crtc->mode);
1397
1398         intel_wait_for_vblank(dev);
1399
1400         if (old_fb) {
1401                 intel_fb = to_intel_framebuffer(old_fb);
1402                 obj_priv = to_intel_bo(intel_fb->obj);
1403                 i915_gem_object_unpin(intel_fb->obj);
1404         }
1405         intel_increase_pllclock(crtc, true);
1406
1407         mutex_unlock(&dev->struct_mutex);
1408
1409         if (!dev->primary->master)
1410                 return 0;
1411
1412         master_priv = dev->primary->master->driver_priv;
1413         if (!master_priv->sarea_priv)
1414                 return 0;
1415
1416         if (pipe) {
1417                 master_priv->sarea_priv->pipeB_x = x;
1418                 master_priv->sarea_priv->pipeB_y = y;
1419         } else {
1420                 master_priv->sarea_priv->pipeA_x = x;
1421                 master_priv->sarea_priv->pipeA_y = y;
1422         }
1423
1424         return 0;
1425 }
1426
1427 /* Disable the VGA plane that we never use */
1428 static void i915_disable_vga (struct drm_device *dev)
1429 {
1430         struct drm_i915_private *dev_priv = dev->dev_private;
1431         u8 sr1;
1432         u32 vga_reg;
1433
1434         if (HAS_PCH_SPLIT(dev))
1435                 vga_reg = CPU_VGACNTRL;
1436         else
1437                 vga_reg = VGACNTRL;
1438
1439         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1440                 return;
1441
1442         I915_WRITE8(VGA_SR_INDEX, 1);
1443         sr1 = I915_READ8(VGA_SR_DATA);
1444         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1445         udelay(100);
1446
1447         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1448 }
1449
1450 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1451 {
1452         struct drm_device *dev = crtc->dev;
1453         struct drm_i915_private *dev_priv = dev->dev_private;
1454         u32 dpa_ctl;
1455
1456         DRM_DEBUG_KMS("\n");
1457         dpa_ctl = I915_READ(DP_A);
1458         dpa_ctl &= ~DP_PLL_ENABLE;
1459         I915_WRITE(DP_A, dpa_ctl);
1460 }
1461
1462 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1463 {
1464         struct drm_device *dev = crtc->dev;
1465         struct drm_i915_private *dev_priv = dev->dev_private;
1466         u32 dpa_ctl;
1467
1468         dpa_ctl = I915_READ(DP_A);
1469         dpa_ctl |= DP_PLL_ENABLE;
1470         I915_WRITE(DP_A, dpa_ctl);
1471         udelay(200);
1472 }
1473
1474
1475 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1476 {
1477         struct drm_device *dev = crtc->dev;
1478         struct drm_i915_private *dev_priv = dev->dev_private;
1479         u32 dpa_ctl;
1480
1481         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1482         dpa_ctl = I915_READ(DP_A);
1483         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1484
1485         if (clock < 200000) {
1486                 u32 temp;
1487                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1488                 /* workaround for 160Mhz:
1489                    1) program 0x4600c bits 15:0 = 0x8124
1490                    2) program 0x46010 bit 0 = 1
1491                    3) program 0x46034 bit 24 = 1
1492                    4) program 0x64000 bit 14 = 1
1493                    */
1494                 temp = I915_READ(0x4600c);
1495                 temp &= 0xffff0000;
1496                 I915_WRITE(0x4600c, temp | 0x8124);
1497
1498                 temp = I915_READ(0x46010);
1499                 I915_WRITE(0x46010, temp | 1);
1500
1501                 temp = I915_READ(0x46034);
1502                 I915_WRITE(0x46034, temp | (1 << 24));
1503         } else {
1504                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1505         }
1506         I915_WRITE(DP_A, dpa_ctl);
1507
1508         udelay(500);
1509 }
1510
1511 /* The FDI link training functions for ILK/Ibexpeak. */
1512 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1513 {
1514         struct drm_device *dev = crtc->dev;
1515         struct drm_i915_private *dev_priv = dev->dev_private;
1516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1517         int pipe = intel_crtc->pipe;
1518         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1519         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1520         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1521         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1522         u32 temp, tries = 0;
1523
1524         /* enable CPU FDI TX and PCH FDI RX */
1525         temp = I915_READ(fdi_tx_reg);
1526         temp |= FDI_TX_ENABLE;
1527         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1528         temp &= ~FDI_LINK_TRAIN_NONE;
1529         temp |= FDI_LINK_TRAIN_PATTERN_1;
1530         I915_WRITE(fdi_tx_reg, temp);
1531         I915_READ(fdi_tx_reg);
1532
1533         temp = I915_READ(fdi_rx_reg);
1534         temp &= ~FDI_LINK_TRAIN_NONE;
1535         temp |= FDI_LINK_TRAIN_PATTERN_1;
1536         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1537         I915_READ(fdi_rx_reg);
1538         udelay(150);
1539
1540         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1541            for train result */
1542         temp = I915_READ(fdi_rx_imr_reg);
1543         temp &= ~FDI_RX_SYMBOL_LOCK;
1544         temp &= ~FDI_RX_BIT_LOCK;
1545         I915_WRITE(fdi_rx_imr_reg, temp);
1546         I915_READ(fdi_rx_imr_reg);
1547         udelay(150);
1548
1549         for (;;) {
1550                 temp = I915_READ(fdi_rx_iir_reg);
1551                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1552
1553                 if ((temp & FDI_RX_BIT_LOCK)) {
1554                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1555                         I915_WRITE(fdi_rx_iir_reg,
1556                                    temp | FDI_RX_BIT_LOCK);
1557                         break;
1558                 }
1559
1560                 tries++;
1561
1562                 if (tries > 5) {
1563                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1564                         break;
1565                 }
1566         }
1567
1568         /* Train 2 */
1569         temp = I915_READ(fdi_tx_reg);
1570         temp &= ~FDI_LINK_TRAIN_NONE;
1571         temp |= FDI_LINK_TRAIN_PATTERN_2;
1572         I915_WRITE(fdi_tx_reg, temp);
1573
1574         temp = I915_READ(fdi_rx_reg);
1575         temp &= ~FDI_LINK_TRAIN_NONE;
1576         temp |= FDI_LINK_TRAIN_PATTERN_2;
1577         I915_WRITE(fdi_rx_reg, temp);
1578         udelay(150);
1579
1580         tries = 0;
1581
1582         for (;;) {
1583                 temp = I915_READ(fdi_rx_iir_reg);
1584                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1585
1586                 if (temp & FDI_RX_SYMBOL_LOCK) {
1587                         I915_WRITE(fdi_rx_iir_reg,
1588                                    temp | FDI_RX_SYMBOL_LOCK);
1589                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1590                         break;
1591                 }
1592
1593                 tries++;
1594
1595                 if (tries > 5) {
1596                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1597                         break;
1598                 }
1599         }
1600
1601         DRM_DEBUG_KMS("FDI train done\n");
1602 }
1603
1604 static int snb_b_fdi_train_param [] = {
1605         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1606         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1607         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1608         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1609 };
1610
1611 /* The FDI link training functions for SNB/Cougarpoint. */
1612 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1613 {
1614         struct drm_device *dev = crtc->dev;
1615         struct drm_i915_private *dev_priv = dev->dev_private;
1616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1617         int pipe = intel_crtc->pipe;
1618         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1619         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1620         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1621         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1622         u32 temp, i;
1623
1624         /* enable CPU FDI TX and PCH FDI RX */
1625         temp = I915_READ(fdi_tx_reg);
1626         temp |= FDI_TX_ENABLE;
1627         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1628         temp &= ~FDI_LINK_TRAIN_NONE;
1629         temp |= FDI_LINK_TRAIN_PATTERN_1;
1630         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1631         /* SNB-B */
1632         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1633         I915_WRITE(fdi_tx_reg, temp);
1634         I915_READ(fdi_tx_reg);
1635
1636         temp = I915_READ(fdi_rx_reg);
1637         if (HAS_PCH_CPT(dev)) {
1638                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1639                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1640         } else {
1641                 temp &= ~FDI_LINK_TRAIN_NONE;
1642                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1643         }
1644         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1645         I915_READ(fdi_rx_reg);
1646         udelay(150);
1647
1648         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1649            for train result */
1650         temp = I915_READ(fdi_rx_imr_reg);
1651         temp &= ~FDI_RX_SYMBOL_LOCK;
1652         temp &= ~FDI_RX_BIT_LOCK;
1653         I915_WRITE(fdi_rx_imr_reg, temp);
1654         I915_READ(fdi_rx_imr_reg);
1655         udelay(150);
1656
1657         for (i = 0; i < 4; i++ ) {
1658                 temp = I915_READ(fdi_tx_reg);
1659                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1660                 temp |= snb_b_fdi_train_param[i];
1661                 I915_WRITE(fdi_tx_reg, temp);
1662                 udelay(500);
1663
1664                 temp = I915_READ(fdi_rx_iir_reg);
1665                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1666
1667                 if (temp & FDI_RX_BIT_LOCK) {
1668                         I915_WRITE(fdi_rx_iir_reg,
1669                                    temp | FDI_RX_BIT_LOCK);
1670                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1671                         break;
1672                 }
1673         }
1674         if (i == 4)
1675                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1676
1677         /* Train 2 */
1678         temp = I915_READ(fdi_tx_reg);
1679         temp &= ~FDI_LINK_TRAIN_NONE;
1680         temp |= FDI_LINK_TRAIN_PATTERN_2;
1681         if (IS_GEN6(dev)) {
1682                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1683                 /* SNB-B */
1684                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1685         }
1686         I915_WRITE(fdi_tx_reg, temp);
1687
1688         temp = I915_READ(fdi_rx_reg);
1689         if (HAS_PCH_CPT(dev)) {
1690                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1691                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1692         } else {
1693                 temp &= ~FDI_LINK_TRAIN_NONE;
1694                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1695         }
1696         I915_WRITE(fdi_rx_reg, temp);
1697         udelay(150);
1698
1699         for (i = 0; i < 4; i++ ) {
1700                 temp = I915_READ(fdi_tx_reg);
1701                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1702                 temp |= snb_b_fdi_train_param[i];
1703                 I915_WRITE(fdi_tx_reg, temp);
1704                 udelay(500);
1705
1706                 temp = I915_READ(fdi_rx_iir_reg);
1707                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1708
1709                 if (temp & FDI_RX_SYMBOL_LOCK) {
1710                         I915_WRITE(fdi_rx_iir_reg,
1711                                    temp | FDI_RX_SYMBOL_LOCK);
1712                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1713                         break;
1714                 }
1715         }
1716         if (i == 4)
1717                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1718
1719         DRM_DEBUG_KMS("FDI train done.\n");
1720 }
1721
1722 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1723 {
1724         struct drm_device *dev = crtc->dev;
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1727         int pipe = intel_crtc->pipe;
1728         int plane = intel_crtc->plane;
1729         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1730         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1731         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1732         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1733         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1734         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1735         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1736         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1737         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1738         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1739         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1740         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1741         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1742         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1743         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1744         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1745         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1746         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1747         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1748         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1749         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1750         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1751         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1752         u32 temp;
1753         int n;
1754         u32 pipe_bpc;
1755
1756         temp = I915_READ(pipeconf_reg);
1757         pipe_bpc = temp & PIPE_BPC_MASK;
1758
1759         /* XXX: When our outputs are all unaware of DPMS modes other than off
1760          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1761          */
1762         switch (mode) {
1763         case DRM_MODE_DPMS_ON:
1764         case DRM_MODE_DPMS_STANDBY:
1765         case DRM_MODE_DPMS_SUSPEND:
1766                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1767
1768                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1769                         temp = I915_READ(PCH_LVDS);
1770                         if ((temp & LVDS_PORT_EN) == 0) {
1771                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1772                                 POSTING_READ(PCH_LVDS);
1773                         }
1774                 }
1775
1776                 if (HAS_eDP) {
1777                         /* enable eDP PLL */
1778                         ironlake_enable_pll_edp(crtc);
1779                 } else {
1780
1781                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1782                         temp = I915_READ(fdi_rx_reg);
1783                         /*
1784                          * make the BPC in FDI Rx be consistent with that in
1785                          * pipeconf reg.
1786                          */
1787                         temp &= ~(0x7 << 16);
1788                         temp |= (pipe_bpc << 11);
1789                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1790                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1791                         I915_READ(fdi_rx_reg);
1792                         udelay(200);
1793
1794                         /* Switch from Rawclk to PCDclk */
1795                         temp = I915_READ(fdi_rx_reg);
1796                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1797                         I915_READ(fdi_rx_reg);
1798                         udelay(200);
1799
1800                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1801                         temp = I915_READ(fdi_tx_reg);
1802                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1803                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1804                                 I915_READ(fdi_tx_reg);
1805                                 udelay(100);
1806                         }
1807                 }
1808
1809                 /* Enable panel fitting for LVDS */
1810                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1811                         temp = I915_READ(pf_ctl_reg);
1812                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1813
1814                         /* currently full aspect */
1815                         I915_WRITE(pf_win_pos, 0);
1816
1817                         I915_WRITE(pf_win_size,
1818                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1819                                    (dev_priv->panel_fixed_mode->vdisplay));
1820                 }
1821
1822                 /* Enable CPU pipe */
1823                 temp = I915_READ(pipeconf_reg);
1824                 if ((temp & PIPEACONF_ENABLE) == 0) {
1825                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1826                         I915_READ(pipeconf_reg);
1827                         udelay(100);
1828                 }
1829
1830                 /* configure and enable CPU plane */
1831                 temp = I915_READ(dspcntr_reg);
1832                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1833                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1834                         /* Flush the plane changes */
1835                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1836                 }
1837
1838                 if (!HAS_eDP) {
1839                         /* For PCH output, training FDI link */
1840                         if (IS_GEN6(dev))
1841                                 gen6_fdi_link_train(crtc);
1842                         else
1843                                 ironlake_fdi_link_train(crtc);
1844
1845                         /* enable PCH DPLL */
1846                         temp = I915_READ(pch_dpll_reg);
1847                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1848                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1849                                 I915_READ(pch_dpll_reg);
1850                         }
1851                         udelay(200);
1852
1853                         if (HAS_PCH_CPT(dev)) {
1854                                 /* Be sure PCH DPLL SEL is set */
1855                                 temp = I915_READ(PCH_DPLL_SEL);
1856                                 if (trans_dpll_sel == 0 &&
1857                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1858                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1859                                 else if (trans_dpll_sel == 1 &&
1860                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1861                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1862                                 I915_WRITE(PCH_DPLL_SEL, temp);
1863                                 I915_READ(PCH_DPLL_SEL);
1864                         }
1865
1866                         /* set transcoder timing */
1867                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1868                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1869                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1870
1871                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1872                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1873                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1874
1875                         /* enable normal train */
1876                         temp = I915_READ(fdi_tx_reg);
1877                         temp &= ~FDI_LINK_TRAIN_NONE;
1878                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1879                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1880                         I915_READ(fdi_tx_reg);
1881
1882                         temp = I915_READ(fdi_rx_reg);
1883                         if (HAS_PCH_CPT(dev)) {
1884                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1885                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1886                         } else {
1887                                 temp &= ~FDI_LINK_TRAIN_NONE;
1888                                 temp |= FDI_LINK_TRAIN_NONE;
1889                         }
1890                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1891                         I915_READ(fdi_rx_reg);
1892
1893                         /* wait one idle pattern time */
1894                         udelay(100);
1895
1896                         /* For PCH DP, enable TRANS_DP_CTL */
1897                         if (HAS_PCH_CPT(dev) &&
1898                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1899                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1900                                 int reg;
1901
1902                                 reg = I915_READ(trans_dp_ctl);
1903                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
1904                                 reg = TRANS_DP_OUTPUT_ENABLE |
1905                                       TRANS_DP_ENH_FRAMING |
1906                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
1907                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
1908
1909                                 switch (intel_trans_dp_port_sel(crtc)) {
1910                                 case PCH_DP_B:
1911                                         reg |= TRANS_DP_PORT_SEL_B;
1912                                         break;
1913                                 case PCH_DP_C:
1914                                         reg |= TRANS_DP_PORT_SEL_C;
1915                                         break;
1916                                 case PCH_DP_D:
1917                                         reg |= TRANS_DP_PORT_SEL_D;
1918                                         break;
1919                                 default:
1920                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1921                                         reg |= TRANS_DP_PORT_SEL_B;
1922                                         break;
1923                                 }
1924
1925                                 I915_WRITE(trans_dp_ctl, reg);
1926                                 POSTING_READ(trans_dp_ctl);
1927                         }
1928
1929                         /* enable PCH transcoder */
1930                         temp = I915_READ(transconf_reg);
1931                         /*
1932                          * make the BPC in transcoder be consistent with
1933                          * that in pipeconf reg.
1934                          */
1935                         temp &= ~PIPE_BPC_MASK;
1936                         temp |= pipe_bpc;
1937                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1938                         I915_READ(transconf_reg);
1939
1940                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1941                                 ;
1942
1943                 }
1944
1945                 intel_crtc_load_lut(crtc);
1946
1947         break;
1948         case DRM_MODE_DPMS_OFF:
1949                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1950
1951                 drm_vblank_off(dev, pipe);
1952                 /* Disable display plane */
1953                 temp = I915_READ(dspcntr_reg);
1954                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1955                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1956                         /* Flush the plane changes */
1957                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1958                         I915_READ(dspbase_reg);
1959                 }
1960
1961                 i915_disable_vga(dev);
1962
1963                 /* disable cpu pipe, disable after all planes disabled */
1964                 temp = I915_READ(pipeconf_reg);
1965                 if ((temp & PIPEACONF_ENABLE) != 0) {
1966                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1967                         I915_READ(pipeconf_reg);
1968                         n = 0;
1969                         /* wait for cpu pipe off, pipe state */
1970                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1971                                 n++;
1972                                 if (n < 60) {
1973                                         udelay(500);
1974                                         continue;
1975                                 } else {
1976                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1977                                                                 pipe);
1978                                         break;
1979                                 }
1980                         }
1981                 } else
1982                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1983
1984                 udelay(100);
1985
1986                 /* Disable PF */
1987                 temp = I915_READ(pf_ctl_reg);
1988                 if ((temp & PF_ENABLE) != 0) {
1989                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1990                         I915_READ(pf_ctl_reg);
1991                 }
1992                 I915_WRITE(pf_win_size, 0);
1993                 POSTING_READ(pf_win_size);
1994
1995
1996                 /* disable CPU FDI tx and PCH FDI rx */
1997                 temp = I915_READ(fdi_tx_reg);
1998                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1999                 I915_READ(fdi_tx_reg);
2000
2001                 temp = I915_READ(fdi_rx_reg);
2002                 /* BPC in FDI rx is consistent with that in pipeconf */
2003                 temp &= ~(0x07 << 16);
2004                 temp |= (pipe_bpc << 11);
2005                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2006                 I915_READ(fdi_rx_reg);
2007
2008                 udelay(100);
2009
2010                 /* still set train pattern 1 */
2011                 temp = I915_READ(fdi_tx_reg);
2012                 temp &= ~FDI_LINK_TRAIN_NONE;
2013                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2014                 I915_WRITE(fdi_tx_reg, temp);
2015                 POSTING_READ(fdi_tx_reg);
2016
2017                 temp = I915_READ(fdi_rx_reg);
2018                 if (HAS_PCH_CPT(dev)) {
2019                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2020                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2021                 } else {
2022                         temp &= ~FDI_LINK_TRAIN_NONE;
2023                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2024                 }
2025                 I915_WRITE(fdi_rx_reg, temp);
2026                 POSTING_READ(fdi_rx_reg);
2027
2028                 udelay(100);
2029
2030                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2031                         temp = I915_READ(PCH_LVDS);
2032                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2033                         I915_READ(PCH_LVDS);
2034                         udelay(100);
2035                 }
2036
2037                 /* disable PCH transcoder */
2038                 temp = I915_READ(transconf_reg);
2039                 if ((temp & TRANS_ENABLE) != 0) {
2040                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2041                         I915_READ(transconf_reg);
2042                         n = 0;
2043                         /* wait for PCH transcoder off, transcoder state */
2044                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2045                                 n++;
2046                                 if (n < 60) {
2047                                         udelay(500);
2048                                         continue;
2049                                 } else {
2050                                         DRM_DEBUG_KMS("transcoder %d off "
2051                                                         "delay\n", pipe);
2052                                         break;
2053                                 }
2054                         }
2055                 }
2056
2057                 temp = I915_READ(transconf_reg);
2058                 /* BPC in transcoder is consistent with that in pipeconf */
2059                 temp &= ~PIPE_BPC_MASK;
2060                 temp |= pipe_bpc;
2061                 I915_WRITE(transconf_reg, temp);
2062                 I915_READ(transconf_reg);
2063                 udelay(100);
2064
2065                 if (HAS_PCH_CPT(dev)) {
2066                         /* disable TRANS_DP_CTL */
2067                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2068                         int reg;
2069
2070                         reg = I915_READ(trans_dp_ctl);
2071                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2072                         I915_WRITE(trans_dp_ctl, reg);
2073                         POSTING_READ(trans_dp_ctl);
2074
2075                         /* disable DPLL_SEL */
2076                         temp = I915_READ(PCH_DPLL_SEL);
2077                         if (trans_dpll_sel == 0)
2078                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2079                         else
2080                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2081                         I915_WRITE(PCH_DPLL_SEL, temp);
2082                         I915_READ(PCH_DPLL_SEL);
2083
2084                 }
2085
2086                 /* disable PCH DPLL */
2087                 temp = I915_READ(pch_dpll_reg);
2088                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2089                 I915_READ(pch_dpll_reg);
2090
2091                 if (HAS_eDP) {
2092                         ironlake_disable_pll_edp(crtc);
2093                 }
2094
2095                 /* Switch from PCDclk to Rawclk */
2096                 temp = I915_READ(fdi_rx_reg);
2097                 temp &= ~FDI_SEL_PCDCLK;
2098                 I915_WRITE(fdi_rx_reg, temp);
2099                 I915_READ(fdi_rx_reg);
2100
2101                 /* Disable CPU FDI TX PLL */
2102                 temp = I915_READ(fdi_tx_reg);
2103                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2104                 I915_READ(fdi_tx_reg);
2105                 udelay(100);
2106
2107                 temp = I915_READ(fdi_rx_reg);
2108                 temp &= ~FDI_RX_PLL_ENABLE;
2109                 I915_WRITE(fdi_rx_reg, temp);
2110                 I915_READ(fdi_rx_reg);
2111
2112                 /* Wait for the clocks to turn off. */
2113                 udelay(100);
2114                 break;
2115         }
2116 }
2117
2118 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2119 {
2120         struct intel_overlay *overlay;
2121         int ret;
2122
2123         if (!enable && intel_crtc->overlay) {
2124                 overlay = intel_crtc->overlay;
2125                 mutex_lock(&overlay->dev->struct_mutex);
2126                 for (;;) {
2127                         ret = intel_overlay_switch_off(overlay);
2128                         if (ret == 0)
2129                                 break;
2130
2131                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2132                         if (ret != 0) {
2133                                 /* overlay doesn't react anymore. Usually
2134                                  * results in a black screen and an unkillable
2135                                  * X server. */
2136                                 BUG();
2137                                 overlay->hw_wedged = HW_WEDGED;
2138                                 break;
2139                         }
2140                 }
2141                 mutex_unlock(&overlay->dev->struct_mutex);
2142         }
2143         /* Let userspace switch the overlay on again. In most cases userspace
2144          * has to recompute where to put it anyway. */
2145
2146         return;
2147 }
2148
2149 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2150 {
2151         struct drm_device *dev = crtc->dev;
2152         struct drm_i915_private *dev_priv = dev->dev_private;
2153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2154         int pipe = intel_crtc->pipe;
2155         int plane = intel_crtc->plane;
2156         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2157         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2158         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2159         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2160         u32 temp;
2161
2162         /* XXX: When our outputs are all unaware of DPMS modes other than off
2163          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2164          */
2165         switch (mode) {
2166         case DRM_MODE_DPMS_ON:
2167         case DRM_MODE_DPMS_STANDBY:
2168         case DRM_MODE_DPMS_SUSPEND:
2169                 intel_update_watermarks(dev);
2170
2171                 /* Enable the DPLL */
2172                 temp = I915_READ(dpll_reg);
2173                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2174                         I915_WRITE(dpll_reg, temp);
2175                         I915_READ(dpll_reg);
2176                         /* Wait for the clocks to stabilize. */
2177                         udelay(150);
2178                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2179                         I915_READ(dpll_reg);
2180                         /* Wait for the clocks to stabilize. */
2181                         udelay(150);
2182                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2183                         I915_READ(dpll_reg);
2184                         /* Wait for the clocks to stabilize. */
2185                         udelay(150);
2186                 }
2187
2188                 /* Enable the pipe */
2189                 temp = I915_READ(pipeconf_reg);
2190                 if ((temp & PIPEACONF_ENABLE) == 0)
2191                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2192
2193                 /* Enable the plane */
2194                 temp = I915_READ(dspcntr_reg);
2195                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2196                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2197                         /* Flush the plane changes */
2198                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2199                 }
2200
2201                 intel_crtc_load_lut(crtc);
2202
2203                 if ((IS_I965G(dev) || plane == 0))
2204                         intel_update_fbc(crtc, &crtc->mode);
2205
2206                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2207                 intel_crtc_dpms_overlay(intel_crtc, true);
2208         break;
2209         case DRM_MODE_DPMS_OFF:
2210                 intel_update_watermarks(dev);
2211
2212                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2213                 intel_crtc_dpms_overlay(intel_crtc, false);
2214                 drm_vblank_off(dev, pipe);
2215
2216                 if (dev_priv->cfb_plane == plane &&
2217                     dev_priv->display.disable_fbc)
2218                         dev_priv->display.disable_fbc(dev);
2219
2220                 /* Disable the VGA plane that we never use */
2221                 i915_disable_vga(dev);
2222
2223                 /* Disable display plane */
2224                 temp = I915_READ(dspcntr_reg);
2225                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2226                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2227                         /* Flush the plane changes */
2228                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2229                         I915_READ(dspbase_reg);
2230                 }
2231
2232                 if (!IS_I9XX(dev)) {
2233                         /* Wait for vblank for the disable to take effect */
2234                         intel_wait_for_vblank(dev);
2235                 }
2236
2237                 /* Next, disable display pipes */
2238                 temp = I915_READ(pipeconf_reg);
2239                 if ((temp & PIPEACONF_ENABLE) != 0) {
2240                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2241                         I915_READ(pipeconf_reg);
2242                 }
2243
2244                 /* Wait for vblank for the disable to take effect. */
2245                 intel_wait_for_vblank(dev);
2246
2247                 temp = I915_READ(dpll_reg);
2248                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2249                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2250                         I915_READ(dpll_reg);
2251                 }
2252
2253                 /* Wait for the clocks to turn off. */
2254                 udelay(150);
2255                 break;
2256         }
2257 }
2258
2259 /**
2260  * Sets the power management mode of the pipe and plane.
2261  *
2262  * This code should probably grow support for turning the cursor off and back
2263  * on appropriately at the same time as we're turning the pipe off/on.
2264  */
2265 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2266 {
2267         struct drm_device *dev = crtc->dev;
2268         struct drm_i915_private *dev_priv = dev->dev_private;
2269         struct drm_i915_master_private *master_priv;
2270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271         int pipe = intel_crtc->pipe;
2272         bool enabled;
2273
2274         dev_priv->display.dpms(crtc, mode);
2275
2276         intel_crtc->dpms_mode = mode;
2277
2278         if (!dev->primary->master)
2279                 return;
2280
2281         master_priv = dev->primary->master->driver_priv;
2282         if (!master_priv->sarea_priv)
2283                 return;
2284
2285         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2286
2287         switch (pipe) {
2288         case 0:
2289                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2290                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2291                 break;
2292         case 1:
2293                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2294                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2295                 break;
2296         default:
2297                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2298                 break;
2299         }
2300 }
2301
2302 static void intel_crtc_prepare (struct drm_crtc *crtc)
2303 {
2304         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2305         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2306 }
2307
2308 static void intel_crtc_commit (struct drm_crtc *crtc)
2309 {
2310         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2311         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2312 }
2313
2314 void intel_encoder_prepare (struct drm_encoder *encoder)
2315 {
2316         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2317         /* lvds has its own version of prepare see intel_lvds_prepare */
2318         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2319 }
2320
2321 void intel_encoder_commit (struct drm_encoder *encoder)
2322 {
2323         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2324         /* lvds has its own version of commit see intel_lvds_commit */
2325         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2326 }
2327
2328 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2329                                   struct drm_display_mode *mode,
2330                                   struct drm_display_mode *adjusted_mode)
2331 {
2332         struct drm_device *dev = crtc->dev;
2333         if (HAS_PCH_SPLIT(dev)) {
2334                 /* FDI link clock is fixed at 2.7G */
2335                 if (mode->clock * 3 > 27000 * 4)
2336                         return MODE_CLOCK_HIGH;
2337         }
2338         return true;
2339 }
2340
2341 static int i945_get_display_clock_speed(struct drm_device *dev)
2342 {
2343         return 400000;
2344 }
2345
2346 static int i915_get_display_clock_speed(struct drm_device *dev)
2347 {
2348         return 333000;
2349 }
2350
2351 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2352 {
2353         return 200000;
2354 }
2355
2356 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2357 {
2358         u16 gcfgc = 0;
2359
2360         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2361
2362         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2363                 return 133000;
2364         else {
2365                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2366                 case GC_DISPLAY_CLOCK_333_MHZ:
2367                         return 333000;
2368                 default:
2369                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2370                         return 190000;
2371                 }
2372         }
2373 }
2374
2375 static int i865_get_display_clock_speed(struct drm_device *dev)
2376 {
2377         return 266000;
2378 }
2379
2380 static int i855_get_display_clock_speed(struct drm_device *dev)
2381 {
2382         u16 hpllcc = 0;
2383         /* Assume that the hardware is in the high speed state.  This
2384          * should be the default.
2385          */
2386         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2387         case GC_CLOCK_133_200:
2388         case GC_CLOCK_100_200:
2389                 return 200000;
2390         case GC_CLOCK_166_250:
2391                 return 250000;
2392         case GC_CLOCK_100_133:
2393                 return 133000;
2394         }
2395
2396         /* Shouldn't happen */
2397         return 0;
2398 }
2399
2400 static int i830_get_display_clock_speed(struct drm_device *dev)
2401 {
2402         return 133000;
2403 }
2404
2405 /**
2406  * Return the pipe currently connected to the panel fitter,
2407  * or -1 if the panel fitter is not present or not in use
2408  */
2409 int intel_panel_fitter_pipe (struct drm_device *dev)
2410 {
2411         struct drm_i915_private *dev_priv = dev->dev_private;
2412         u32  pfit_control;
2413
2414         /* i830 doesn't have a panel fitter */
2415         if (IS_I830(dev))
2416                 return -1;
2417
2418         pfit_control = I915_READ(PFIT_CONTROL);
2419
2420         /* See if the panel fitter is in use */
2421         if ((pfit_control & PFIT_ENABLE) == 0)
2422                 return -1;
2423
2424         /* 965 can place panel fitter on either pipe */
2425         if (IS_I965G(dev))
2426                 return (pfit_control >> 29) & 0x3;
2427
2428         /* older chips can only use pipe 1 */
2429         return 1;
2430 }
2431
2432 struct fdi_m_n {
2433         u32        tu;
2434         u32        gmch_m;
2435         u32        gmch_n;
2436         u32        link_m;
2437         u32        link_n;
2438 };
2439
2440 static void
2441 fdi_reduce_ratio(u32 *num, u32 *den)
2442 {
2443         while (*num > 0xffffff || *den > 0xffffff) {
2444                 *num >>= 1;
2445                 *den >>= 1;
2446         }
2447 }
2448
2449 #define DATA_N 0x800000
2450 #define LINK_N 0x80000
2451
2452 static void
2453 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2454                      int link_clock, struct fdi_m_n *m_n)
2455 {
2456         u64 temp;
2457
2458         m_n->tu = 64; /* default size */
2459
2460         temp = (u64) DATA_N * pixel_clock;
2461         temp = div_u64(temp, link_clock);
2462         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2463         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2464         m_n->gmch_n = DATA_N;
2465         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2466
2467         temp = (u64) LINK_N * pixel_clock;
2468         m_n->link_m = div_u64(temp, link_clock);
2469         m_n->link_n = LINK_N;
2470         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2471 }
2472
2473
2474 struct intel_watermark_params {
2475         unsigned long fifo_size;
2476         unsigned long max_wm;
2477         unsigned long default_wm;
2478         unsigned long guard_size;
2479         unsigned long cacheline_size;
2480 };
2481
2482 /* Pineview has different values for various configs */
2483 static struct intel_watermark_params pineview_display_wm = {
2484         PINEVIEW_DISPLAY_FIFO,
2485         PINEVIEW_MAX_WM,
2486         PINEVIEW_DFT_WM,
2487         PINEVIEW_GUARD_WM,
2488         PINEVIEW_FIFO_LINE_SIZE
2489 };
2490 static struct intel_watermark_params pineview_display_hplloff_wm = {
2491         PINEVIEW_DISPLAY_FIFO,
2492         PINEVIEW_MAX_WM,
2493         PINEVIEW_DFT_HPLLOFF_WM,
2494         PINEVIEW_GUARD_WM,
2495         PINEVIEW_FIFO_LINE_SIZE
2496 };
2497 static struct intel_watermark_params pineview_cursor_wm = {
2498         PINEVIEW_CURSOR_FIFO,
2499         PINEVIEW_CURSOR_MAX_WM,
2500         PINEVIEW_CURSOR_DFT_WM,
2501         PINEVIEW_CURSOR_GUARD_WM,
2502         PINEVIEW_FIFO_LINE_SIZE,
2503 };
2504 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2505         PINEVIEW_CURSOR_FIFO,
2506         PINEVIEW_CURSOR_MAX_WM,
2507         PINEVIEW_CURSOR_DFT_WM,
2508         PINEVIEW_CURSOR_GUARD_WM,
2509         PINEVIEW_FIFO_LINE_SIZE
2510 };
2511 static struct intel_watermark_params g4x_wm_info = {
2512         G4X_FIFO_SIZE,
2513         G4X_MAX_WM,
2514         G4X_MAX_WM,
2515         2,
2516         G4X_FIFO_LINE_SIZE,
2517 };
2518 static struct intel_watermark_params i945_wm_info = {
2519         I945_FIFO_SIZE,
2520         I915_MAX_WM,
2521         1,
2522         2,
2523         I915_FIFO_LINE_SIZE
2524 };
2525 static struct intel_watermark_params i915_wm_info = {
2526         I915_FIFO_SIZE,
2527         I915_MAX_WM,
2528         1,
2529         2,
2530         I915_FIFO_LINE_SIZE
2531 };
2532 static struct intel_watermark_params i855_wm_info = {
2533         I855GM_FIFO_SIZE,
2534         I915_MAX_WM,
2535         1,
2536         2,
2537         I830_FIFO_LINE_SIZE
2538 };
2539 static struct intel_watermark_params i830_wm_info = {
2540         I830_FIFO_SIZE,
2541         I915_MAX_WM,
2542         1,
2543         2,
2544         I830_FIFO_LINE_SIZE
2545 };
2546
2547 /**
2548  * intel_calculate_wm - calculate watermark level
2549  * @clock_in_khz: pixel clock
2550  * @wm: chip FIFO params
2551  * @pixel_size: display pixel size
2552  * @latency_ns: memory latency for the platform
2553  *
2554  * Calculate the watermark level (the level at which the display plane will
2555  * start fetching from memory again).  Each chip has a different display
2556  * FIFO size and allocation, so the caller needs to figure that out and pass
2557  * in the correct intel_watermark_params structure.
2558  *
2559  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2560  * on the pixel size.  When it reaches the watermark level, it'll start
2561  * fetching FIFO line sized based chunks from memory until the FIFO fills
2562  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2563  * will occur, and a display engine hang could result.
2564  */
2565 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2566                                         struct intel_watermark_params *wm,
2567                                         int pixel_size,
2568                                         unsigned long latency_ns)
2569 {
2570         long entries_required, wm_size;
2571
2572         /*
2573          * Note: we need to make sure we don't overflow for various clock &
2574          * latency values.
2575          * clocks go from a few thousand to several hundred thousand.
2576          * latency is usually a few thousand
2577          */
2578         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2579                 1000;
2580         entries_required /= wm->cacheline_size;
2581
2582         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2583
2584         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2585
2586         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2587
2588         /* Don't promote wm_size to unsigned... */
2589         if (wm_size > (long)wm->max_wm)
2590                 wm_size = wm->max_wm;
2591         if (wm_size <= 0)
2592                 wm_size = wm->default_wm;
2593         return wm_size;
2594 }
2595
2596 struct cxsr_latency {
2597         int is_desktop;
2598         unsigned long fsb_freq;
2599         unsigned long mem_freq;
2600         unsigned long display_sr;
2601         unsigned long display_hpll_disable;
2602         unsigned long cursor_sr;
2603         unsigned long cursor_hpll_disable;
2604 };
2605
2606 static struct cxsr_latency cxsr_latency_table[] = {
2607         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2608         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2609         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2610
2611         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2612         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2613         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2614
2615         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2616         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2617         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2618
2619         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2620         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2621         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2622
2623         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2624         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2625         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2626
2627         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2628         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2629         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2630 };
2631
2632 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2633                                                    int mem)
2634 {
2635         int i;
2636         struct cxsr_latency *latency;
2637
2638         if (fsb == 0 || mem == 0)
2639                 return NULL;
2640
2641         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2642                 latency = &cxsr_latency_table[i];
2643                 if (is_desktop == latency->is_desktop &&
2644                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2645                         return latency;
2646         }
2647
2648         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2649
2650         return NULL;
2651 }
2652
2653 static void pineview_disable_cxsr(struct drm_device *dev)
2654 {
2655         struct drm_i915_private *dev_priv = dev->dev_private;
2656         u32 reg;
2657
2658         /* deactivate cxsr */
2659         reg = I915_READ(DSPFW3);
2660         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2661         I915_WRITE(DSPFW3, reg);
2662         DRM_INFO("Big FIFO is disabled\n");
2663 }
2664
2665 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2666                                  int pixel_size)
2667 {
2668         struct drm_i915_private *dev_priv = dev->dev_private;
2669         u32 reg;
2670         unsigned long wm;
2671         struct cxsr_latency *latency;
2672
2673         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2674                 dev_priv->mem_freq);
2675         if (!latency) {
2676                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2677                 pineview_disable_cxsr(dev);
2678                 return;
2679         }
2680
2681         /* Display SR */
2682         wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2683                                 latency->display_sr);
2684         reg = I915_READ(DSPFW1);
2685         reg &= 0x7fffff;
2686         reg |= wm << 23;
2687         I915_WRITE(DSPFW1, reg);
2688         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2689
2690         /* cursor SR */
2691         wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2692                                 latency->cursor_sr);
2693         reg = I915_READ(DSPFW3);
2694         reg &= ~(0x3f << 24);
2695         reg |= (wm & 0x3f) << 24;
2696         I915_WRITE(DSPFW3, reg);
2697
2698         /* Display HPLL off SR */
2699         wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2700                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2701         reg = I915_READ(DSPFW3);
2702         reg &= 0xfffffe00;
2703         reg |= wm & 0x1ff;
2704         I915_WRITE(DSPFW3, reg);
2705
2706         /* cursor HPLL off SR */
2707         wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2708                                 latency->cursor_hpll_disable);
2709         reg = I915_READ(DSPFW3);
2710         reg &= ~(0x3f << 16);
2711         reg |= (wm & 0x3f) << 16;
2712         I915_WRITE(DSPFW3, reg);
2713         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2714
2715         /* activate cxsr */
2716         reg = I915_READ(DSPFW3);
2717         reg |= PINEVIEW_SELF_REFRESH_EN;
2718         I915_WRITE(DSPFW3, reg);
2719
2720         DRM_INFO("Big FIFO is enabled\n");
2721
2722         return;
2723 }
2724
2725 /*
2726  * Latency for FIFO fetches is dependent on several factors:
2727  *   - memory configuration (speed, channels)
2728  *   - chipset
2729  *   - current MCH state
2730  * It can be fairly high in some situations, so here we assume a fairly
2731  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2732  * set this value too high, the FIFO will fetch frequently to stay full)
2733  * and power consumption (set it too low to save power and we might see
2734  * FIFO underruns and display "flicker").
2735  *
2736  * A value of 5us seems to be a good balance; safe for very low end
2737  * platforms but not overly aggressive on lower latency configs.
2738  */
2739 static const int latency_ns = 5000;
2740
2741 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2742 {
2743         struct drm_i915_private *dev_priv = dev->dev_private;
2744         uint32_t dsparb = I915_READ(DSPARB);
2745         int size;
2746
2747         if (plane == 0)
2748                 size = dsparb & 0x7f;
2749         else
2750                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2751                         (dsparb & 0x7f);
2752
2753         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2754                         plane ? "B" : "A", size);
2755
2756         return size;
2757 }
2758
2759 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2760 {
2761         struct drm_i915_private *dev_priv = dev->dev_private;
2762         uint32_t dsparb = I915_READ(DSPARB);
2763         int size;
2764
2765         if (plane == 0)
2766                 size = dsparb & 0x1ff;
2767         else
2768                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2769                         (dsparb & 0x1ff);
2770         size >>= 1; /* Convert to cachelines */
2771
2772         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2773                         plane ? "B" : "A", size);
2774
2775         return size;
2776 }
2777
2778 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2779 {
2780         struct drm_i915_private *dev_priv = dev->dev_private;
2781         uint32_t dsparb = I915_READ(DSPARB);
2782         int size;
2783
2784         size = dsparb & 0x7f;
2785         size >>= 2; /* Convert to cachelines */
2786
2787         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2788                         plane ? "B" : "A",
2789                   size);
2790
2791         return size;
2792 }
2793
2794 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2795 {
2796         struct drm_i915_private *dev_priv = dev->dev_private;
2797         uint32_t dsparb = I915_READ(DSPARB);
2798         int size;
2799
2800         size = dsparb & 0x7f;
2801         size >>= 1; /* Convert to cachelines */
2802
2803         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2804                         plane ? "B" : "A", size);
2805
2806         return size;
2807 }
2808
2809 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2810                           int planeb_clock, int sr_hdisplay, int pixel_size)
2811 {
2812         struct drm_i915_private *dev_priv = dev->dev_private;
2813         int total_size, cacheline_size;
2814         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2815         struct intel_watermark_params planea_params, planeb_params;
2816         unsigned long line_time_us;
2817         int sr_clock, sr_entries = 0, entries_required;
2818
2819         /* Create copies of the base settings for each pipe */
2820         planea_params = planeb_params = g4x_wm_info;
2821
2822         /* Grab a couple of global values before we overwrite them */
2823         total_size = planea_params.fifo_size;
2824         cacheline_size = planea_params.cacheline_size;
2825
2826         /*
2827          * Note: we need to make sure we don't overflow for various clock &
2828          * latency values.
2829          * clocks go from a few thousand to several hundred thousand.
2830          * latency is usually a few thousand
2831          */
2832         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2833                 1000;
2834         entries_required /= G4X_FIFO_LINE_SIZE;
2835         planea_wm = entries_required + planea_params.guard_size;
2836
2837         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2838                 1000;
2839         entries_required /= G4X_FIFO_LINE_SIZE;
2840         planeb_wm = entries_required + planeb_params.guard_size;
2841
2842         cursora_wm = cursorb_wm = 16;
2843         cursor_sr = 32;
2844
2845         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2846
2847         /* Calc sr entries for one plane configs */
2848         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2849                 /* self-refresh has much higher latency */
2850                 static const int sr_latency_ns = 12000;
2851
2852                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2853                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2854
2855                 /* Use ns/us then divide to preserve precision */
2856                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2857                               pixel_size * sr_hdisplay) / 1000;
2858                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2859                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2860                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2861         } else {
2862                 /* Turn off self refresh if both pipes are enabled */
2863                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2864                                         & ~FW_BLC_SELF_EN);
2865         }
2866
2867         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2868                   planea_wm, planeb_wm, sr_entries);
2869
2870         planea_wm &= 0x3f;
2871         planeb_wm &= 0x3f;
2872
2873         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2874                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2875                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2876         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2877                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2878         /* HPLL off in SR has some issues on G4x... disable it */
2879         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2880                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2881 }
2882
2883 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2884                            int planeb_clock, int sr_hdisplay, int pixel_size)
2885 {
2886         struct drm_i915_private *dev_priv = dev->dev_private;
2887         unsigned long line_time_us;
2888         int sr_clock, sr_entries, srwm = 1;
2889
2890         /* Calc sr entries for one plane configs */
2891         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2892                 /* self-refresh has much higher latency */
2893                 static const int sr_latency_ns = 12000;
2894
2895                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2896                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2897
2898                 /* Use ns/us then divide to preserve precision */
2899                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2900                               pixel_size * sr_hdisplay) / 1000;
2901                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2902                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2903                 srwm = I945_FIFO_SIZE - sr_entries;
2904                 if (srwm < 0)
2905                         srwm = 1;
2906                 srwm &= 0x3f;
2907                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2908         } else {
2909                 /* Turn off self refresh if both pipes are enabled */
2910                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2911                                         & ~FW_BLC_SELF_EN);
2912         }
2913
2914         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2915                       srwm);
2916
2917         /* 965 has limitations... */
2918         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2919                    (8 << 0));
2920         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2921 }
2922
2923 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2924                            int planeb_clock, int sr_hdisplay, int pixel_size)
2925 {
2926         struct drm_i915_private *dev_priv = dev->dev_private;
2927         uint32_t fwater_lo;
2928         uint32_t fwater_hi;
2929         int total_size, cacheline_size, cwm, srwm = 1;
2930         int planea_wm, planeb_wm;
2931         struct intel_watermark_params planea_params, planeb_params;
2932         unsigned long line_time_us;
2933         int sr_clock, sr_entries = 0;
2934
2935         /* Create copies of the base settings for each pipe */
2936         if (IS_I965GM(dev) || IS_I945GM(dev))
2937                 planea_params = planeb_params = i945_wm_info;
2938         else if (IS_I9XX(dev))
2939                 planea_params = planeb_params = i915_wm_info;
2940         else
2941                 planea_params = planeb_params = i855_wm_info;
2942
2943         /* Grab a couple of global values before we overwrite them */
2944         total_size = planea_params.fifo_size;
2945         cacheline_size = planea_params.cacheline_size;
2946
2947         /* Update per-plane FIFO sizes */
2948         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2949         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2950
2951         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2952                                        pixel_size, latency_ns);
2953         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2954                                        pixel_size, latency_ns);
2955         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2956
2957         /*
2958          * Overlay gets an aggressive default since video jitter is bad.
2959          */
2960         cwm = 2;
2961
2962         /* Calc sr entries for one plane configs */
2963         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2964             (!planea_clock || !planeb_clock)) {
2965                 /* self-refresh has much higher latency */
2966                 static const int sr_latency_ns = 6000;
2967
2968                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2969                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2970
2971                 /* Use ns/us then divide to preserve precision */
2972                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2973                               pixel_size * sr_hdisplay) / 1000;
2974                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2975                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2976                 srwm = total_size - sr_entries;
2977                 if (srwm < 0)
2978                         srwm = 1;
2979
2980                 if (IS_I945G(dev) || IS_I945GM(dev))
2981                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2982                 else if (IS_I915GM(dev)) {
2983                         /* 915M has a smaller SRWM field */
2984                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2985                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
2986                 }
2987         } else {
2988                 /* Turn off self refresh if both pipes are enabled */
2989                 if (IS_I945G(dev) || IS_I945GM(dev)) {
2990                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2991                                    & ~FW_BLC_SELF_EN);
2992                 } else if (IS_I915GM(dev)) {
2993                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
2994                 }
2995         }
2996
2997         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2998                   planea_wm, planeb_wm, cwm, srwm);
2999
3000         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3001         fwater_hi = (cwm & 0x1f);
3002
3003         /* Set request length to 8 cachelines per fetch */
3004         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3005         fwater_hi = fwater_hi | (1 << 8);
3006
3007         I915_WRITE(FW_BLC, fwater_lo);
3008         I915_WRITE(FW_BLC2, fwater_hi);
3009 }
3010
3011 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3012                            int unused2, int pixel_size)
3013 {
3014         struct drm_i915_private *dev_priv = dev->dev_private;
3015         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3016         int planea_wm;
3017
3018         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3019
3020         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3021                                        pixel_size, latency_ns);
3022         fwater_lo |= (3<<8) | planea_wm;
3023
3024         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3025
3026         I915_WRITE(FW_BLC, fwater_lo);
3027 }
3028
3029 /**
3030  * intel_update_watermarks - update FIFO watermark values based on current modes
3031  *
3032  * Calculate watermark values for the various WM regs based on current mode
3033  * and plane configuration.
3034  *
3035  * There are several cases to deal with here:
3036  *   - normal (i.e. non-self-refresh)
3037  *   - self-refresh (SR) mode
3038  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3039  *   - lines are small relative to FIFO size (buffer can hold more than 2
3040  *     lines), so need to account for TLB latency
3041  *
3042  *   The normal calculation is:
3043  *     watermark = dotclock * bytes per pixel * latency
3044  *   where latency is platform & configuration dependent (we assume pessimal
3045  *   values here).
3046  *
3047  *   The SR calculation is:
3048  *     watermark = (trunc(latency/line time)+1) * surface width *
3049  *       bytes per pixel
3050  *   where
3051  *     line time = htotal / dotclock
3052  *   and latency is assumed to be high, as above.
3053  *
3054  * The final value programmed to the register should always be rounded up,
3055  * and include an extra 2 entries to account for clock crossings.
3056  *
3057  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3058  * to set the non-SR watermarks to 8.
3059   */
3060 static void intel_update_watermarks(struct drm_device *dev)
3061 {
3062         struct drm_i915_private *dev_priv = dev->dev_private;
3063         struct drm_crtc *crtc;
3064         struct intel_crtc *intel_crtc;
3065         int sr_hdisplay = 0;
3066         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3067         int enabled = 0, pixel_size = 0;
3068
3069         if (!dev_priv->display.update_wm)
3070                 return;
3071
3072         /* Get the clock config from both planes */
3073         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3074                 intel_crtc = to_intel_crtc(crtc);
3075                 if (crtc->enabled) {
3076                         enabled++;
3077                         if (intel_crtc->plane == 0) {
3078                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3079                                           intel_crtc->pipe, crtc->mode.clock);
3080                                 planea_clock = crtc->mode.clock;
3081                         } else {
3082                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3083                                           intel_crtc->pipe, crtc->mode.clock);
3084                                 planeb_clock = crtc->mode.clock;
3085                         }
3086                         sr_hdisplay = crtc->mode.hdisplay;
3087                         sr_clock = crtc->mode.clock;
3088                         if (crtc->fb)
3089                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3090                         else
3091                                 pixel_size = 4; /* by default */
3092                 }
3093         }
3094
3095         if (enabled <= 0)
3096                 return;
3097
3098         /* Single plane configs can enable self refresh */
3099         if (enabled == 1 && IS_PINEVIEW(dev))
3100                 pineview_enable_cxsr(dev, sr_clock, pixel_size);
3101         else if (IS_PINEVIEW(dev))
3102                 pineview_disable_cxsr(dev);
3103
3104         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3105                                     sr_hdisplay, pixel_size);
3106 }
3107
3108 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3109                                struct drm_display_mode *mode,
3110                                struct drm_display_mode *adjusted_mode,
3111                                int x, int y,
3112                                struct drm_framebuffer *old_fb)
3113 {
3114         struct drm_device *dev = crtc->dev;
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3117         int pipe = intel_crtc->pipe;
3118         int plane = intel_crtc->plane;
3119         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3120         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3121         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3122         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3123         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3124         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3125         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3126         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3127         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3128         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3129         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3130         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3131         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3132         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3133         int refclk, num_connectors = 0;
3134         intel_clock_t clock, reduced_clock;
3135         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3136         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3137         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3138         bool is_edp = false;
3139         struct drm_mode_config *mode_config = &dev->mode_config;
3140         struct drm_encoder *encoder;
3141         struct intel_encoder *intel_encoder = NULL;
3142         const intel_limit_t *limit;
3143         int ret;
3144         struct fdi_m_n m_n = {0};
3145         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3146         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3147         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3148         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3149         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3150         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3151         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3152         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3153         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3154         int lvds_reg = LVDS;
3155         u32 temp;
3156         int sdvo_pixel_multiply;
3157         int target_clock;
3158
3159         drm_vblank_pre_modeset(dev, pipe);
3160
3161         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3162
3163                 if (!encoder || encoder->crtc != crtc)
3164                         continue;
3165
3166                 intel_encoder = enc_to_intel_encoder(encoder);
3167
3168                 switch (intel_encoder->type) {
3169                 case INTEL_OUTPUT_LVDS:
3170                         is_lvds = true;
3171                         break;
3172                 case INTEL_OUTPUT_SDVO:
3173                 case INTEL_OUTPUT_HDMI:
3174                         is_sdvo = true;
3175                         if (intel_encoder->needs_tv_clock)
3176                                 is_tv = true;
3177                         break;
3178                 case INTEL_OUTPUT_DVO:
3179                         is_dvo = true;
3180                         break;
3181                 case INTEL_OUTPUT_TVOUT:
3182                         is_tv = true;
3183                         break;
3184                 case INTEL_OUTPUT_ANALOG:
3185                         is_crt = true;
3186                         break;
3187                 case INTEL_OUTPUT_DISPLAYPORT:
3188                         is_dp = true;
3189                         break;
3190                 case INTEL_OUTPUT_EDP:
3191                         is_edp = true;
3192                         break;
3193                 }
3194
3195                 num_connectors++;
3196         }
3197
3198         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3199                 refclk = dev_priv->lvds_ssc_freq * 1000;
3200                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3201                                         refclk / 1000);
3202         } else if (IS_I9XX(dev)) {
3203                 refclk = 96000;
3204                 if (HAS_PCH_SPLIT(dev))
3205                         refclk = 120000; /* 120Mhz refclk */
3206         } else {
3207                 refclk = 48000;
3208         }
3209
3210
3211         /*
3212          * Returns a set of divisors for the desired target clock with the given
3213          * refclk, or FALSE.  The returned values represent the clock equation:
3214          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3215          */
3216         limit = intel_limit(crtc);
3217         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3218         if (!ok) {
3219                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3220                 drm_vblank_post_modeset(dev, pipe);
3221                 return -EINVAL;
3222         }
3223
3224         if (is_lvds && dev_priv->lvds_downclock_avail) {
3225                 has_reduced_clock = limit->find_pll(limit, crtc,
3226                                                             dev_priv->lvds_downclock,
3227                                                             refclk,
3228                                                             &reduced_clock);
3229                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3230                         /*
3231                          * If the different P is found, it means that we can't
3232                          * switch the display clock by using the FP0/FP1.
3233                          * In such case we will disable the LVDS downclock
3234                          * feature.
3235                          */
3236                         DRM_DEBUG_KMS("Different P is found for "
3237                                                 "LVDS clock/downclock\n");
3238                         has_reduced_clock = 0;
3239                 }
3240         }
3241         /* SDVO TV has fixed PLL values depend on its clock range,
3242            this mirrors vbios setting. */
3243         if (is_sdvo && is_tv) {
3244                 if (adjusted_mode->clock >= 100000
3245                                 && adjusted_mode->clock < 140500) {
3246                         clock.p1 = 2;
3247                         clock.p2 = 10;
3248                         clock.n = 3;
3249                         clock.m1 = 16;
3250                         clock.m2 = 8;
3251                 } else if (adjusted_mode->clock >= 140500
3252                                 && adjusted_mode->clock <= 200000) {
3253                         clock.p1 = 1;
3254                         clock.p2 = 10;
3255                         clock.n = 6;
3256                         clock.m1 = 12;
3257                         clock.m2 = 8;
3258                 }
3259         }
3260
3261         /* FDI link */
3262         if (HAS_PCH_SPLIT(dev)) {
3263                 int lane, link_bw, bpp;
3264                 /* eDP doesn't require FDI link, so just set DP M/N
3265                    according to current link config */
3266                 if (is_edp) {
3267                         target_clock = mode->clock;
3268                         intel_edp_link_config(intel_encoder,
3269                                         &lane, &link_bw);
3270                 } else {
3271                         /* DP over FDI requires target mode clock
3272                            instead of link clock */
3273                         if (is_dp)
3274                                 target_clock = mode->clock;
3275                         else
3276                                 target_clock = adjusted_mode->clock;
3277                         lane = 4;
3278                         link_bw = 270000;
3279                 }
3280
3281                 /* determine panel color depth */
3282                 temp = I915_READ(pipeconf_reg);
3283                 temp &= ~PIPE_BPC_MASK;
3284                 if (is_lvds) {
3285                         int lvds_reg = I915_READ(PCH_LVDS);
3286                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3287                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3288                                 temp |= PIPE_8BPC;
3289                         else
3290                                 temp |= PIPE_6BPC;
3291                 } else if (is_edp) {
3292                         switch (dev_priv->edp_bpp/3) {
3293                         case 8:
3294                                 temp |= PIPE_8BPC;
3295                                 break;
3296                         case 10:
3297                                 temp |= PIPE_10BPC;
3298                                 break;
3299                         case 6:
3300                                 temp |= PIPE_6BPC;
3301                                 break;
3302                         case 12:
3303                                 temp |= PIPE_12BPC;
3304                                 break;
3305                         }
3306                 } else
3307                         temp |= PIPE_8BPC;
3308                 I915_WRITE(pipeconf_reg, temp);
3309                 I915_READ(pipeconf_reg);
3310
3311                 switch (temp & PIPE_BPC_MASK) {
3312                 case PIPE_8BPC:
3313                         bpp = 24;
3314                         break;
3315                 case PIPE_10BPC:
3316                         bpp = 30;
3317                         break;
3318                 case PIPE_6BPC:
3319                         bpp = 18;
3320                         break;
3321                 case PIPE_12BPC:
3322                         bpp = 36;
3323                         break;
3324                 default:
3325                         DRM_ERROR("unknown pipe bpc value\n");
3326                         bpp = 24;
3327                 }
3328
3329                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3330         }
3331
3332         /* Ironlake: try to setup display ref clock before DPLL
3333          * enabling. This is only under driver's control after
3334          * PCH B stepping, previous chipset stepping should be
3335          * ignoring this setting.
3336          */
3337         if (HAS_PCH_SPLIT(dev)) {
3338                 temp = I915_READ(PCH_DREF_CONTROL);
3339                 /* Always enable nonspread source */
3340                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3341                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3342                 I915_WRITE(PCH_DREF_CONTROL, temp);
3343                 POSTING_READ(PCH_DREF_CONTROL);
3344
3345                 temp &= ~DREF_SSC_SOURCE_MASK;
3346                 temp |= DREF_SSC_SOURCE_ENABLE;
3347                 I915_WRITE(PCH_DREF_CONTROL, temp);
3348                 POSTING_READ(PCH_DREF_CONTROL);
3349
3350                 udelay(200);
3351
3352                 if (is_edp) {
3353                         if (dev_priv->lvds_use_ssc) {
3354                                 temp |= DREF_SSC1_ENABLE;
3355                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3356                                 POSTING_READ(PCH_DREF_CONTROL);
3357
3358                                 udelay(200);
3359
3360                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3361                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3362                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3363                                 POSTING_READ(PCH_DREF_CONTROL);
3364                         } else {
3365                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3366                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3367                                 POSTING_READ(PCH_DREF_CONTROL);
3368                         }
3369                 }
3370         }
3371
3372         if (IS_PINEVIEW(dev)) {
3373                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3374                 if (has_reduced_clock)
3375                         fp2 = (1 << reduced_clock.n) << 16 |
3376                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3377         } else {
3378                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3379                 if (has_reduced_clock)
3380                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3381                                 reduced_clock.m2;
3382         }
3383
3384         if (!HAS_PCH_SPLIT(dev))
3385                 dpll = DPLL_VGA_MODE_DIS;
3386
3387         if (IS_I9XX(dev)) {
3388                 if (is_lvds)
3389                         dpll |= DPLLB_MODE_LVDS;
3390                 else
3391                         dpll |= DPLLB_MODE_DAC_SERIAL;
3392                 if (is_sdvo) {
3393                         dpll |= DPLL_DVO_HIGH_SPEED;
3394                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3395                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3396                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3397                         else if (HAS_PCH_SPLIT(dev))
3398                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3399                 }
3400                 if (is_dp)
3401                         dpll |= DPLL_DVO_HIGH_SPEED;
3402
3403                 /* compute bitmask from p1 value */
3404                 if (IS_PINEVIEW(dev))
3405                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3406                 else {
3407                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3408                         /* also FPA1 */
3409                         if (HAS_PCH_SPLIT(dev))
3410                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3411                         if (IS_G4X(dev) && has_reduced_clock)
3412                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3413                 }
3414                 switch (clock.p2) {
3415                 case 5:
3416                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3417                         break;
3418                 case 7:
3419                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3420                         break;
3421                 case 10:
3422                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3423                         break;
3424                 case 14:
3425                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3426                         break;
3427                 }
3428                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3429                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3430         } else {
3431                 if (is_lvds) {
3432                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3433                 } else {
3434                         if (clock.p1 == 2)
3435                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3436                         else
3437                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3438                         if (clock.p2 == 4)
3439                                 dpll |= PLL_P2_DIVIDE_BY_4;
3440                 }
3441         }
3442
3443         if (is_sdvo && is_tv)
3444                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3445         else if (is_tv)
3446                 /* XXX: just matching BIOS for now */
3447                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3448                 dpll |= 3;
3449         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3450                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3451         else
3452                 dpll |= PLL_REF_INPUT_DREFCLK;
3453
3454         /* setup pipeconf */
3455         pipeconf = I915_READ(pipeconf_reg);
3456
3457         /* Set up the display plane register */
3458         dspcntr = DISPPLANE_GAMMA_ENABLE;
3459
3460         /* Ironlake's plane is forced to pipe, bit 24 is to
3461            enable color space conversion */
3462         if (!HAS_PCH_SPLIT(dev)) {
3463                 if (pipe == 0)
3464                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3465                 else
3466                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3467         }
3468
3469         if (pipe == 0 && !IS_I965G(dev)) {
3470                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3471                  * core speed.
3472                  *
3473                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3474                  * pipe == 0 check?
3475                  */
3476                 if (mode->clock >
3477                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3478                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3479                 else
3480                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3481         }
3482
3483         dspcntr |= DISPLAY_PLANE_ENABLE;
3484         pipeconf |= PIPEACONF_ENABLE;
3485         dpll |= DPLL_VCO_ENABLE;
3486
3487
3488         /* Disable the panel fitter if it was on our pipe */
3489         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3490                 I915_WRITE(PFIT_CONTROL, 0);
3491
3492         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3493         drm_mode_debug_printmodeline(mode);
3494
3495         /* assign to Ironlake registers */
3496         if (HAS_PCH_SPLIT(dev)) {
3497                 fp_reg = pch_fp_reg;
3498                 dpll_reg = pch_dpll_reg;
3499         }
3500
3501         if (is_edp) {
3502                 ironlake_disable_pll_edp(crtc);
3503         } else if ((dpll & DPLL_VCO_ENABLE)) {
3504                 I915_WRITE(fp_reg, fp);
3505                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3506                 I915_READ(dpll_reg);
3507                 udelay(150);
3508         }
3509
3510         /* enable transcoder DPLL */
3511         if (HAS_PCH_CPT(dev)) {
3512                 temp = I915_READ(PCH_DPLL_SEL);
3513                 if (trans_dpll_sel == 0)
3514                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3515                 else
3516                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3517                 I915_WRITE(PCH_DPLL_SEL, temp);
3518                 I915_READ(PCH_DPLL_SEL);
3519                 udelay(150);
3520         }
3521
3522         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3523          * This is an exception to the general rule that mode_set doesn't turn
3524          * things on.
3525          */
3526         if (is_lvds) {
3527                 u32 lvds;
3528
3529                 if (HAS_PCH_SPLIT(dev))
3530                         lvds_reg = PCH_LVDS;
3531
3532                 lvds = I915_READ(lvds_reg);
3533                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3534                 if (pipe == 1) {
3535                         if (HAS_PCH_CPT(dev))
3536                                 lvds |= PORT_TRANS_B_SEL_CPT;
3537                         else
3538                                 lvds |= LVDS_PIPEB_SELECT;
3539                 } else {
3540                         if (HAS_PCH_CPT(dev))
3541                                 lvds &= ~PORT_TRANS_SEL_MASK;
3542                         else
3543                                 lvds &= ~LVDS_PIPEB_SELECT;
3544                 }
3545                 /* set the corresponsding LVDS_BORDER bit */
3546                 lvds |= dev_priv->lvds_border_bits;
3547                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3548                  * set the DPLLs for dual-channel mode or not.
3549                  */
3550                 if (clock.p2 == 7)
3551                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3552                 else
3553                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3554
3555                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3556                  * appropriately here, but we need to look more thoroughly into how
3557                  * panels behave in the two modes.
3558                  */
3559                 /* set the dithering flag */
3560                 if (IS_I965G(dev)) {
3561                         if (dev_priv->lvds_dither) {
3562                                 if (HAS_PCH_SPLIT(dev))
3563                                         pipeconf |= PIPE_ENABLE_DITHER;
3564                                 else
3565                                         lvds |= LVDS_ENABLE_DITHER;
3566                         } else {
3567                                 if (HAS_PCH_SPLIT(dev))
3568                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3569                                 else
3570                                         lvds &= ~LVDS_ENABLE_DITHER;
3571                         }
3572                 }
3573                 I915_WRITE(lvds_reg, lvds);
3574                 I915_READ(lvds_reg);
3575         }
3576         if (is_dp)
3577                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3578         else if (HAS_PCH_SPLIT(dev)) {
3579                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3580                 if (pipe == 0) {
3581                         I915_WRITE(TRANSA_DATA_M1, 0);
3582                         I915_WRITE(TRANSA_DATA_N1, 0);
3583                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3584                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3585                 } else {
3586                         I915_WRITE(TRANSB_DATA_M1, 0);
3587                         I915_WRITE(TRANSB_DATA_N1, 0);
3588                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3589                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3590                 }
3591         }
3592
3593         if (!is_edp) {
3594                 I915_WRITE(fp_reg, fp);
3595                 I915_WRITE(dpll_reg, dpll);
3596                 I915_READ(dpll_reg);
3597                 /* Wait for the clocks to stabilize. */
3598                 udelay(150);
3599
3600                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3601                         if (is_sdvo) {
3602                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3603                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3604                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3605                         } else
3606                                 I915_WRITE(dpll_md_reg, 0);
3607                 } else {
3608                         /* write it again -- the BIOS does, after all */
3609                         I915_WRITE(dpll_reg, dpll);
3610                 }
3611                 I915_READ(dpll_reg);
3612                 /* Wait for the clocks to stabilize. */
3613                 udelay(150);
3614         }
3615
3616         if (is_lvds && has_reduced_clock && i915_powersave) {
3617                 I915_WRITE(fp_reg + 4, fp2);
3618                 intel_crtc->lowfreq_avail = true;
3619                 if (HAS_PIPE_CXSR(dev)) {
3620                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3621                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3622                 }
3623         } else {
3624                 I915_WRITE(fp_reg + 4, fp);
3625                 intel_crtc->lowfreq_avail = false;
3626                 if (HAS_PIPE_CXSR(dev)) {
3627                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3628                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3629                 }
3630         }
3631
3632         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3633                    ((adjusted_mode->crtc_htotal - 1) << 16));
3634         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3635                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3636         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3637                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3638         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3639                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3640         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3641                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3642         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3643                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3644         /* pipesrc and dspsize control the size that is scaled from, which should
3645          * always be the user's requested size.
3646          */
3647         if (!HAS_PCH_SPLIT(dev)) {
3648                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3649                                 (mode->hdisplay - 1));
3650                 I915_WRITE(dsppos_reg, 0);
3651         }
3652         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3653
3654         if (HAS_PCH_SPLIT(dev)) {
3655                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3656                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3657                 I915_WRITE(link_m1_reg, m_n.link_m);
3658                 I915_WRITE(link_n1_reg, m_n.link_n);
3659
3660                 if (is_edp) {
3661                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3662                 } else {
3663                         /* enable FDI RX PLL too */
3664                         temp = I915_READ(fdi_rx_reg);
3665                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3666                         I915_READ(fdi_rx_reg);
3667                         udelay(200);
3668
3669                         /* enable FDI TX PLL too */
3670                         temp = I915_READ(fdi_tx_reg);
3671                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3672                         I915_READ(fdi_tx_reg);
3673
3674                         /* enable FDI RX PCDCLK */
3675                         temp = I915_READ(fdi_rx_reg);
3676                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3677                         I915_READ(fdi_rx_reg);
3678                         udelay(200);
3679                 }
3680         }
3681
3682         I915_WRITE(pipeconf_reg, pipeconf);
3683         I915_READ(pipeconf_reg);
3684
3685         intel_wait_for_vblank(dev);
3686
3687         if (IS_IRONLAKE(dev)) {
3688                 /* enable address swizzle for tiling buffer */
3689                 temp = I915_READ(DISP_ARB_CTL);
3690                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3691         }
3692
3693         I915_WRITE(dspcntr_reg, dspcntr);
3694
3695         /* Flush the plane changes */
3696         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3697
3698         if ((IS_I965G(dev) || plane == 0))
3699                 intel_update_fbc(crtc, &crtc->mode);
3700
3701         intel_update_watermarks(dev);
3702
3703         drm_vblank_post_modeset(dev, pipe);
3704
3705         return ret;
3706 }
3707
3708 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3709 void intel_crtc_load_lut(struct drm_crtc *crtc)
3710 {
3711         struct drm_device *dev = crtc->dev;
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3714         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3715         int i;
3716
3717         /* The clocks have to be on to load the palette. */
3718         if (!crtc->enabled)
3719                 return;
3720
3721         /* use legacy palette for Ironlake */
3722         if (HAS_PCH_SPLIT(dev))
3723                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3724                                                    LGC_PALETTE_B;
3725
3726         for (i = 0; i < 256; i++) {
3727                 I915_WRITE(palreg + 4 * i,
3728                            (intel_crtc->lut_r[i] << 16) |
3729                            (intel_crtc->lut_g[i] << 8) |
3730                            intel_crtc->lut_b[i]);
3731         }
3732 }
3733
3734 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3735                                  struct drm_file *file_priv,
3736                                  uint32_t handle,
3737                                  uint32_t width, uint32_t height)
3738 {
3739         struct drm_device *dev = crtc->dev;
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742         struct drm_gem_object *bo;
3743         struct drm_i915_gem_object *obj_priv;
3744         int pipe = intel_crtc->pipe;
3745         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3746         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3747         uint32_t temp = I915_READ(control);
3748         size_t addr;
3749         int ret;
3750
3751         DRM_DEBUG_KMS("\n");
3752
3753         /* if we want to turn off the cursor ignore width and height */
3754         if (!handle) {
3755                 DRM_DEBUG_KMS("cursor off\n");
3756                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3757                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3758                         temp |= CURSOR_MODE_DISABLE;
3759                 } else {
3760                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3761                 }
3762                 addr = 0;
3763                 bo = NULL;
3764                 mutex_lock(&dev->struct_mutex);
3765                 goto finish;
3766         }
3767
3768         /* Currently we only support 64x64 cursors */
3769         if (width != 64 || height != 64) {
3770                 DRM_ERROR("we currently only support 64x64 cursors\n");
3771                 return -EINVAL;
3772         }
3773
3774         bo = drm_gem_object_lookup(dev, file_priv, handle);
3775         if (!bo)
3776                 return -ENOENT;
3777
3778         obj_priv = to_intel_bo(bo);
3779
3780         if (bo->size < width * height * 4) {
3781                 DRM_ERROR("buffer is to small\n");
3782                 ret = -ENOMEM;
3783                 goto fail;
3784         }
3785
3786         /* we only need to pin inside GTT if cursor is non-phy */
3787         mutex_lock(&dev->struct_mutex);
3788         if (!dev_priv->info->cursor_needs_physical) {
3789                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3790                 if (ret) {
3791                         DRM_ERROR("failed to pin cursor bo\n");
3792                         goto fail_locked;
3793                 }
3794                 addr = obj_priv->gtt_offset;
3795         } else {
3796                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3797                 if (ret) {
3798                         DRM_ERROR("failed to attach phys object\n");
3799                         goto fail_locked;
3800                 }
3801                 addr = obj_priv->phys_obj->handle->busaddr;
3802         }
3803
3804         if (!IS_I9XX(dev))
3805                 I915_WRITE(CURSIZE, (height << 12) | width);
3806
3807         /* Hooray for CUR*CNTR differences */
3808         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3809                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3810                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3811                 temp |= (pipe << 28); /* Connect to correct pipe */
3812         } else {
3813                 temp &= ~(CURSOR_FORMAT_MASK);
3814                 temp |= CURSOR_ENABLE;
3815                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3816         }
3817
3818  finish:
3819         I915_WRITE(control, temp);
3820         I915_WRITE(base, addr);
3821
3822         if (intel_crtc->cursor_bo) {
3823                 if (dev_priv->info->cursor_needs_physical) {
3824                         if (intel_crtc->cursor_bo != bo)
3825                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3826                 } else
3827                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3828                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3829         }
3830
3831         mutex_unlock(&dev->struct_mutex);
3832
3833         intel_crtc->cursor_addr = addr;
3834         intel_crtc->cursor_bo = bo;
3835
3836         return 0;
3837 fail_locked:
3838         mutex_unlock(&dev->struct_mutex);
3839 fail:
3840         drm_gem_object_unreference_unlocked(bo);
3841         return ret;
3842 }
3843
3844 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3845 {
3846         struct drm_device *dev = crtc->dev;
3847         struct drm_i915_private *dev_priv = dev->dev_private;
3848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849         struct intel_framebuffer *intel_fb;
3850         int pipe = intel_crtc->pipe;
3851         uint32_t temp = 0;
3852         uint32_t adder;
3853
3854         if (crtc->fb) {
3855                 intel_fb = to_intel_framebuffer(crtc->fb);
3856                 intel_mark_busy(dev, intel_fb->obj);
3857         }
3858
3859         if (x < 0) {
3860                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3861                 x = -x;
3862         }
3863         if (y < 0) {
3864                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3865                 y = -y;
3866         }
3867
3868         temp |= x << CURSOR_X_SHIFT;
3869         temp |= y << CURSOR_Y_SHIFT;
3870
3871         adder = intel_crtc->cursor_addr;
3872         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3873         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3874
3875         return 0;
3876 }
3877
3878 /** Sets the color ramps on behalf of RandR */
3879 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3880                                  u16 blue, int regno)
3881 {
3882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3883
3884         intel_crtc->lut_r[regno] = red >> 8;
3885         intel_crtc->lut_g[regno] = green >> 8;
3886         intel_crtc->lut_b[regno] = blue >> 8;
3887 }
3888
3889 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3890                              u16 *blue, int regno)
3891 {
3892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893
3894         *red = intel_crtc->lut_r[regno] << 8;
3895         *green = intel_crtc->lut_g[regno] << 8;
3896         *blue = intel_crtc->lut_b[regno] << 8;
3897 }
3898
3899 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3900                                  u16 *blue, uint32_t size)
3901 {
3902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3903         int i;
3904
3905         if (size != 256)
3906                 return;
3907
3908         for (i = 0; i < 256; i++) {
3909                 intel_crtc->lut_r[i] = red[i] >> 8;
3910                 intel_crtc->lut_g[i] = green[i] >> 8;
3911                 intel_crtc->lut_b[i] = blue[i] >> 8;
3912         }
3913
3914         intel_crtc_load_lut(crtc);
3915 }
3916
3917 /**
3918  * Get a pipe with a simple mode set on it for doing load-based monitor
3919  * detection.
3920  *
3921  * It will be up to the load-detect code to adjust the pipe as appropriate for
3922  * its requirements.  The pipe will be connected to no other encoders.
3923  *
3924  * Currently this code will only succeed if there is a pipe with no encoders
3925  * configured for it.  In the future, it could choose to temporarily disable
3926  * some outputs to free up a pipe for its use.
3927  *
3928  * \return crtc, or NULL if no pipes are available.
3929  */
3930
3931 /* VESA 640x480x72Hz mode to set on the pipe */
3932 static struct drm_display_mode load_detect_mode = {
3933         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3934                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3935 };
3936
3937 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
3938                                             struct drm_connector *connector,
3939                                             struct drm_display_mode *mode,
3940                                             int *dpms_mode)
3941 {
3942         struct intel_crtc *intel_crtc;
3943         struct drm_crtc *possible_crtc;
3944         struct drm_crtc *supported_crtc =NULL;
3945         struct drm_encoder *encoder = &intel_encoder->enc;
3946         struct drm_crtc *crtc = NULL;
3947         struct drm_device *dev = encoder->dev;
3948         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3949         struct drm_crtc_helper_funcs *crtc_funcs;
3950         int i = -1;
3951
3952         /*
3953          * Algorithm gets a little messy:
3954          *   - if the connector already has an assigned crtc, use it (but make
3955          *     sure it's on first)
3956          *   - try to find the first unused crtc that can drive this connector,
3957          *     and use that if we find one
3958          *   - if there are no unused crtcs available, try to use the first
3959          *     one we found that supports the connector
3960          */
3961
3962         /* See if we already have a CRTC for this connector */
3963         if (encoder->crtc) {
3964                 crtc = encoder->crtc;
3965                 /* Make sure the crtc and connector are running */
3966                 intel_crtc = to_intel_crtc(crtc);
3967                 *dpms_mode = intel_crtc->dpms_mode;
3968                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3969                         crtc_funcs = crtc->helper_private;
3970                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3971                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3972                 }
3973                 return crtc;
3974         }
3975
3976         /* Find an unused one (if possible) */
3977         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3978                 i++;
3979                 if (!(encoder->possible_crtcs & (1 << i)))
3980                         continue;
3981                 if (!possible_crtc->enabled) {
3982                         crtc = possible_crtc;
3983                         break;
3984                 }
3985                 if (!supported_crtc)
3986                         supported_crtc = possible_crtc;
3987         }
3988
3989         /*
3990          * If we didn't find an unused CRTC, don't use any.
3991          */
3992         if (!crtc) {
3993                 return NULL;
3994         }
3995
3996         encoder->crtc = crtc;
3997         connector->encoder = encoder;
3998         intel_encoder->load_detect_temp = true;
3999
4000         intel_crtc = to_intel_crtc(crtc);
4001         *dpms_mode = intel_crtc->dpms_mode;
4002
4003         if (!crtc->enabled) {
4004                 if (!mode)
4005                         mode = &load_detect_mode;
4006                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4007         } else {
4008                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4009                         crtc_funcs = crtc->helper_private;
4010                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4011                 }
4012
4013                 /* Add this connector to the crtc */
4014                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4015                 encoder_funcs->commit(encoder);
4016         }
4017         /* let the connector get through one full cycle before testing */
4018         intel_wait_for_vblank(dev);
4019
4020         return crtc;
4021 }
4022
4023 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4024                                     struct drm_connector *connector, int dpms_mode)
4025 {
4026         struct drm_encoder *encoder = &intel_encoder->enc;
4027         struct drm_device *dev = encoder->dev;
4028         struct drm_crtc *crtc = encoder->crtc;
4029         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4030         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4031
4032         if (intel_encoder->load_detect_temp) {
4033                 encoder->crtc = NULL;
4034                 connector->encoder = NULL;
4035                 intel_encoder->load_detect_temp = false;
4036                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4037                 drm_helper_disable_unused_functions(dev);
4038         }
4039
4040         /* Switch crtc and encoder back off if necessary */
4041         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4042                 if (encoder->crtc == crtc)
4043                         encoder_funcs->dpms(encoder, dpms_mode);
4044                 crtc_funcs->dpms(crtc, dpms_mode);
4045         }
4046 }
4047
4048 /* Returns the clock of the currently programmed mode of the given pipe. */
4049 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4050 {
4051         struct drm_i915_private *dev_priv = dev->dev_private;
4052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4053         int pipe = intel_crtc->pipe;
4054         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4055         u32 fp;
4056         intel_clock_t clock;
4057
4058         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4059                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4060         else
4061                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4062
4063         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4064         if (IS_PINEVIEW(dev)) {
4065                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4066                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4067         } else {
4068                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4069                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4070         }
4071
4072         if (IS_I9XX(dev)) {
4073                 if (IS_PINEVIEW(dev))
4074                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4075                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4076                 else
4077                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4078                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4079
4080                 switch (dpll & DPLL_MODE_MASK) {
4081                 case DPLLB_MODE_DAC_SERIAL:
4082                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4083                                 5 : 10;
4084                         break;
4085                 case DPLLB_MODE_LVDS:
4086                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4087                                 7 : 14;
4088                         break;
4089                 default:
4090                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4091                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4092                         return 0;
4093                 }
4094
4095                 /* XXX: Handle the 100Mhz refclk */
4096                 intel_clock(dev, 96000, &clock);
4097         } else {
4098                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4099
4100                 if (is_lvds) {
4101                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4102                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4103                         clock.p2 = 14;
4104
4105                         if ((dpll & PLL_REF_INPUT_MASK) ==
4106                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4107                                 /* XXX: might not be 66MHz */
4108                                 intel_clock(dev, 66000, &clock);
4109                         } else
4110                                 intel_clock(dev, 48000, &clock);
4111                 } else {
4112                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4113                                 clock.p1 = 2;
4114                         else {
4115                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4116                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4117                         }
4118                         if (dpll & PLL_P2_DIVIDE_BY_4)
4119                                 clock.p2 = 4;
4120                         else
4121                                 clock.p2 = 2;
4122
4123                         intel_clock(dev, 48000, &clock);
4124                 }
4125         }
4126
4127         /* XXX: It would be nice to validate the clocks, but we can't reuse
4128          * i830PllIsValid() because it relies on the xf86_config connector
4129          * configuration being accurate, which it isn't necessarily.
4130          */
4131
4132         return clock.dot;
4133 }
4134
4135 /** Returns the currently programmed mode of the given pipe. */
4136 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4137                                              struct drm_crtc *crtc)
4138 {
4139         struct drm_i915_private *dev_priv = dev->dev_private;
4140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4141         int pipe = intel_crtc->pipe;
4142         struct drm_display_mode *mode;
4143         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4144         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4145         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4146         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4147
4148         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4149         if (!mode)
4150                 return NULL;
4151
4152         mode->clock = intel_crtc_clock_get(dev, crtc);
4153         mode->hdisplay = (htot & 0xffff) + 1;
4154         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4155         mode->hsync_start = (hsync & 0xffff) + 1;
4156         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4157         mode->vdisplay = (vtot & 0xffff) + 1;
4158         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4159         mode->vsync_start = (vsync & 0xffff) + 1;
4160         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4161
4162         drm_mode_set_name(mode);
4163         drm_mode_set_crtcinfo(mode, 0);
4164
4165         return mode;
4166 }
4167
4168 #define GPU_IDLE_TIMEOUT 500 /* ms */
4169
4170 /* When this timer fires, we've been idle for awhile */
4171 static void intel_gpu_idle_timer(unsigned long arg)
4172 {
4173         struct drm_device *dev = (struct drm_device *)arg;
4174         drm_i915_private_t *dev_priv = dev->dev_private;
4175
4176         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4177
4178         dev_priv->busy = false;
4179
4180         queue_work(dev_priv->wq, &dev_priv->idle_work);
4181 }
4182
4183 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4184
4185 static void intel_crtc_idle_timer(unsigned long arg)
4186 {
4187         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4188         struct drm_crtc *crtc = &intel_crtc->base;
4189         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4190
4191         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4192
4193         intel_crtc->busy = false;
4194
4195         queue_work(dev_priv->wq, &dev_priv->idle_work);
4196 }
4197
4198 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4199 {
4200         struct drm_device *dev = crtc->dev;
4201         drm_i915_private_t *dev_priv = dev->dev_private;
4202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4203         int pipe = intel_crtc->pipe;
4204         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4205         int dpll = I915_READ(dpll_reg);
4206
4207         if (HAS_PCH_SPLIT(dev))
4208                 return;
4209
4210         if (!dev_priv->lvds_downclock_avail)
4211                 return;
4212
4213         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4214                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4215
4216                 /* Unlock panel regs */
4217                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4218
4219                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4220                 I915_WRITE(dpll_reg, dpll);
4221                 dpll = I915_READ(dpll_reg);
4222                 intel_wait_for_vblank(dev);
4223                 dpll = I915_READ(dpll_reg);
4224                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4225                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4226
4227                 /* ...and lock them again */
4228                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4229         }
4230
4231         /* Schedule downclock */
4232         if (schedule)
4233                 mod_timer(&intel_crtc->idle_timer, jiffies +
4234                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4235 }
4236
4237 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4238 {
4239         struct drm_device *dev = crtc->dev;
4240         drm_i915_private_t *dev_priv = dev->dev_private;
4241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4242         int pipe = intel_crtc->pipe;
4243         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4244         int dpll = I915_READ(dpll_reg);
4245
4246         if (HAS_PCH_SPLIT(dev))
4247                 return;
4248
4249         if (!dev_priv->lvds_downclock_avail)
4250                 return;
4251
4252         /*
4253          * Since this is called by a timer, we should never get here in
4254          * the manual case.
4255          */
4256         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4257                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4258
4259                 /* Unlock panel regs */
4260                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4261
4262                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4263                 I915_WRITE(dpll_reg, dpll);
4264                 dpll = I915_READ(dpll_reg);
4265                 intel_wait_for_vblank(dev);
4266                 dpll = I915_READ(dpll_reg);
4267                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4268                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4269
4270                 /* ...and lock them again */
4271                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4272         }
4273
4274 }
4275
4276 /**
4277  * intel_idle_update - adjust clocks for idleness
4278  * @work: work struct
4279  *
4280  * Either the GPU or display (or both) went idle.  Check the busy status
4281  * here and adjust the CRTC and GPU clocks as necessary.
4282  */
4283 static void intel_idle_update(struct work_struct *work)
4284 {
4285         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4286                                                     idle_work);
4287         struct drm_device *dev = dev_priv->dev;
4288         struct drm_crtc *crtc;
4289         struct intel_crtc *intel_crtc;
4290
4291         if (!i915_powersave)
4292                 return;
4293
4294         mutex_lock(&dev->struct_mutex);
4295
4296         if (IS_I945G(dev) || IS_I945GM(dev)) {
4297                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4298                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4299         }
4300
4301         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4302                 /* Skip inactive CRTCs */
4303                 if (!crtc->fb)
4304                         continue;
4305
4306                 intel_crtc = to_intel_crtc(crtc);
4307                 if (!intel_crtc->busy)
4308                         intel_decrease_pllclock(crtc);
4309         }
4310
4311         mutex_unlock(&dev->struct_mutex);
4312 }
4313
4314 /**
4315  * intel_mark_busy - mark the GPU and possibly the display busy
4316  * @dev: drm device
4317  * @obj: object we're operating on
4318  *
4319  * Callers can use this function to indicate that the GPU is busy processing
4320  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4321  * buffer), we'll also mark the display as busy, so we know to increase its
4322  * clock frequency.
4323  */
4324 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4325 {
4326         drm_i915_private_t *dev_priv = dev->dev_private;
4327         struct drm_crtc *crtc = NULL;
4328         struct intel_framebuffer *intel_fb;
4329         struct intel_crtc *intel_crtc;
4330
4331         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4332                 return;
4333
4334         if (!dev_priv->busy) {
4335                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4336                         u32 fw_blc_self;
4337
4338                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4339                         fw_blc_self = I915_READ(FW_BLC_SELF);
4340                         fw_blc_self &= ~FW_BLC_SELF_EN;
4341                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4342                 }
4343                 dev_priv->busy = true;
4344         } else
4345                 mod_timer(&dev_priv->idle_timer, jiffies +
4346                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4347
4348         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4349                 if (!crtc->fb)
4350                         continue;
4351
4352                 intel_crtc = to_intel_crtc(crtc);
4353                 intel_fb = to_intel_framebuffer(crtc->fb);
4354                 if (intel_fb->obj == obj) {
4355                         if (!intel_crtc->busy) {
4356                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4357                                         u32 fw_blc_self;
4358
4359                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4360                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4361                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4362                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4363                                 }
4364                                 /* Non-busy -> busy, upclock */
4365                                 intel_increase_pllclock(crtc, true);
4366                                 intel_crtc->busy = true;
4367                         } else {
4368                                 /* Busy -> busy, put off timer */
4369                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4370                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4371                         }
4372                 }
4373         }
4374 }
4375
4376 static void intel_crtc_destroy(struct drm_crtc *crtc)
4377 {
4378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4379
4380         drm_crtc_cleanup(crtc);
4381         kfree(intel_crtc);
4382 }
4383
4384 struct intel_unpin_work {
4385         struct work_struct work;
4386         struct drm_device *dev;
4387         struct drm_gem_object *old_fb_obj;
4388         struct drm_gem_object *pending_flip_obj;
4389         struct drm_pending_vblank_event *event;
4390         int pending;
4391 };
4392
4393 static void intel_unpin_work_fn(struct work_struct *__work)
4394 {
4395         struct intel_unpin_work *work =
4396                 container_of(__work, struct intel_unpin_work, work);
4397
4398         mutex_lock(&work->dev->struct_mutex);
4399         i915_gem_object_unpin(work->old_fb_obj);
4400         drm_gem_object_unreference(work->pending_flip_obj);
4401         drm_gem_object_unreference(work->old_fb_obj);
4402         mutex_unlock(&work->dev->struct_mutex);
4403         kfree(work);
4404 }
4405
4406 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4407 {
4408         drm_i915_private_t *dev_priv = dev->dev_private;
4409         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4411         struct intel_unpin_work *work;
4412         struct drm_i915_gem_object *obj_priv;
4413         struct drm_pending_vblank_event *e;
4414         struct timeval now;
4415         unsigned long flags;
4416
4417         /* Ignore early vblank irqs */
4418         if (intel_crtc == NULL)
4419                 return;
4420
4421         spin_lock_irqsave(&dev->event_lock, flags);
4422         work = intel_crtc->unpin_work;
4423         if (work == NULL || !work->pending) {
4424                 if (work && !work->pending) {
4425                         obj_priv = to_intel_bo(work->pending_flip_obj);
4426                         DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4427                                          obj_priv,
4428                                          atomic_read(&obj_priv->pending_flip));
4429                 }
4430                 spin_unlock_irqrestore(&dev->event_lock, flags);
4431                 return;
4432         }
4433
4434         intel_crtc->unpin_work = NULL;
4435         drm_vblank_put(dev, intel_crtc->pipe);
4436
4437         if (work->event) {
4438                 e = work->event;
4439                 do_gettimeofday(&now);
4440                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4441                 e->event.tv_sec = now.tv_sec;
4442                 e->event.tv_usec = now.tv_usec;
4443                 list_add_tail(&e->base.link,
4444                               &e->base.file_priv->event_list);
4445                 wake_up_interruptible(&e->base.file_priv->event_wait);
4446         }
4447
4448         spin_unlock_irqrestore(&dev->event_lock, flags);
4449
4450         obj_priv = to_intel_bo(work->pending_flip_obj);
4451
4452         /* Initial scanout buffer will have a 0 pending flip count */
4453         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4454             atomic_dec_and_test(&obj_priv->pending_flip))
4455                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4456         schedule_work(&work->work);
4457 }
4458
4459 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4460 {
4461         drm_i915_private_t *dev_priv = dev->dev_private;
4462         struct intel_crtc *intel_crtc =
4463                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4464         unsigned long flags;
4465
4466         spin_lock_irqsave(&dev->event_lock, flags);
4467         if (intel_crtc->unpin_work) {
4468                 intel_crtc->unpin_work->pending = 1;
4469         } else {
4470                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4471         }
4472         spin_unlock_irqrestore(&dev->event_lock, flags);
4473 }
4474
4475 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4476                                 struct drm_framebuffer *fb,
4477                                 struct drm_pending_vblank_event *event)
4478 {
4479         struct drm_device *dev = crtc->dev;
4480         struct drm_i915_private *dev_priv = dev->dev_private;
4481         struct intel_framebuffer *intel_fb;
4482         struct drm_i915_gem_object *obj_priv;
4483         struct drm_gem_object *obj;
4484         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4485         struct intel_unpin_work *work;
4486         unsigned long flags;
4487         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4488         int ret, pipesrc;
4489         RING_LOCALS;
4490
4491         work = kzalloc(sizeof *work, GFP_KERNEL);
4492         if (work == NULL)
4493                 return -ENOMEM;
4494
4495         mutex_lock(&dev->struct_mutex);
4496
4497         work->event = event;
4498         work->dev = crtc->dev;
4499         intel_fb = to_intel_framebuffer(crtc->fb);
4500         work->old_fb_obj = intel_fb->obj;
4501         INIT_WORK(&work->work, intel_unpin_work_fn);
4502
4503         /* We borrow the event spin lock for protecting unpin_work */
4504         spin_lock_irqsave(&dev->event_lock, flags);
4505         if (intel_crtc->unpin_work) {
4506                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4507                 spin_unlock_irqrestore(&dev->event_lock, flags);
4508                 kfree(work);
4509                 mutex_unlock(&dev->struct_mutex);
4510                 return -EBUSY;
4511         }
4512         intel_crtc->unpin_work = work;
4513         spin_unlock_irqrestore(&dev->event_lock, flags);
4514
4515         intel_fb = to_intel_framebuffer(fb);
4516         obj = intel_fb->obj;
4517
4518         ret = intel_pin_and_fence_fb_obj(dev, obj);
4519         if (ret != 0) {
4520                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4521                           to_intel_bo(obj));
4522                 kfree(work);
4523                 intel_crtc->unpin_work = NULL;
4524                 mutex_unlock(&dev->struct_mutex);
4525                 return ret;
4526         }
4527
4528         /* Reference the objects for the scheduled work. */
4529         drm_gem_object_reference(work->old_fb_obj);
4530         drm_gem_object_reference(obj);
4531
4532         crtc->fb = fb;
4533         i915_gem_object_flush_write_domain(obj);
4534         drm_vblank_get(dev, intel_crtc->pipe);
4535         obj_priv = to_intel_bo(obj);
4536         atomic_inc(&obj_priv->pending_flip);
4537         work->pending_flip_obj = obj;
4538
4539         BEGIN_LP_RING(4);
4540         OUT_RING(MI_DISPLAY_FLIP |
4541                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4542         OUT_RING(fb->pitch);
4543         if (IS_I965G(dev)) {
4544                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4545                 pipesrc = I915_READ(pipesrc_reg);
4546                 OUT_RING(pipesrc & 0x0fff0fff);
4547         } else {
4548                 OUT_RING(obj_priv->gtt_offset);
4549                 OUT_RING(MI_NOOP);
4550         }
4551         ADVANCE_LP_RING();
4552
4553         mutex_unlock(&dev->struct_mutex);
4554
4555         return 0;
4556 }
4557
4558 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4559         .dpms = intel_crtc_dpms,
4560         .mode_fixup = intel_crtc_mode_fixup,
4561         .mode_set = intel_crtc_mode_set,
4562         .mode_set_base = intel_pipe_set_base,
4563         .prepare = intel_crtc_prepare,
4564         .commit = intel_crtc_commit,
4565         .load_lut = intel_crtc_load_lut,
4566 };
4567
4568 static const struct drm_crtc_funcs intel_crtc_funcs = {
4569         .cursor_set = intel_crtc_cursor_set,
4570         .cursor_move = intel_crtc_cursor_move,
4571         .gamma_set = intel_crtc_gamma_set,
4572         .set_config = drm_crtc_helper_set_config,
4573         .destroy = intel_crtc_destroy,
4574         .page_flip = intel_crtc_page_flip,
4575 };
4576
4577
4578 static void intel_crtc_init(struct drm_device *dev, int pipe)
4579 {
4580         drm_i915_private_t *dev_priv = dev->dev_private;
4581         struct intel_crtc *intel_crtc;
4582         int i;
4583
4584         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4585         if (intel_crtc == NULL)
4586                 return;
4587
4588         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4589
4590         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4591         intel_crtc->pipe = pipe;
4592         intel_crtc->plane = pipe;
4593         for (i = 0; i < 256; i++) {
4594                 intel_crtc->lut_r[i] = i;
4595                 intel_crtc->lut_g[i] = i;
4596                 intel_crtc->lut_b[i] = i;
4597         }
4598
4599         /* Swap pipes & planes for FBC on pre-965 */
4600         intel_crtc->pipe = pipe;
4601         intel_crtc->plane = pipe;
4602         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4603                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4604                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4605         }
4606
4607         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4608                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4609         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4610         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4611
4612         intel_crtc->cursor_addr = 0;
4613         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4614         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4615
4616         intel_crtc->busy = false;
4617
4618         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4619                     (unsigned long)intel_crtc);
4620 }
4621
4622 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4623                                 struct drm_file *file_priv)
4624 {
4625         drm_i915_private_t *dev_priv = dev->dev_private;
4626         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4627         struct drm_mode_object *drmmode_obj;
4628         struct intel_crtc *crtc;
4629
4630         if (!dev_priv) {
4631                 DRM_ERROR("called with no initialization\n");
4632                 return -EINVAL;
4633         }
4634
4635         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4636                         DRM_MODE_OBJECT_CRTC);
4637
4638         if (!drmmode_obj) {
4639                 DRM_ERROR("no such CRTC id\n");
4640                 return -EINVAL;
4641         }
4642
4643         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4644         pipe_from_crtc_id->pipe = crtc->pipe;
4645
4646         return 0;
4647 }
4648
4649 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4650 {
4651         struct drm_crtc *crtc = NULL;
4652
4653         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4654                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4655                 if (intel_crtc->pipe == pipe)
4656                         break;
4657         }
4658         return crtc;
4659 }
4660
4661 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4662 {
4663         int index_mask = 0;
4664         struct drm_encoder *encoder;
4665         int entry = 0;
4666
4667         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4668                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4669                 if (type_mask & intel_encoder->clone_mask)
4670                         index_mask |= (1 << entry);
4671                 entry++;
4672         }
4673         return index_mask;
4674 }
4675
4676
4677 static void intel_setup_outputs(struct drm_device *dev)
4678 {
4679         struct drm_i915_private *dev_priv = dev->dev_private;
4680         struct drm_encoder *encoder;
4681
4682         intel_crt_init(dev);
4683
4684         /* Set up integrated LVDS */
4685         if (IS_MOBILE(dev) && !IS_I830(dev))
4686                 intel_lvds_init(dev);
4687
4688         if (HAS_PCH_SPLIT(dev)) {
4689                 int found;
4690
4691                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4692                         intel_dp_init(dev, DP_A);
4693
4694                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4695                         /* check SDVOB */
4696                         /* found = intel_sdvo_init(dev, HDMIB); */
4697                         found = 0;
4698                         if (!found)
4699                                 intel_hdmi_init(dev, HDMIB);
4700                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4701                                 intel_dp_init(dev, PCH_DP_B);
4702                 }
4703
4704                 if (I915_READ(HDMIC) & PORT_DETECTED)
4705                         intel_hdmi_init(dev, HDMIC);
4706
4707                 if (I915_READ(HDMID) & PORT_DETECTED)
4708                         intel_hdmi_init(dev, HDMID);
4709
4710                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4711                         intel_dp_init(dev, PCH_DP_C);
4712
4713                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4714                         intel_dp_init(dev, PCH_DP_D);
4715
4716         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4717                 bool found = false;
4718
4719                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4720                         DRM_DEBUG_KMS("probing SDVOB\n");
4721                         found = intel_sdvo_init(dev, SDVOB);
4722                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4723                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4724                                 intel_hdmi_init(dev, SDVOB);
4725                         }
4726
4727                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4728                                 DRM_DEBUG_KMS("probing DP_B\n");
4729                                 intel_dp_init(dev, DP_B);
4730                         }
4731                 }
4732
4733                 /* Before G4X SDVOC doesn't have its own detect register */
4734
4735                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4736                         DRM_DEBUG_KMS("probing SDVOC\n");
4737                         found = intel_sdvo_init(dev, SDVOC);
4738                 }
4739
4740                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4741
4742                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4743                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4744                                 intel_hdmi_init(dev, SDVOC);
4745                         }
4746                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4747                                 DRM_DEBUG_KMS("probing DP_C\n");
4748                                 intel_dp_init(dev, DP_C);
4749                         }
4750                 }
4751
4752                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4753                     (I915_READ(DP_D) & DP_DETECTED)) {
4754                         DRM_DEBUG_KMS("probing DP_D\n");
4755                         intel_dp_init(dev, DP_D);
4756                 }
4757         } else if (IS_GEN2(dev))
4758                 intel_dvo_init(dev);
4759
4760         if (SUPPORTS_TV(dev))
4761                 intel_tv_init(dev);
4762
4763         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4764                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4765
4766                 encoder->possible_crtcs = intel_encoder->crtc_mask;
4767                 encoder->possible_clones = intel_encoder_clones(dev,
4768                                                 intel_encoder->clone_mask);
4769         }
4770 }
4771
4772 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4773 {
4774         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4775         struct drm_device *dev = fb->dev;
4776
4777         if (fb->fbdev)
4778                 intelfb_remove(dev, fb);
4779
4780         drm_framebuffer_cleanup(fb);
4781         drm_gem_object_unreference_unlocked(intel_fb->obj);
4782
4783         kfree(intel_fb);
4784 }
4785
4786 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4787                                                 struct drm_file *file_priv,
4788                                                 unsigned int *handle)
4789 {
4790         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4791         struct drm_gem_object *object = intel_fb->obj;
4792
4793         return drm_gem_handle_create(file_priv, object, handle);
4794 }
4795
4796 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4797         .destroy = intel_user_framebuffer_destroy,
4798         .create_handle = intel_user_framebuffer_create_handle,
4799 };
4800
4801 int intel_framebuffer_create(struct drm_device *dev,
4802                              struct drm_mode_fb_cmd *mode_cmd,
4803                              struct drm_framebuffer **fb,
4804                              struct drm_gem_object *obj)
4805 {
4806         struct intel_framebuffer *intel_fb;
4807         int ret;
4808
4809         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4810         if (!intel_fb)
4811                 return -ENOMEM;
4812
4813         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4814         if (ret) {
4815                 DRM_ERROR("framebuffer init failed %d\n", ret);
4816                 return ret;
4817         }
4818
4819         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4820
4821         intel_fb->obj = obj;
4822
4823         *fb = &intel_fb->base;
4824
4825         return 0;
4826 }
4827
4828
4829 static struct drm_framebuffer *
4830 intel_user_framebuffer_create(struct drm_device *dev,
4831                               struct drm_file *filp,
4832                               struct drm_mode_fb_cmd *mode_cmd)
4833 {
4834         struct drm_gem_object *obj;
4835         struct drm_framebuffer *fb;
4836         int ret;
4837
4838         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4839         if (!obj)
4840                 return NULL;
4841
4842         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4843         if (ret) {
4844                 drm_gem_object_unreference_unlocked(obj);
4845                 return NULL;
4846         }
4847
4848         return fb;
4849 }
4850
4851 static const struct drm_mode_config_funcs intel_mode_funcs = {
4852         .fb_create = intel_user_framebuffer_create,
4853         .fb_changed = intelfb_probe,
4854 };
4855
4856 static struct drm_gem_object *
4857 intel_alloc_power_context(struct drm_device *dev)
4858 {
4859         struct drm_gem_object *pwrctx;
4860         int ret;
4861
4862         pwrctx = drm_gem_object_alloc(dev, 4096);
4863         if (!pwrctx) {
4864                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4865                 return NULL;
4866         }
4867
4868         mutex_lock(&dev->struct_mutex);
4869         ret = i915_gem_object_pin(pwrctx, 4096);
4870         if (ret) {
4871                 DRM_ERROR("failed to pin power context: %d\n", ret);
4872                 goto err_unref;
4873         }
4874
4875         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4876         if (ret) {
4877                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4878                 goto err_unpin;
4879         }
4880         mutex_unlock(&dev->struct_mutex);
4881
4882         return pwrctx;
4883
4884 err_unpin:
4885         i915_gem_object_unpin(pwrctx);
4886 err_unref:
4887         drm_gem_object_unreference(pwrctx);
4888         mutex_unlock(&dev->struct_mutex);
4889         return NULL;
4890 }
4891
4892 void ironlake_enable_drps(struct drm_device *dev)
4893 {
4894         struct drm_i915_private *dev_priv = dev->dev_private;
4895         u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
4896         u8 fmax, fmin, fstart, vstart;
4897         int i = 0;
4898
4899         /* 100ms RC evaluation intervals */
4900         I915_WRITE(RCUPEI, 100000);
4901         I915_WRITE(RCDNEI, 100000);
4902
4903         /* Set max/min thresholds to 90ms and 80ms respectively */
4904         I915_WRITE(RCBMAXAVG, 90000);
4905         I915_WRITE(RCBMINAVG, 80000);
4906
4907         I915_WRITE(MEMIHYST, 1);
4908
4909         /* Set up min, max, and cur for interrupt handling */
4910         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4911         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4912         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4913                 MEMMODE_FSTART_SHIFT;
4914         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4915                 PXVFREQ_PX_SHIFT;
4916
4917         dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
4918         dev_priv->min_delay = fmin;
4919         dev_priv->cur_delay = fstart;
4920
4921         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4922
4923         /*
4924          * Interrupts will be enabled in ironlake_irq_postinstall
4925          */
4926
4927         I915_WRITE(VIDSTART, vstart);
4928         POSTING_READ(VIDSTART);
4929
4930         rgvmodectl |= MEMMODE_SWMODE_EN;
4931         I915_WRITE(MEMMODECTL, rgvmodectl);
4932
4933         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
4934                 if (i++ > 100) {
4935                         DRM_ERROR("stuck trying to change perf mode\n");
4936                         break;
4937                 }
4938                 msleep(1);
4939         }
4940         msleep(1);
4941
4942         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4943                 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4944         I915_WRITE(MEMSWCTL, rgvswctl);
4945         POSTING_READ(MEMSWCTL);
4946
4947         rgvswctl |= MEMCTL_CMD_STS;
4948         I915_WRITE(MEMSWCTL, rgvswctl);
4949 }
4950
4951 void ironlake_disable_drps(struct drm_device *dev)
4952 {
4953         struct drm_i915_private *dev_priv = dev->dev_private;
4954         u32 rgvswctl;
4955         u8 fstart;
4956
4957         /* Ack interrupts, disable EFC interrupt */
4958         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4959         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4960         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4961         I915_WRITE(DEIIR, DE_PCU_EVENT);
4962         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4963
4964         /* Go back to the starting frequency */
4965         fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
4966                 MEMMODE_FSTART_SHIFT;
4967         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4968                 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4969         I915_WRITE(MEMSWCTL, rgvswctl);
4970         msleep(1);
4971         rgvswctl |= MEMCTL_CMD_STS;
4972         I915_WRITE(MEMSWCTL, rgvswctl);
4973         msleep(1);
4974
4975 }
4976
4977 void intel_init_clock_gating(struct drm_device *dev)
4978 {
4979         struct drm_i915_private *dev_priv = dev->dev_private;
4980
4981         /*
4982          * Disable clock gating reported to work incorrectly according to the
4983          * specs, but enable as much else as we can.
4984          */
4985         if (HAS_PCH_SPLIT(dev)) {
4986                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
4987
4988                 if (IS_IRONLAKE(dev)) {
4989                         /* Required for FBC */
4990                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
4991                         /* Required for CxSR */
4992                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
4993
4994                         I915_WRITE(PCH_3DCGDIS0,
4995                                    MARIUNIT_CLOCK_GATE_DISABLE |
4996                                    SVSMUNIT_CLOCK_GATE_DISABLE);
4997                 }
4998
4999                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5000                 return;
5001         } else if (IS_G4X(dev)) {
5002                 uint32_t dspclk_gate;
5003                 I915_WRITE(RENCLK_GATE_D1, 0);
5004                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5005                        GS_UNIT_CLOCK_GATE_DISABLE |
5006                        CL_UNIT_CLOCK_GATE_DISABLE);
5007                 I915_WRITE(RAMCLK_GATE_D, 0);
5008                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5009                         OVRUNIT_CLOCK_GATE_DISABLE |
5010                         OVCUNIT_CLOCK_GATE_DISABLE;
5011                 if (IS_GM45(dev))
5012                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5013                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5014         } else if (IS_I965GM(dev)) {
5015                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5016                 I915_WRITE(RENCLK_GATE_D2, 0);
5017                 I915_WRITE(DSPCLK_GATE_D, 0);
5018                 I915_WRITE(RAMCLK_GATE_D, 0);
5019                 I915_WRITE16(DEUC, 0);
5020         } else if (IS_I965G(dev)) {
5021                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5022                        I965_RCC_CLOCK_GATE_DISABLE |
5023                        I965_RCPB_CLOCK_GATE_DISABLE |
5024                        I965_ISC_CLOCK_GATE_DISABLE |
5025                        I965_FBC_CLOCK_GATE_DISABLE);
5026                 I915_WRITE(RENCLK_GATE_D2, 0);
5027         } else if (IS_I9XX(dev)) {
5028                 u32 dstate = I915_READ(D_STATE);
5029
5030                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5031                         DSTATE_DOT_CLOCK_GATING;
5032                 I915_WRITE(D_STATE, dstate);
5033         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5034                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5035         } else if (IS_I830(dev)) {
5036                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5037         }
5038
5039         /*
5040          * GPU can automatically power down the render unit if given a page
5041          * to save state.
5042          */
5043         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5044                 struct drm_i915_gem_object *obj_priv = NULL;
5045
5046                 if (dev_priv->pwrctx) {
5047                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5048                 } else {
5049                         struct drm_gem_object *pwrctx;
5050
5051                         pwrctx = intel_alloc_power_context(dev);
5052                         if (pwrctx) {
5053                                 dev_priv->pwrctx = pwrctx;
5054                                 obj_priv = to_intel_bo(pwrctx);
5055                         }
5056                 }
5057
5058                 if (obj_priv) {
5059                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5060                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5061                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5062                 }
5063         }
5064 }
5065
5066 /* Set up chip specific display functions */
5067 static void intel_init_display(struct drm_device *dev)
5068 {
5069         struct drm_i915_private *dev_priv = dev->dev_private;
5070
5071         /* We always want a DPMS function */
5072         if (HAS_PCH_SPLIT(dev))
5073                 dev_priv->display.dpms = ironlake_crtc_dpms;
5074         else
5075                 dev_priv->display.dpms = i9xx_crtc_dpms;
5076
5077         /* Only mobile has FBC, leave pointers NULL for other chips */
5078         if (IS_MOBILE(dev)) {
5079                 if (IS_GM45(dev)) {
5080                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5081                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5082                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5083                 } else if (IS_I965GM(dev)) {
5084                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5085                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5086                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5087                 }
5088                 /* 855GM needs testing */
5089         }
5090
5091         /* Returns the core display clock speed */
5092         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5093                 dev_priv->display.get_display_clock_speed =
5094                         i945_get_display_clock_speed;
5095         else if (IS_I915G(dev))
5096                 dev_priv->display.get_display_clock_speed =
5097                         i915_get_display_clock_speed;
5098         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5099                 dev_priv->display.get_display_clock_speed =
5100                         i9xx_misc_get_display_clock_speed;
5101         else if (IS_I915GM(dev))
5102                 dev_priv->display.get_display_clock_speed =
5103                         i915gm_get_display_clock_speed;
5104         else if (IS_I865G(dev))
5105                 dev_priv->display.get_display_clock_speed =
5106                         i865_get_display_clock_speed;
5107         else if (IS_I85X(dev))
5108                 dev_priv->display.get_display_clock_speed =
5109                         i855_get_display_clock_speed;
5110         else /* 852, 830 */
5111                 dev_priv->display.get_display_clock_speed =
5112                         i830_get_display_clock_speed;
5113
5114         /* For FIFO watermark updates */
5115         if (HAS_PCH_SPLIT(dev))
5116                 dev_priv->display.update_wm = NULL;
5117         else if (IS_G4X(dev))
5118                 dev_priv->display.update_wm = g4x_update_wm;
5119         else if (IS_I965G(dev))
5120                 dev_priv->display.update_wm = i965_update_wm;
5121         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
5122                 dev_priv->display.update_wm = i9xx_update_wm;
5123                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5124         } else {
5125                 if (IS_I85X(dev))
5126                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5127                 else if (IS_845G(dev))
5128                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5129                 else
5130                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5131                 dev_priv->display.update_wm = i830_update_wm;
5132         }
5133 }
5134
5135 void intel_modeset_init(struct drm_device *dev)
5136 {
5137         struct drm_i915_private *dev_priv = dev->dev_private;
5138         int num_pipe;
5139         int i;
5140
5141         drm_mode_config_init(dev);
5142
5143         dev->mode_config.min_width = 0;
5144         dev->mode_config.min_height = 0;
5145
5146         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5147
5148         intel_init_display(dev);
5149
5150         if (IS_I965G(dev)) {
5151                 dev->mode_config.max_width = 8192;
5152                 dev->mode_config.max_height = 8192;
5153         } else if (IS_I9XX(dev)) {
5154                 dev->mode_config.max_width = 4096;
5155                 dev->mode_config.max_height = 4096;
5156         } else {
5157                 dev->mode_config.max_width = 2048;
5158                 dev->mode_config.max_height = 2048;
5159         }
5160
5161         /* set memory base */
5162         if (IS_I9XX(dev))
5163                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5164         else
5165                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5166
5167         if (IS_MOBILE(dev) || IS_I9XX(dev))
5168                 num_pipe = 2;
5169         else
5170                 num_pipe = 1;
5171         DRM_DEBUG_KMS("%d display pipe%s available.\n",
5172                   num_pipe, num_pipe > 1 ? "s" : "");
5173
5174         for (i = 0; i < num_pipe; i++) {
5175                 intel_crtc_init(dev, i);
5176         }
5177
5178         intel_setup_outputs(dev);
5179
5180         intel_init_clock_gating(dev);
5181
5182         if (IS_IRONLAKE_M(dev))
5183                 ironlake_enable_drps(dev);
5184
5185         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5186         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5187                     (unsigned long)dev);
5188
5189         intel_setup_overlay(dev);
5190
5191         if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5192                                                         dev_priv->fsb_freq,
5193                                                         dev_priv->mem_freq))
5194                 DRM_INFO("failed to find known CxSR latency "
5195                          "(found fsb freq %d, mem freq %d), disabling CxSR\n",
5196                          dev_priv->fsb_freq, dev_priv->mem_freq);
5197 }
5198
5199 void intel_modeset_cleanup(struct drm_device *dev)
5200 {
5201         struct drm_i915_private *dev_priv = dev->dev_private;
5202         struct drm_crtc *crtc;
5203         struct intel_crtc *intel_crtc;
5204
5205         mutex_lock(&dev->struct_mutex);
5206
5207         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5208                 /* Skip inactive CRTCs */
5209                 if (!crtc->fb)
5210                         continue;
5211
5212                 intel_crtc = to_intel_crtc(crtc);
5213                 intel_increase_pllclock(crtc, false);
5214                 del_timer_sync(&intel_crtc->idle_timer);
5215         }
5216
5217         del_timer_sync(&dev_priv->idle_timer);
5218
5219         if (dev_priv->display.disable_fbc)
5220                 dev_priv->display.disable_fbc(dev);
5221
5222         if (dev_priv->pwrctx) {
5223                 struct drm_i915_gem_object *obj_priv;
5224
5225                 obj_priv = to_intel_bo(dev_priv->pwrctx);
5226                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5227                 I915_READ(PWRCTXA);
5228                 i915_gem_object_unpin(dev_priv->pwrctx);
5229                 drm_gem_object_unreference(dev_priv->pwrctx);
5230         }
5231
5232         if (IS_IRONLAKE_M(dev))
5233                 ironlake_disable_drps(dev);
5234
5235         mutex_unlock(&dev->struct_mutex);
5236
5237         drm_mode_config_cleanup(dev);
5238 }
5239
5240
5241 /* current intel driver doesn't take advantage of encoders
5242    always give back the encoder for the connector
5243 */
5244 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
5245 {
5246         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
5247
5248         return &intel_encoder->enc;
5249 }
5250
5251 /*
5252  * Return which encoder is currently attached for connector.
5253  */
5254 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5255 {
5256         struct drm_mode_object *obj;
5257         struct drm_encoder *encoder;
5258         int i;
5259
5260         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5261                 if (connector->encoder_ids[i] == 0)
5262                         break;
5263
5264                 obj = drm_mode_object_find(connector->dev,
5265                                            connector->encoder_ids[i],
5266                                            DRM_MODE_OBJECT_ENCODER);
5267                 if (!obj)
5268                         continue;
5269
5270                 encoder = obj_to_encoder(obj);
5271                 return encoder;
5272         }
5273         return NULL;
5274 }
5275
5276 /*
5277  * set vga decode state - true == enable VGA decode
5278  */
5279 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5280 {
5281         struct drm_i915_private *dev_priv = dev->dev_private;
5282         u16 gmch_ctrl;
5283
5284         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5285         if (state)
5286                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5287         else
5288                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5289         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5290         return 0;
5291 }