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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 710              clock.m1++) {
 711                 for (clock.m2 = limit->m2.min;
 712                      clock.m2 <= limit->m2.max; clock.m2++) {
 713                         /* m1 is always 0 in IGD */
 714                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 715                                 break;
 716                         for (clock.n = limit->n.min;
 717                              clock.n <= limit->n.max; clock.n++) {
 718                                 for (clock.p1 = limit->p1.min;
 719                                         clock.p1 <= limit->p1.max; clock.p1++) {
 720                                         int this_err;
 721
 722                                         intel_clock(dev, refclk, &clock);
 723
 724                                         if (!intel_PLL_is_valid(crtc, &clock))
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740
 741 static bool
 742 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 743                             int target, int refclk, intel_clock_t *best_clock)
 744
 745 {
 746         struct drm_device *dev = crtc->dev;
 747         intel_clock_t clock;
 748         int err = target;
 749         bool found = false;
 750
 751         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 752
 753         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 754                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 755                         /* m1 is always 0 in IGD */
 756                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 757                                 break;
 758                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 759                              clock.n++) {
 760                                 int this_err;
 761
 762                                 intel_clock(dev, refclk, &clock);
 763
 764                                 if (!intel_PLL_is_valid(crtc, &clock))
 765                                         continue;
 766
 767                                 this_err = abs(clock.dot - target);
 768                                 if (this_err < err) {
 769                                         *best_clock = clock;
 770                                         err = this_err;
 771                                         found = true;
 772                                 }
 773                         }
 774                 }
 775         }
 776
 777         return found;
 778 }
 779
 780 static bool
 781 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 782                         int target, int refclk, intel_clock_t *best_clock)
 783 {
 784         struct drm_device *dev = crtc->dev;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         intel_clock_t clock;
 787         int max_n;
 788         bool found;
 789         /* approximately equals target * 0.00488 */
 790         int err_most = (target >> 8) + (target >> 10);
 791         found = false;
 792
 793         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 794                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 795                     LVDS_CLKB_POWER_UP)
 796                         clock.p2 = limit->p2.p2_fast;
 797                 else
 798                         clock.p2 = limit->p2.p2_slow;
 799         } else {
 800                 if (target < limit->p2.dot_limit)
 801                         clock.p2 = limit->p2.p2_slow;
 802                 else
 803                         clock.p2 = limit->p2.p2_fast;
 804         }
 805
 806         memset(best_clock, 0, sizeof(*best_clock));
 807         max_n = limit->n.max;
 808         /* based on hardware requriment prefer smaller n to precision */
 809         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 810                 /* based on hardware requirment prefere larger m1,m2 */
 811                 for (clock.m1 = limit->m1.max;
 812                      clock.m1 >= limit->m1.min; clock.m1--) {
 813                         for (clock.m2 = limit->m2.max;
 814                              clock.m2 >= limit->m2.min; clock.m2--) {
 815                                 for (clock.p1 = limit->p1.max;
 816                                      clock.p1 >= limit->p1.min; clock.p1--) {
 817                                         int this_err;
 818
 819                                         intel_clock(dev, refclk, &clock);
 820                                         if (!intel_PLL_is_valid(crtc, &clock))
 821                                                 continue;
 822                                         this_err = abs(clock.dot - target) ;
 823                                         if (this_err < err_most) {
 824                                                 *best_clock = clock;
 825                                                 err_most = this_err;
 826                                                 max_n = clock.n;
 827                                                 found = true;
 828                                         }
 829                                 }
 830                         }
 831                 }
 832         }
 833         return found;
 834 }
 835
 836 static bool
 837 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 838                       int target, int refclk, intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->dev;
 841         intel_clock_t clock;
 842         if (target < 200000) {
 843                 clock.n = 1;
 844                 clock.p1 = 2;
 845                 clock.p2 = 10;
 846                 clock.m1 = 12;
 847                 clock.m2 = 9;
 848         } else {
 849                 clock.n = 2;
 850                 clock.p1 = 1;
 851                 clock.p2 = 10;
 852                 clock.m1 = 14;
 853                 clock.m2 = 8;
 854         }
 855         intel_clock(dev, refclk, &clock);
 856         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 857         return true;
 858 }
 859
 860 static bool
 861 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 862                         int target, int refclk, intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc->dev;
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         intel_clock_t clock;
 867         int err_most = 47;
 868         int err_min = 10000;
 869
 870         /* eDP has only 2 clock choice, no n/m/p setting */
 871         if (HAS_eDP)
 872                 return true;
 873
 874         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 875                 return intel_find_pll_igdng_dp(limit, crtc, target,
 876                                                refclk, best_clock);
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 880                     LVDS_CLKB_POWER_UP)
 881                         clock.p2 = limit->p2.p2_fast;
 882                 else
 883                         clock.p2 = limit->p2.p2_slow;
 884         } else {
 885                 if (target < limit->p2.dot_limit)
 886                         clock.p2 = limit->p2.p2_slow;
 887                 else
 888                         clock.p2 = limit->p2.p2_fast;
 889         }
 890
 891         memset(best_clock, 0, sizeof(*best_clock));
 892         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 893                 /* based on hardware requriment prefer smaller n to precision */
 894                 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
 895                         /* based on hardware requirment prefere larger m1,m2 */
 896                         for (clock.m1 = limit->m1.max;
 897                              clock.m1 >= limit->m1.min; clock.m1--) {
 898                                 for (clock.m2 = limit->m2.max;
 899                                      clock.m2 >= limit->m2.min; clock.m2--) {
 900                                         int this_err;
 901
 902                                         intel_clock(dev, refclk, &clock);
 903                                         if (!intel_PLL_is_valid(crtc, &clock))
 904                                                 continue;
 905                                         this_err = abs((10000 - (target*10000/clock.dot)));
 906                                         if (this_err < err_most) {
 907                                                 *best_clock = clock;
 908                                                 /* found on first matching */
 909                                                 goto out;
 910                                         } else if (this_err < err_min) {
 911                                                 *best_clock = clock;
 912                                                 err_min = this_err;
 913                                         }
 914                                 }
 915                         }
 916                 }
 917         }
 918 out:
 919         return true;
 920 }
 921
 922 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 923 static bool
 924 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 925                       int target, int refclk, intel_clock_t *best_clock)
 926 {
 927     intel_clock_t clock;
 928     if (target < 200000) {
 929         clock.p1 = 2;
 930         clock.p2 = 10;
 931         clock.n = 2;
 932         clock.m1 = 23;
 933         clock.m2 = 8;
 934     } else {
 935         clock.p1 = 1;
 936         clock.p2 = 10;
 937         clock.n = 1;
 938         clock.m1 = 14;
 939         clock.m2 = 2;
 940     }
 941     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 942     clock.p = (clock.p1 * clock.p2);
 943     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 944     clock.vco = 0;
 945     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 946     return true;
 947 }
 948
 949 void
 950 intel_wait_for_vblank(struct drm_device *dev)
 951 {
 952         /* Wait for 20ms, i.e. one cycle at 50hz. */
 953         msleep(20);
 954 }
 955
 956 /* Parameters have changed, update FBC info */
 957 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 958 {
 959         struct drm_device *dev = crtc->dev;
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         struct drm_framebuffer *fb = crtc->fb;
 962         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 963         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 965         int plane, i;
 966         u32 fbc_ctl, fbc_ctl2;
 967
 968         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 969
 970         if (fb->pitch < dev_priv->cfb_pitch)
 971                 dev_priv->cfb_pitch = fb->pitch;
 972
 973         /* FBC_CTL wants 64B units */
 974         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 975         dev_priv->cfb_fence = obj_priv->fence_reg;
 976         dev_priv->cfb_plane = intel_crtc->plane;
 977         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 978
 979         /* Clear old tags */
 980         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 981                 I915_WRITE(FBC_TAG + (i * 4), 0);
 982
 983         /* Set it up... */
 984         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 985         if (obj_priv->tiling_mode != I915_TILING_NONE)
 986                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 987         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 988         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 989
 990         /* enable it... */
 991         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 992         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 993         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 994         if (obj_priv->tiling_mode != I915_TILING_NONE)
 995                 fbc_ctl |= dev_priv->cfb_fence;
 996         I915_WRITE(FBC_CONTROL, fbc_ctl);
 997
 998         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
 999                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1000 }
1001
1002 void i8xx_disable_fbc(struct drm_device *dev)
1003 {
1004         struct drm_i915_private *dev_priv = dev->dev_private;
1005         u32 fbc_ctl;
1006
1007         if (!I915_HAS_FBC(dev))
1008                 return;
1009
1010         /* Disable compression */
1011         fbc_ctl = I915_READ(FBC_CONTROL);
1012         fbc_ctl &= ~FBC_CTL_EN;
1013         I915_WRITE(FBC_CONTROL, fbc_ctl);
1014
1015         /* Wait for compressing bit to clear */
1016         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1017                 ; /* nothing */
1018
1019         intel_wait_for_vblank(dev);
1020
1021         DRM_DEBUG_KMS("disabled FBC\n");
1022 }
1023
1024 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1025 {
1026         struct drm_device *dev = crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028
1029         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1030 }
1031
1032 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1033 {
1034         struct drm_device *dev = crtc->dev;
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         struct drm_framebuffer *fb = crtc->fb;
1037         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1038         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1040         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1041                      DPFC_CTL_PLANEB);
1042         unsigned long stall_watermark = 200;
1043         u32 dpfc_ctl;
1044
1045         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1046         dev_priv->cfb_fence = obj_priv->fence_reg;
1047         dev_priv->cfb_plane = intel_crtc->plane;
1048
1049         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1050         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1051                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1052                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1053         } else {
1054                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1055         }
1056
1057         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1058         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1059                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1060                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1061         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1062
1063         /* enable it... */
1064         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1065
1066         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1067 }
1068
1069 void g4x_disable_fbc(struct drm_device *dev)
1070 {
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         u32 dpfc_ctl;
1073
1074         /* Disable compression */
1075         dpfc_ctl = I915_READ(DPFC_CONTROL);
1076         dpfc_ctl &= ~DPFC_CTL_EN;
1077         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1078         intel_wait_for_vblank(dev);
1079
1080         DRM_DEBUG_KMS("disabled FBC\n");
1081 }
1082
1083 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1084 {
1085         struct drm_device *dev = crtc->dev;
1086         struct drm_i915_private *dev_priv = dev->dev_private;
1087
1088         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1089 }
1090
1091 /**
1092  * intel_update_fbc - enable/disable FBC as needed
1093  * @crtc: CRTC to point the compressor at
1094  * @mode: mode in use
1095  *
1096  * Set up the framebuffer compression hardware at mode set time.  We
1097  * enable it if possible:
1098  *   - plane A only (on pre-965)
1099  *   - no pixel mulitply/line duplication
1100  *   - no alpha buffer discard
1101  *   - no dual wide
1102  *   - framebuffer <= 2048 in width, 1536 in height
1103  *
1104  * We can't assume that any compression will take place (worst case),
1105  * so the compressed buffer has to be the same size as the uncompressed
1106  * one.  It also must reside (along with the line length buffer) in
1107  * stolen memory.
1108  *
1109  * We need to enable/disable FBC on a global basis.
1110  */
1111 static void intel_update_fbc(struct drm_crtc *crtc,
1112                              struct drm_display_mode *mode)
1113 {
1114         struct drm_device *dev = crtc->dev;
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         struct drm_framebuffer *fb = crtc->fb;
1117         struct intel_framebuffer *intel_fb;
1118         struct drm_i915_gem_object *obj_priv;
1119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1120         int plane = intel_crtc->plane;
1121
1122         if (!i915_powersave)
1123                 return;
1124
1125         if (!dev_priv->display.fbc_enabled ||
1126             !dev_priv->display.enable_fbc ||
1127             !dev_priv->display.disable_fbc)
1128                 return;
1129
1130         if (!crtc->fb)
1131                 return;
1132
1133         intel_fb = to_intel_framebuffer(fb);
1134         obj_priv = intel_fb->obj->driver_private;
1135
1136         /*
1137          * If FBC is already on, we just have to verify that we can
1138          * keep it that way...
1139          * Need to disable if:
1140          *   - changing FBC params (stride, fence, mode)
1141          *   - new fb is too large to fit in compressed buffer
1142          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1143          */
1144         if (intel_fb->obj->size > dev_priv->cfb_size) {
1145                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1146                                 "compression\n");
1147                 goto out_disable;
1148         }
1149         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1150             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1151                 DRM_DEBUG_KMS("mode incompatible with compression, "
1152                                 "disabling\n");
1153                 goto out_disable;
1154         }
1155         if ((mode->hdisplay > 2048) ||
1156             (mode->vdisplay > 1536)) {
1157                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1158                 goto out_disable;
1159         }
1160         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1161                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1162                 goto out_disable;
1163         }
1164         if (obj_priv->tiling_mode != I915_TILING_X) {
1165                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1166                 goto out_disable;
1167         }
1168
1169         if (dev_priv->display.fbc_enabled(crtc)) {
1170                 /* We can re-enable it in this case, but need to update pitch */
1171                 if (fb->pitch > dev_priv->cfb_pitch)
1172                         dev_priv->display.disable_fbc(dev);
1173                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1174                         dev_priv->display.disable_fbc(dev);
1175                 if (plane != dev_priv->cfb_plane)
1176                         dev_priv->display.disable_fbc(dev);
1177         }
1178
1179         if (!dev_priv->display.fbc_enabled(crtc)) {
1180                 /* Now try to turn it back on if possible */
1181                 dev_priv->display.enable_fbc(crtc, 500);
1182         }
1183
1184         return;
1185
1186 out_disable:
1187         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1188         /* Multiple disables should be harmless */
1189         if (dev_priv->display.fbc_enabled(crtc))
1190                 dev_priv->display.disable_fbc(dev);
1191 }
1192
1193 static int
1194 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1195 {
1196         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1197         u32 alignment;
1198         int ret;
1199
1200         switch (obj_priv->tiling_mode) {
1201         case I915_TILING_NONE:
1202                 alignment = 64 * 1024;
1203                 break;
1204         case I915_TILING_X:
1205                 /* pin() will align the object as required by fence */
1206                 alignment = 0;
1207                 break;
1208         case I915_TILING_Y:
1209                 /* FIXME: Is this true? */
1210                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1211                 return -EINVAL;
1212         default:
1213                 BUG();
1214         }
1215
1216         alignment = 256 * 1024;
1217         ret = i915_gem_object_pin(obj, alignment);
1218         if (ret != 0)
1219                 return ret;
1220
1221         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1222          * fence, whereas 965+ only requires a fence if using
1223          * framebuffer compression.  For simplicity, we always install
1224          * a fence as the cost is not that onerous.
1225          */
1226         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1227             obj_priv->tiling_mode != I915_TILING_NONE) {
1228                 ret = i915_gem_object_get_fence_reg(obj);
1229                 if (ret != 0) {
1230                         i915_gem_object_unpin(obj);
1231                         return ret;
1232                 }
1233         }
1234
1235         return 0;
1236 }
1237
1238 static int
1239 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1240                     struct drm_framebuffer *old_fb)
1241 {
1242         struct drm_device *dev = crtc->dev;
1243         struct drm_i915_private *dev_priv = dev->dev_private;
1244         struct drm_i915_master_private *master_priv;
1245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1246         struct intel_framebuffer *intel_fb;
1247         struct drm_i915_gem_object *obj_priv;
1248         struct drm_gem_object *obj;
1249         int pipe = intel_crtc->pipe;
1250         int plane = intel_crtc->plane;
1251         unsigned long Start, Offset;
1252         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1253         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1254         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1255         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1256         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1257         u32 dspcntr;
1258         int ret;
1259
1260         /* no fb bound */
1261         if (!crtc->fb) {
1262                 DRM_DEBUG_KMS("No FB bound\n");
1263                 return 0;
1264         }
1265
1266         switch (plane) {
1267         case 0:
1268         case 1:
1269                 break;
1270         default:
1271                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1272                 return -EINVAL;
1273         }
1274
1275         intel_fb = to_intel_framebuffer(crtc->fb);
1276         obj = intel_fb->obj;
1277         obj_priv = obj->driver_private;
1278
1279         mutex_lock(&dev->struct_mutex);
1280         ret = intel_pin_and_fence_fb_obj(dev, obj);
1281         if (ret != 0) {
1282                 mutex_unlock(&dev->struct_mutex);
1283                 return ret;
1284         }
1285
1286         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1287         if (ret != 0) {
1288                 i915_gem_object_unpin(obj);
1289                 mutex_unlock(&dev->struct_mutex);
1290                 return ret;
1291         }
1292
1293         dspcntr = I915_READ(dspcntr_reg);
1294         /* Mask out pixel format bits in case we change it */
1295         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1296         switch (crtc->fb->bits_per_pixel) {
1297         case 8:
1298                 dspcntr |= DISPPLANE_8BPP;
1299                 break;
1300         case 16:
1301                 if (crtc->fb->depth == 15)
1302                         dspcntr |= DISPPLANE_15_16BPP;
1303                 else
1304                         dspcntr |= DISPPLANE_16BPP;
1305                 break;
1306         case 24:
1307         case 32:
1308                 if (crtc->fb->depth == 30)
1309                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1310                 else
1311                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1312                 break;
1313         default:
1314                 DRM_ERROR("Unknown color depth\n");
1315                 i915_gem_object_unpin(obj);
1316                 mutex_unlock(&dev->struct_mutex);
1317                 return -EINVAL;
1318         }
1319         if (IS_I965G(dev)) {
1320                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1321                         dspcntr |= DISPPLANE_TILED;
1322                 else
1323                         dspcntr &= ~DISPPLANE_TILED;
1324         }
1325
1326         if (IS_IGDNG(dev))
1327                 /* must disable */
1328                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1329
1330         I915_WRITE(dspcntr_reg, dspcntr);
1331
1332         Start = obj_priv->gtt_offset;
1333         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1334
1335         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1336         I915_WRITE(dspstride, crtc->fb->pitch);
1337         if (IS_I965G(dev)) {
1338                 I915_WRITE(dspbase, Offset);
1339                 I915_READ(dspbase);
1340                 I915_WRITE(dspsurf, Start);
1341                 I915_READ(dspsurf);
1342                 I915_WRITE(dsptileoff, (y << 16) | x);
1343         } else {
1344                 I915_WRITE(dspbase, Start + Offset);
1345                 I915_READ(dspbase);
1346         }
1347
1348         if ((IS_I965G(dev) || plane == 0))
1349                 intel_update_fbc(crtc, &crtc->mode);
1350
1351         intel_wait_for_vblank(dev);
1352
1353         if (old_fb) {
1354                 intel_fb = to_intel_framebuffer(old_fb);
1355                 obj_priv = intel_fb->obj->driver_private;
1356                 i915_gem_object_unpin(intel_fb->obj);
1357         }
1358         intel_increase_pllclock(crtc, true);
1359
1360         mutex_unlock(&dev->struct_mutex);
1361
1362         if (!dev->primary->master)
1363                 return 0;
1364
1365         master_priv = dev->primary->master->driver_priv;
1366         if (!master_priv->sarea_priv)
1367                 return 0;
1368
1369         if (pipe) {
1370                 master_priv->sarea_priv->pipeB_x = x;
1371                 master_priv->sarea_priv->pipeB_y = y;
1372         } else {
1373                 master_priv->sarea_priv->pipeA_x = x;
1374                 master_priv->sarea_priv->pipeA_y = y;
1375         }
1376
1377         return 0;
1378 }
1379
1380 /* Disable the VGA plane that we never use */
1381 static void i915_disable_vga (struct drm_device *dev)
1382 {
1383         struct drm_i915_private *dev_priv = dev->dev_private;
1384         u8 sr1;
1385         u32 vga_reg;
1386
1387         if (IS_IGDNG(dev))
1388                 vga_reg = CPU_VGACNTRL;
1389         else
1390                 vga_reg = VGACNTRL;
1391
1392         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1393                 return;
1394
1395         I915_WRITE8(VGA_SR_INDEX, 1);
1396         sr1 = I915_READ8(VGA_SR_DATA);
1397         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1398         udelay(100);
1399
1400         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1401 }
1402
1403 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1404 {
1405         struct drm_device *dev = crtc->dev;
1406         struct drm_i915_private *dev_priv = dev->dev_private;
1407         u32 dpa_ctl;
1408
1409         DRM_DEBUG_KMS("\n");
1410         dpa_ctl = I915_READ(DP_A);
1411         dpa_ctl &= ~DP_PLL_ENABLE;
1412         I915_WRITE(DP_A, dpa_ctl);
1413 }
1414
1415 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1416 {
1417         struct drm_device *dev = crtc->dev;
1418         struct drm_i915_private *dev_priv = dev->dev_private;
1419         u32 dpa_ctl;
1420
1421         dpa_ctl = I915_READ(DP_A);
1422         dpa_ctl |= DP_PLL_ENABLE;
1423         I915_WRITE(DP_A, dpa_ctl);
1424         udelay(200);
1425 }
1426
1427
1428 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1429 {
1430         struct drm_device *dev = crtc->dev;
1431         struct drm_i915_private *dev_priv = dev->dev_private;
1432         u32 dpa_ctl;
1433
1434         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1435         dpa_ctl = I915_READ(DP_A);
1436         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1437
1438         if (clock < 200000) {
1439                 u32 temp;
1440                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1441                 /* workaround for 160Mhz:
1442                    1) program 0x4600c bits 15:0 = 0x8124
1443                    2) program 0x46010 bit 0 = 1
1444                    3) program 0x46034 bit 24 = 1
1445                    4) program 0x64000 bit 14 = 1
1446                    */
1447                 temp = I915_READ(0x4600c);
1448                 temp &= 0xffff0000;
1449                 I915_WRITE(0x4600c, temp | 0x8124);
1450
1451                 temp = I915_READ(0x46010);
1452                 I915_WRITE(0x46010, temp | 1);
1453
1454                 temp = I915_READ(0x46034);
1455                 I915_WRITE(0x46034, temp | (1 << 24));
1456         } else {
1457                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1458         }
1459         I915_WRITE(DP_A, dpa_ctl);
1460
1461         udelay(500);
1462 }
1463
1464 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1465 {
1466         struct drm_device *dev = crtc->dev;
1467         struct drm_i915_private *dev_priv = dev->dev_private;
1468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1469         int pipe = intel_crtc->pipe;
1470         int plane = intel_crtc->plane;
1471         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1472         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1473         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1474         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1475         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1476         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1477         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1478         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1479         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1480         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1481         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1482         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1483         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1484         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1485         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1486         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1487         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1488         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1489         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1490         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1491         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1492         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1493         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1494         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1495         u32 temp;
1496         int tries = 5, j, n;
1497
1498         /* XXX: When our outputs are all unaware of DPMS modes other than off
1499          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1500          */
1501         switch (mode) {
1502         case DRM_MODE_DPMS_ON:
1503         case DRM_MODE_DPMS_STANDBY:
1504         case DRM_MODE_DPMS_SUSPEND:
1505                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1506
1507                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1508                         temp = I915_READ(PCH_LVDS);
1509                         if ((temp & LVDS_PORT_EN) == 0) {
1510                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1511                                 POSTING_READ(PCH_LVDS);
1512                         }
1513                 }
1514
1515                 if (HAS_eDP) {
1516                         /* enable eDP PLL */
1517                         igdng_enable_pll_edp(crtc);
1518                 } else {
1519                         /* enable PCH DPLL */
1520                         temp = I915_READ(pch_dpll_reg);
1521                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1522                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1523                                 I915_READ(pch_dpll_reg);
1524                         }
1525
1526                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1527                         temp = I915_READ(fdi_rx_reg);
1528                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1529                                         FDI_SEL_PCDCLK |
1530                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1531                         I915_READ(fdi_rx_reg);
1532                         udelay(200);
1533
1534                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1535                         temp = I915_READ(fdi_tx_reg);
1536                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1537                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1538                                 I915_READ(fdi_tx_reg);
1539                                 udelay(100);
1540                         }
1541                 }
1542
1543                 /* Enable panel fitting for LVDS */
1544                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1545                         temp = I915_READ(pf_ctl_reg);
1546                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1547
1548                         /* currently full aspect */
1549                         I915_WRITE(pf_win_pos, 0);
1550
1551                         I915_WRITE(pf_win_size,
1552                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1553                                    (dev_priv->panel_fixed_mode->vdisplay));
1554                 }
1555
1556                 /* Enable CPU pipe */
1557                 temp = I915_READ(pipeconf_reg);
1558                 if ((temp & PIPEACONF_ENABLE) == 0) {
1559                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1560                         I915_READ(pipeconf_reg);
1561                         udelay(100);
1562                 }
1563
1564                 /* configure and enable CPU plane */
1565                 temp = I915_READ(dspcntr_reg);
1566                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1567                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1568                         /* Flush the plane changes */
1569                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1570                 }
1571
1572                 if (!HAS_eDP) {
1573                         /* enable CPU FDI TX and PCH FDI RX */
1574                         temp = I915_READ(fdi_tx_reg);
1575                         temp |= FDI_TX_ENABLE;
1576                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1577                         temp &= ~FDI_LINK_TRAIN_NONE;
1578                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1579                         I915_WRITE(fdi_tx_reg, temp);
1580                         I915_READ(fdi_tx_reg);
1581
1582                         temp = I915_READ(fdi_rx_reg);
1583                         temp &= ~FDI_LINK_TRAIN_NONE;
1584                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1585                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1586                         I915_READ(fdi_rx_reg);
1587
1588                         udelay(150);
1589
1590                         /* Train FDI. */
1591                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1592                            for train result */
1593                         temp = I915_READ(fdi_rx_imr_reg);
1594                         temp &= ~FDI_RX_SYMBOL_LOCK;
1595                         temp &= ~FDI_RX_BIT_LOCK;
1596                         I915_WRITE(fdi_rx_imr_reg, temp);
1597                         I915_READ(fdi_rx_imr_reg);
1598                         udelay(150);
1599
1600                         temp = I915_READ(fdi_rx_iir_reg);
1601                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1602
1603                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1604                                 for (j = 0; j < tries; j++) {
1605                                         temp = I915_READ(fdi_rx_iir_reg);
1606                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1607                                                                 temp);
1608                                         if (temp & FDI_RX_BIT_LOCK)
1609                                                 break;
1610                                         udelay(200);
1611                                 }
1612                                 if (j != tries)
1613                                         I915_WRITE(fdi_rx_iir_reg,
1614                                                         temp | FDI_RX_BIT_LOCK);
1615                                 else
1616                                         DRM_DEBUG_KMS("train 1 fail\n");
1617                         } else {
1618                                 I915_WRITE(fdi_rx_iir_reg,
1619                                                 temp | FDI_RX_BIT_LOCK);
1620                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1621                         }
1622                         temp = I915_READ(fdi_tx_reg);
1623                         temp &= ~FDI_LINK_TRAIN_NONE;
1624                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1625                         I915_WRITE(fdi_tx_reg, temp);
1626
1627                         temp = I915_READ(fdi_rx_reg);
1628                         temp &= ~FDI_LINK_TRAIN_NONE;
1629                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1630                         I915_WRITE(fdi_rx_reg, temp);
1631
1632                         udelay(150);
1633
1634                         temp = I915_READ(fdi_rx_iir_reg);
1635                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1636
1637                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1638                                 for (j = 0; j < tries; j++) {
1639                                         temp = I915_READ(fdi_rx_iir_reg);
1640                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1641                                                                 temp);
1642                                         if (temp & FDI_RX_SYMBOL_LOCK)
1643                                                 break;
1644                                         udelay(200);
1645                                 }
1646                                 if (j != tries) {
1647                                         I915_WRITE(fdi_rx_iir_reg,
1648                                                         temp | FDI_RX_SYMBOL_LOCK);
1649                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1650                                 } else
1651                                         DRM_DEBUG_KMS("train 2 fail\n");
1652                         } else {
1653                                 I915_WRITE(fdi_rx_iir_reg,
1654                                                 temp | FDI_RX_SYMBOL_LOCK);
1655                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1656                         }
1657                         DRM_DEBUG_KMS("train done\n");
1658
1659                         /* set transcoder timing */
1660                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1661                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1662                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1663
1664                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1665                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1666                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1667
1668                         /* enable PCH transcoder */
1669                         temp = I915_READ(transconf_reg);
1670                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1671                         I915_READ(transconf_reg);
1672
1673                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1674                                 ;
1675
1676                         /* enable normal */
1677
1678                         temp = I915_READ(fdi_tx_reg);
1679                         temp &= ~FDI_LINK_TRAIN_NONE;
1680                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1681                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1682                         I915_READ(fdi_tx_reg);
1683
1684                         temp = I915_READ(fdi_rx_reg);
1685                         temp &= ~FDI_LINK_TRAIN_NONE;
1686                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1687                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1688                         I915_READ(fdi_rx_reg);
1689
1690                         /* wait one idle pattern time */
1691                         udelay(100);
1692
1693                 }
1694
1695                 intel_crtc_load_lut(crtc);
1696
1697         break;
1698         case DRM_MODE_DPMS_OFF:
1699                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1700
1701                 /* Disable display plane */
1702                 temp = I915_READ(dspcntr_reg);
1703                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1704                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1705                         /* Flush the plane changes */
1706                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1707                         I915_READ(dspbase_reg);
1708                 }
1709
1710                 i915_disable_vga(dev);
1711
1712                 /* disable cpu pipe, disable after all planes disabled */
1713                 temp = I915_READ(pipeconf_reg);
1714                 if ((temp & PIPEACONF_ENABLE) != 0) {
1715                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1716                         I915_READ(pipeconf_reg);
1717                         n = 0;
1718                         /* wait for cpu pipe off, pipe state */
1719                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1720                                 n++;
1721                                 if (n < 60) {
1722                                         udelay(500);
1723                                         continue;
1724                                 } else {
1725                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1726                                                                 pipe);
1727                                         break;
1728                                 }
1729                         }
1730                 } else
1731                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1732
1733                 udelay(100);
1734
1735                 /* Disable PF */
1736                 temp = I915_READ(pf_ctl_reg);
1737                 if ((temp & PF_ENABLE) != 0) {
1738                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1739                         I915_READ(pf_ctl_reg);
1740                 }
1741                 I915_WRITE(pf_win_size, 0);
1742
1743                 /* disable CPU FDI tx and PCH FDI rx */
1744                 temp = I915_READ(fdi_tx_reg);
1745                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1746                 I915_READ(fdi_tx_reg);
1747
1748                 temp = I915_READ(fdi_rx_reg);
1749                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1750                 I915_READ(fdi_rx_reg);
1751
1752                 udelay(100);
1753
1754                 /* still set train pattern 1 */
1755                 temp = I915_READ(fdi_tx_reg);
1756                 temp &= ~FDI_LINK_TRAIN_NONE;
1757                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1758                 I915_WRITE(fdi_tx_reg, temp);
1759
1760                 temp = I915_READ(fdi_rx_reg);
1761                 temp &= ~FDI_LINK_TRAIN_NONE;
1762                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1763                 I915_WRITE(fdi_rx_reg, temp);
1764
1765                 udelay(100);
1766
1767                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1768                         temp = I915_READ(PCH_LVDS);
1769                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1770                         I915_READ(PCH_LVDS);
1771                         udelay(100);
1772                 }
1773
1774                 /* disable PCH transcoder */
1775                 temp = I915_READ(transconf_reg);
1776                 if ((temp & TRANS_ENABLE) != 0) {
1777                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1778                         I915_READ(transconf_reg);
1779                         n = 0;
1780                         /* wait for PCH transcoder off, transcoder state */
1781                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1782                                 n++;
1783                                 if (n < 60) {
1784                                         udelay(500);
1785                                         continue;
1786                                 } else {
1787                                         DRM_DEBUG_KMS("transcoder %d off "
1788                                                         "delay\n", pipe);
1789                                         break;
1790                                 }
1791                         }
1792                 }
1793
1794                 udelay(100);
1795
1796                 /* disable PCH DPLL */
1797                 temp = I915_READ(pch_dpll_reg);
1798                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1799                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1800                         I915_READ(pch_dpll_reg);
1801                 }
1802
1803                 if (HAS_eDP) {
1804                         igdng_disable_pll_edp(crtc);
1805                 }
1806
1807                 temp = I915_READ(fdi_rx_reg);
1808                 temp &= ~FDI_SEL_PCDCLK;
1809                 I915_WRITE(fdi_rx_reg, temp);
1810                 I915_READ(fdi_rx_reg);
1811
1812                 temp = I915_READ(fdi_rx_reg);
1813                 temp &= ~FDI_RX_PLL_ENABLE;
1814                 I915_WRITE(fdi_rx_reg, temp);
1815                 I915_READ(fdi_rx_reg);
1816
1817                 /* Disable CPU FDI TX PLL */
1818                 temp = I915_READ(fdi_tx_reg);
1819                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1820                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1821                         I915_READ(fdi_tx_reg);
1822                         udelay(100);
1823                 }
1824
1825                 /* Wait for the clocks to turn off. */
1826                 udelay(100);
1827                 break;
1828         }
1829 }
1830
1831 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1832 {
1833         struct intel_overlay *overlay;
1834         int ret;
1835
1836         if (!enable && intel_crtc->overlay) {
1837                 overlay = intel_crtc->overlay;
1838                 mutex_lock(&overlay->dev->struct_mutex);
1839                 for (;;) {
1840                         ret = intel_overlay_switch_off(overlay);
1841                         if (ret == 0)
1842                                 break;
1843
1844                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1845                         if (ret != 0) {
1846                                 /* overlay doesn't react anymore. Usually
1847                                  * results in a black screen and an unkillable
1848                                  * X server. */
1849                                 BUG();
1850                                 overlay->hw_wedged = HW_WEDGED;
1851                                 break;
1852                         }
1853                 }
1854                 mutex_unlock(&overlay->dev->struct_mutex);
1855         }
1856         /* Let userspace switch the overlay on again. In most cases userspace
1857          * has to recompute where to put it anyway. */
1858
1859         return;
1860 }
1861
1862 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1863 {
1864         struct drm_device *dev = crtc->dev;
1865         struct drm_i915_private *dev_priv = dev->dev_private;
1866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867         int pipe = intel_crtc->pipe;
1868         int plane = intel_crtc->plane;
1869         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1870         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1871         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1872         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1873         u32 temp;
1874
1875         /* XXX: When our outputs are all unaware of DPMS modes other than off
1876          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1877          */
1878         switch (mode) {
1879         case DRM_MODE_DPMS_ON:
1880         case DRM_MODE_DPMS_STANDBY:
1881         case DRM_MODE_DPMS_SUSPEND:
1882                 intel_update_watermarks(dev);
1883
1884                 /* Enable the DPLL */
1885                 temp = I915_READ(dpll_reg);
1886                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1887                         I915_WRITE(dpll_reg, temp);
1888                         I915_READ(dpll_reg);
1889                         /* Wait for the clocks to stabilize. */
1890                         udelay(150);
1891                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1892                         I915_READ(dpll_reg);
1893                         /* Wait for the clocks to stabilize. */
1894                         udelay(150);
1895                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1896                         I915_READ(dpll_reg);
1897                         /* Wait for the clocks to stabilize. */
1898                         udelay(150);
1899                 }
1900
1901                 /* Enable the pipe */
1902                 temp = I915_READ(pipeconf_reg);
1903                 if ((temp & PIPEACONF_ENABLE) == 0)
1904                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1905
1906                 /* Enable the plane */
1907                 temp = I915_READ(dspcntr_reg);
1908                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1909                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1910                         /* Flush the plane changes */
1911                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1912                 }
1913
1914                 intel_crtc_load_lut(crtc);
1915
1916                 if ((IS_I965G(dev) || plane == 0))
1917                         intel_update_fbc(crtc, &crtc->mode);
1918
1919                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1920                 intel_crtc_dpms_overlay(intel_crtc, true);
1921         break;
1922         case DRM_MODE_DPMS_OFF:
1923                 intel_update_watermarks(dev);
1924
1925                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1926                 intel_crtc_dpms_overlay(intel_crtc, false);
1927
1928                 if (dev_priv->cfb_plane == plane &&
1929                     dev_priv->display.disable_fbc)
1930                         dev_priv->display.disable_fbc(dev);
1931
1932                 /* Disable the VGA plane that we never use */
1933                 i915_disable_vga(dev);
1934
1935                 /* Disable display plane */
1936                 temp = I915_READ(dspcntr_reg);
1937                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1938                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1939                         /* Flush the plane changes */
1940                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1941                         I915_READ(dspbase_reg);
1942                 }
1943
1944                 if (!IS_I9XX(dev)) {
1945                         /* Wait for vblank for the disable to take effect */
1946                         intel_wait_for_vblank(dev);
1947                 }
1948
1949                 /* Next, disable display pipes */
1950                 temp = I915_READ(pipeconf_reg);
1951                 if ((temp & PIPEACONF_ENABLE) != 0) {
1952                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1953                         I915_READ(pipeconf_reg);
1954                 }
1955
1956                 /* Wait for vblank for the disable to take effect. */
1957                 intel_wait_for_vblank(dev);
1958
1959                 temp = I915_READ(dpll_reg);
1960                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1961                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1962                         I915_READ(dpll_reg);
1963                 }
1964
1965                 /* Wait for the clocks to turn off. */
1966                 udelay(150);
1967                 break;
1968         }
1969 }
1970
1971 /**
1972  * Sets the power management mode of the pipe and plane.
1973  *
1974  * This code should probably grow support for turning the cursor off and back
1975  * on appropriately at the same time as we're turning the pipe off/on.
1976  */
1977 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1978 {
1979         struct drm_device *dev = crtc->dev;
1980         struct drm_i915_private *dev_priv = dev->dev_private;
1981         struct drm_i915_master_private *master_priv;
1982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983         int pipe = intel_crtc->pipe;
1984         bool enabled;
1985
1986         dev_priv->display.dpms(crtc, mode);
1987
1988         intel_crtc->dpms_mode = mode;
1989
1990         if (!dev->primary->master)
1991                 return;
1992
1993         master_priv = dev->primary->master->driver_priv;
1994         if (!master_priv->sarea_priv)
1995                 return;
1996
1997         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1998
1999         switch (pipe) {
2000         case 0:
2001                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2002                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2003                 break;
2004         case 1:
2005                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2006                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2007                 break;
2008         default:
2009                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2010                 break;
2011         }
2012 }
2013
2014 static void intel_crtc_prepare (struct drm_crtc *crtc)
2015 {
2016         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2017         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2018 }
2019
2020 static void intel_crtc_commit (struct drm_crtc *crtc)
2021 {
2022         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2023         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2024 }
2025
2026 void intel_encoder_prepare (struct drm_encoder *encoder)
2027 {
2028         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2029         /* lvds has its own version of prepare see intel_lvds_prepare */
2030         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2031 }
2032
2033 void intel_encoder_commit (struct drm_encoder *encoder)
2034 {
2035         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2036         /* lvds has its own version of commit see intel_lvds_commit */
2037         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2038 }
2039
2040 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2041                                   struct drm_display_mode *mode,
2042                                   struct drm_display_mode *adjusted_mode)
2043 {
2044         struct drm_device *dev = crtc->dev;
2045         if (IS_IGDNG(dev)) {
2046                 /* FDI link clock is fixed at 2.7G */
2047                 if (mode->clock * 3 > 27000 * 4)
2048                         return MODE_CLOCK_HIGH;
2049         }
2050         return true;
2051 }
2052
2053 static int i945_get_display_clock_speed(struct drm_device *dev)
2054 {
2055         return 400000;
2056 }
2057
2058 static int i915_get_display_clock_speed(struct drm_device *dev)
2059 {
2060         return 333000;
2061 }
2062
2063 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2064 {
2065         return 200000;
2066 }
2067
2068 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2069 {
2070         u16 gcfgc = 0;
2071
2072         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2073
2074         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2075                 return 133000;
2076         else {
2077                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2078                 case GC_DISPLAY_CLOCK_333_MHZ:
2079                         return 333000;
2080                 default:
2081                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2082                         return 190000;
2083                 }
2084         }
2085 }
2086
2087 static int i865_get_display_clock_speed(struct drm_device *dev)
2088 {
2089         return 266000;
2090 }
2091
2092 static int i855_get_display_clock_speed(struct drm_device *dev)
2093 {
2094         u16 hpllcc = 0;
2095         /* Assume that the hardware is in the high speed state.  This
2096          * should be the default.
2097          */
2098         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2099         case GC_CLOCK_133_200:
2100         case GC_CLOCK_100_200:
2101                 return 200000;
2102         case GC_CLOCK_166_250:
2103                 return 250000;
2104         case GC_CLOCK_100_133:
2105                 return 133000;
2106         }
2107
2108         /* Shouldn't happen */
2109         return 0;
2110 }
2111
2112 static int i830_get_display_clock_speed(struct drm_device *dev)
2113 {
2114         return 133000;
2115 }
2116
2117 /**
2118  * Return the pipe currently connected to the panel fitter,
2119  * or -1 if the panel fitter is not present or not in use
2120  */
2121 int intel_panel_fitter_pipe (struct drm_device *dev)
2122 {
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124         u32  pfit_control;
2125
2126         /* i830 doesn't have a panel fitter */
2127         if (IS_I830(dev))
2128                 return -1;
2129
2130         pfit_control = I915_READ(PFIT_CONTROL);
2131
2132         /* See if the panel fitter is in use */
2133         if ((pfit_control & PFIT_ENABLE) == 0)
2134                 return -1;
2135
2136         /* 965 can place panel fitter on either pipe */
2137         if (IS_I965G(dev))
2138                 return (pfit_control >> 29) & 0x3;
2139
2140         /* older chips can only use pipe 1 */
2141         return 1;
2142 }
2143
2144 struct fdi_m_n {
2145         u32        tu;
2146         u32        gmch_m;
2147         u32        gmch_n;
2148         u32        link_m;
2149         u32        link_n;
2150 };
2151
2152 static void
2153 fdi_reduce_ratio(u32 *num, u32 *den)
2154 {
2155         while (*num > 0xffffff || *den > 0xffffff) {
2156                 *num >>= 1;
2157                 *den >>= 1;
2158         }
2159 }
2160
2161 #define DATA_N 0x800000
2162 #define LINK_N 0x80000
2163
2164 static void
2165 igdng_compute_m_n(int bits_per_pixel, int nlanes,
2166                 int pixel_clock, int link_clock,
2167                 struct fdi_m_n *m_n)
2168 {
2169         u64 temp;
2170
2171         m_n->tu = 64; /* default size */
2172
2173         temp = (u64) DATA_N * pixel_clock;
2174         temp = div_u64(temp, link_clock);
2175         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2176         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2177         m_n->gmch_n = DATA_N;
2178         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2179
2180         temp = (u64) LINK_N * pixel_clock;
2181         m_n->link_m = div_u64(temp, link_clock);
2182         m_n->link_n = LINK_N;
2183         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2184 }
2185
2186
2187 struct intel_watermark_params {
2188         unsigned long fifo_size;
2189         unsigned long max_wm;
2190         unsigned long default_wm;
2191         unsigned long guard_size;
2192         unsigned long cacheline_size;
2193 };
2194
2195 /* IGD has different values for various configs */
2196 static struct intel_watermark_params igd_display_wm = {
2197         IGD_DISPLAY_FIFO,
2198         IGD_MAX_WM,
2199         IGD_DFT_WM,
2200         IGD_GUARD_WM,
2201         IGD_FIFO_LINE_SIZE
2202 };
2203 static struct intel_watermark_params igd_display_hplloff_wm = {
2204         IGD_DISPLAY_FIFO,
2205         IGD_MAX_WM,
2206         IGD_DFT_HPLLOFF_WM,
2207         IGD_GUARD_WM,
2208         IGD_FIFO_LINE_SIZE
2209 };
2210 static struct intel_watermark_params igd_cursor_wm = {
2211         IGD_CURSOR_FIFO,
2212         IGD_CURSOR_MAX_WM,
2213         IGD_CURSOR_DFT_WM,
2214         IGD_CURSOR_GUARD_WM,
2215         IGD_FIFO_LINE_SIZE,
2216 };
2217 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2218         IGD_CURSOR_FIFO,
2219         IGD_CURSOR_MAX_WM,
2220         IGD_CURSOR_DFT_WM,
2221         IGD_CURSOR_GUARD_WM,
2222         IGD_FIFO_LINE_SIZE
2223 };
2224 static struct intel_watermark_params g4x_wm_info = {
2225         G4X_FIFO_SIZE,
2226         G4X_MAX_WM,
2227         G4X_MAX_WM,
2228         2,
2229         G4X_FIFO_LINE_SIZE,
2230 };
2231 static struct intel_watermark_params i945_wm_info = {
2232         I945_FIFO_SIZE,
2233         I915_MAX_WM,
2234         1,
2235         2,
2236         I915_FIFO_LINE_SIZE
2237 };
2238 static struct intel_watermark_params i915_wm_info = {
2239         I915_FIFO_SIZE,
2240         I915_MAX_WM,
2241         1,
2242         2,
2243         I915_FIFO_LINE_SIZE
2244 };
2245 static struct intel_watermark_params i855_wm_info = {
2246         I855GM_FIFO_SIZE,
2247         I915_MAX_WM,
2248         1,
2249         2,
2250         I830_FIFO_LINE_SIZE
2251 };
2252 static struct intel_watermark_params i830_wm_info = {
2253         I830_FIFO_SIZE,
2254         I915_MAX_WM,
2255         1,
2256         2,
2257         I830_FIFO_LINE_SIZE
2258 };
2259
2260 /**
2261  * intel_calculate_wm - calculate watermark level
2262  * @clock_in_khz: pixel clock
2263  * @wm: chip FIFO params
2264  * @pixel_size: display pixel size
2265  * @latency_ns: memory latency for the platform
2266  *
2267  * Calculate the watermark level (the level at which the display plane will
2268  * start fetching from memory again).  Each chip has a different display
2269  * FIFO size and allocation, so the caller needs to figure that out and pass
2270  * in the correct intel_watermark_params structure.
2271  *
2272  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2273  * on the pixel size.  When it reaches the watermark level, it'll start
2274  * fetching FIFO line sized based chunks from memory until the FIFO fills
2275  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2276  * will occur, and a display engine hang could result.
2277  */
2278 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2279                                         struct intel_watermark_params *wm,
2280                                         int pixel_size,
2281                                         unsigned long latency_ns)
2282 {
2283         long entries_required, wm_size;
2284
2285         /*
2286          * Note: we need to make sure we don't overflow for various clock &
2287          * latency values.
2288          * clocks go from a few thousand to several hundred thousand.
2289          * latency is usually a few thousand
2290          */
2291         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2292                 1000;
2293         entries_required /= wm->cacheline_size;
2294
2295         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2296
2297         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2298
2299         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2300
2301         /* Don't promote wm_size to unsigned... */
2302         if (wm_size > (long)wm->max_wm)
2303                 wm_size = wm->max_wm;
2304         if (wm_size <= 0)
2305                 wm_size = wm->default_wm;
2306         return wm_size;
2307 }
2308
2309 struct cxsr_latency {
2310         int is_desktop;
2311         unsigned long fsb_freq;
2312         unsigned long mem_freq;
2313         unsigned long display_sr;
2314         unsigned long display_hpll_disable;
2315         unsigned long cursor_sr;
2316         unsigned long cursor_hpll_disable;
2317 };
2318
2319 static struct cxsr_latency cxsr_latency_table[] = {
2320         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2321         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2322         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2323
2324         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2325         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2326         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2327
2328         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2329         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2330         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2331
2332         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2333         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2334         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2335
2336         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2337         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2338         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2339
2340         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2341         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2342         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2343 };
2344
2345 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2346                                                    int mem)
2347 {
2348         int i;
2349         struct cxsr_latency *latency;
2350
2351         if (fsb == 0 || mem == 0)
2352                 return NULL;
2353
2354         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2355                 latency = &cxsr_latency_table[i];
2356                 if (is_desktop == latency->is_desktop &&
2357                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2358                         return latency;
2359         }
2360
2361         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2362
2363         return NULL;
2364 }
2365
2366 static void igd_disable_cxsr(struct drm_device *dev)
2367 {
2368         struct drm_i915_private *dev_priv = dev->dev_private;
2369         u32 reg;
2370
2371         /* deactivate cxsr */
2372         reg = I915_READ(DSPFW3);
2373         reg &= ~(IGD_SELF_REFRESH_EN);
2374         I915_WRITE(DSPFW3, reg);
2375         DRM_INFO("Big FIFO is disabled\n");
2376 }
2377
2378 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2379                             int pixel_size)
2380 {
2381         struct drm_i915_private *dev_priv = dev->dev_private;
2382         u32 reg;
2383         unsigned long wm;
2384         struct cxsr_latency *latency;
2385
2386         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2387                 dev_priv->mem_freq);
2388         if (!latency) {
2389                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2390                 igd_disable_cxsr(dev);
2391                 return;
2392         }
2393
2394         /* Display SR */
2395         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2396                                 latency->display_sr);
2397         reg = I915_READ(DSPFW1);
2398         reg &= 0x7fffff;
2399         reg |= wm << 23;
2400         I915_WRITE(DSPFW1, reg);
2401         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2402
2403         /* cursor SR */
2404         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2405                                 latency->cursor_sr);
2406         reg = I915_READ(DSPFW3);
2407         reg &= ~(0x3f << 24);
2408         reg |= (wm & 0x3f) << 24;
2409         I915_WRITE(DSPFW3, reg);
2410
2411         /* Display HPLL off SR */
2412         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2413                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2414         reg = I915_READ(DSPFW3);
2415         reg &= 0xfffffe00;
2416         reg |= wm & 0x1ff;
2417         I915_WRITE(DSPFW3, reg);
2418
2419         /* cursor HPLL off SR */
2420         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2421                                 latency->cursor_hpll_disable);
2422         reg = I915_READ(DSPFW3);
2423         reg &= ~(0x3f << 16);
2424         reg |= (wm & 0x3f) << 16;
2425         I915_WRITE(DSPFW3, reg);
2426         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2427
2428         /* activate cxsr */
2429         reg = I915_READ(DSPFW3);
2430         reg |= IGD_SELF_REFRESH_EN;
2431         I915_WRITE(DSPFW3, reg);
2432
2433         DRM_INFO("Big FIFO is enabled\n");
2434
2435         return;
2436 }
2437
2438 /*
2439  * Latency for FIFO fetches is dependent on several factors:
2440  *   - memory configuration (speed, channels)
2441  *   - chipset
2442  *   - current MCH state
2443  * It can be fairly high in some situations, so here we assume a fairly
2444  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2445  * set this value too high, the FIFO will fetch frequently to stay full)
2446  * and power consumption (set it too low to save power and we might see
2447  * FIFO underruns and display "flicker").
2448  *
2449  * A value of 5us seems to be a good balance; safe for very low end
2450  * platforms but not overly aggressive on lower latency configs.
2451  */
2452 const static int latency_ns = 5000;
2453
2454 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2455 {
2456         struct drm_i915_private *dev_priv = dev->dev_private;
2457         uint32_t dsparb = I915_READ(DSPARB);
2458         int size;
2459
2460         if (plane == 0)
2461                 size = dsparb & 0x7f;
2462         else
2463                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2464                         (dsparb & 0x7f);
2465
2466         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2467                         plane ? "B" : "A", size);
2468
2469         return size;
2470 }
2471
2472 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2473 {
2474         struct drm_i915_private *dev_priv = dev->dev_private;
2475         uint32_t dsparb = I915_READ(DSPARB);
2476         int size;
2477
2478         if (plane == 0)
2479                 size = dsparb & 0x1ff;
2480         else
2481                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2482                         (dsparb & 0x1ff);
2483         size >>= 1; /* Convert to cachelines */
2484
2485         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2486                         plane ? "B" : "A", size);
2487
2488         return size;
2489 }
2490
2491 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2492 {
2493         struct drm_i915_private *dev_priv = dev->dev_private;
2494         uint32_t dsparb = I915_READ(DSPARB);
2495         int size;
2496
2497         size = dsparb & 0x7f;
2498         size >>= 2; /* Convert to cachelines */
2499
2500         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2501                         plane ? "B" : "A",
2502                   size);
2503
2504         return size;
2505 }
2506
2507 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2508 {
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         uint32_t dsparb = I915_READ(DSPARB);
2511         int size;
2512
2513         size = dsparb & 0x7f;
2514         size >>= 1; /* Convert to cachelines */
2515
2516         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2517                         plane ? "B" : "A", size);
2518
2519         return size;
2520 }
2521
2522 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2523                           int planeb_clock, int sr_hdisplay, int pixel_size)
2524 {
2525         struct drm_i915_private *dev_priv = dev->dev_private;
2526         int total_size, cacheline_size;
2527         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2528         struct intel_watermark_params planea_params, planeb_params;
2529         unsigned long line_time_us;
2530         int sr_clock, sr_entries = 0, entries_required;
2531
2532         /* Create copies of the base settings for each pipe */
2533         planea_params = planeb_params = g4x_wm_info;
2534
2535         /* Grab a couple of global values before we overwrite them */
2536         total_size = planea_params.fifo_size;
2537         cacheline_size = planea_params.cacheline_size;
2538
2539         /*
2540          * Note: we need to make sure we don't overflow for various clock &
2541          * latency values.
2542          * clocks go from a few thousand to several hundred thousand.
2543          * latency is usually a few thousand
2544          */
2545         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2546                 1000;
2547         entries_required /= G4X_FIFO_LINE_SIZE;
2548         planea_wm = entries_required + planea_params.guard_size;
2549
2550         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2551                 1000;
2552         entries_required /= G4X_FIFO_LINE_SIZE;
2553         planeb_wm = entries_required + planeb_params.guard_size;
2554
2555         cursora_wm = cursorb_wm = 16;
2556         cursor_sr = 32;
2557
2558         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2559
2560         /* Calc sr entries for one plane configs */
2561         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2562                 /* self-refresh has much higher latency */
2563                 const static int sr_latency_ns = 12000;
2564
2565                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2566                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2567
2568                 /* Use ns/us then divide to preserve precision */
2569                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2570                               pixel_size * sr_hdisplay) / 1000;
2571                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2572                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2573                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2574         }
2575
2576         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2577                   planea_wm, planeb_wm, sr_entries);
2578
2579         planea_wm &= 0x3f;
2580         planeb_wm &= 0x3f;
2581
2582         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2583                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2584                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2585         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2586                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2587         /* HPLL off in SR has some issues on G4x... disable it */
2588         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2589                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2590 }
2591
2592 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2593                            int planeb_clock, int sr_hdisplay, int pixel_size)
2594 {
2595         struct drm_i915_private *dev_priv = dev->dev_private;
2596         unsigned long line_time_us;
2597         int sr_clock, sr_entries, srwm = 1;
2598
2599         /* Calc sr entries for one plane configs */
2600         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2601                 /* self-refresh has much higher latency */
2602                 const static int sr_latency_ns = 12000;
2603
2604                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2605                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2606
2607                 /* Use ns/us then divide to preserve precision */
2608                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2609                               pixel_size * sr_hdisplay) / 1000;
2610                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2611                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2612                 srwm = I945_FIFO_SIZE - sr_entries;
2613                 if (srwm < 0)
2614                         srwm = 1;
2615                 srwm &= 0x3f;
2616                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2617         }
2618
2619         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2620                       srwm);
2621
2622         /* 965 has limitations... */
2623         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2624                    (8 << 0));
2625         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2626 }
2627
2628 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2629                            int planeb_clock, int sr_hdisplay, int pixel_size)
2630 {
2631         struct drm_i915_private *dev_priv = dev->dev_private;
2632         uint32_t fwater_lo;
2633         uint32_t fwater_hi;
2634         int total_size, cacheline_size, cwm, srwm = 1;
2635         int planea_wm, planeb_wm;
2636         struct intel_watermark_params planea_params, planeb_params;
2637         unsigned long line_time_us;
2638         int sr_clock, sr_entries = 0;
2639
2640         /* Create copies of the base settings for each pipe */
2641         if (IS_I965GM(dev) || IS_I945GM(dev))
2642                 planea_params = planeb_params = i945_wm_info;
2643         else if (IS_I9XX(dev))
2644                 planea_params = planeb_params = i915_wm_info;
2645         else
2646                 planea_params = planeb_params = i855_wm_info;
2647
2648         /* Grab a couple of global values before we overwrite them */
2649         total_size = planea_params.fifo_size;
2650         cacheline_size = planea_params.cacheline_size;
2651
2652         /* Update per-plane FIFO sizes */
2653         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2654         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2655
2656         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2657                                        pixel_size, latency_ns);
2658         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2659                                        pixel_size, latency_ns);
2660         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2661
2662         /*
2663          * Overlay gets an aggressive default since video jitter is bad.
2664          */
2665         cwm = 2;
2666
2667         /* Calc sr entries for one plane configs */
2668         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2669             (!planea_clock || !planeb_clock)) {
2670                 /* self-refresh has much higher latency */
2671                 const static int sr_latency_ns = 6000;
2672
2673                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2674                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2675
2676                 /* Use ns/us then divide to preserve precision */
2677                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2678                               pixel_size * sr_hdisplay) / 1000;
2679                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2680                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2681                 srwm = total_size - sr_entries;
2682                 if (srwm < 0)
2683                         srwm = 1;
2684                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2685         }
2686
2687         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2688                   planea_wm, planeb_wm, cwm, srwm);
2689
2690         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2691         fwater_hi = (cwm & 0x1f);
2692
2693         /* Set request length to 8 cachelines per fetch */
2694         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2695         fwater_hi = fwater_hi | (1 << 8);
2696
2697         I915_WRITE(FW_BLC, fwater_lo);
2698         I915_WRITE(FW_BLC2, fwater_hi);
2699 }
2700
2701 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2702                            int unused2, int pixel_size)
2703 {
2704         struct drm_i915_private *dev_priv = dev->dev_private;
2705         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2706         int planea_wm;
2707
2708         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2709
2710         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2711                                        pixel_size, latency_ns);
2712         fwater_lo |= (3<<8) | planea_wm;
2713
2714         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2715
2716         I915_WRITE(FW_BLC, fwater_lo);
2717 }
2718
2719 /**
2720  * intel_update_watermarks - update FIFO watermark values based on current modes
2721  *
2722  * Calculate watermark values for the various WM regs based on current mode
2723  * and plane configuration.
2724  *
2725  * There are several cases to deal with here:
2726  *   - normal (i.e. non-self-refresh)
2727  *   - self-refresh (SR) mode
2728  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2729  *   - lines are small relative to FIFO size (buffer can hold more than 2
2730  *     lines), so need to account for TLB latency
2731  *
2732  *   The normal calculation is:
2733  *     watermark = dotclock * bytes per pixel * latency
2734  *   where latency is platform & configuration dependent (we assume pessimal
2735  *   values here).
2736  *
2737  *   The SR calculation is:
2738  *     watermark = (trunc(latency/line time)+1) * surface width *
2739  *       bytes per pixel
2740  *   where
2741  *     line time = htotal / dotclock
2742  *   and latency is assumed to be high, as above.
2743  *
2744  * The final value programmed to the register should always be rounded up,
2745  * and include an extra 2 entries to account for clock crossings.
2746  *
2747  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2748  * to set the non-SR watermarks to 8.
2749   */
2750 static void intel_update_watermarks(struct drm_device *dev)
2751 {
2752         struct drm_i915_private *dev_priv = dev->dev_private;
2753         struct drm_crtc *crtc;
2754         struct intel_crtc *intel_crtc;
2755         int sr_hdisplay = 0;
2756         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2757         int enabled = 0, pixel_size = 0;
2758
2759         if (!dev_priv->display.update_wm)
2760                 return;
2761
2762         /* Get the clock config from both planes */
2763         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2764                 intel_crtc = to_intel_crtc(crtc);
2765                 if (crtc->enabled) {
2766                         enabled++;
2767                         if (intel_crtc->plane == 0) {
2768                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2769                                           intel_crtc->pipe, crtc->mode.clock);
2770                                 planea_clock = crtc->mode.clock;
2771                         } else {
2772                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2773                                           intel_crtc->pipe, crtc->mode.clock);
2774                                 planeb_clock = crtc->mode.clock;
2775                         }
2776                         sr_hdisplay = crtc->mode.hdisplay;
2777                         sr_clock = crtc->mode.clock;
2778                         if (crtc->fb)
2779                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2780                         else
2781                                 pixel_size = 4; /* by default */
2782                 }
2783         }
2784
2785         if (enabled <= 0)
2786                 return;
2787
2788         /* Single plane configs can enable self refresh */
2789         if (enabled == 1 && IS_IGD(dev))
2790                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2791         else if (IS_IGD(dev))
2792                 igd_disable_cxsr(dev);
2793
2794         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2795                                     sr_hdisplay, pixel_size);
2796 }
2797
2798 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2799                                struct drm_display_mode *mode,
2800                                struct drm_display_mode *adjusted_mode,
2801                                int x, int y,
2802                                struct drm_framebuffer *old_fb)
2803 {
2804         struct drm_device *dev = crtc->dev;
2805         struct drm_i915_private *dev_priv = dev->dev_private;
2806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2807         int pipe = intel_crtc->pipe;
2808         int plane = intel_crtc->plane;
2809         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2810         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2811         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2812         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2813         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2814         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2815         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2816         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2817         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2818         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2819         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2820         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2821         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2822         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2823         int refclk, num_outputs = 0;
2824         intel_clock_t clock, reduced_clock;
2825         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2826         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2827         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2828         bool is_edp = false;
2829         struct drm_mode_config *mode_config = &dev->mode_config;
2830         struct drm_connector *connector;
2831         const intel_limit_t *limit;
2832         int ret;
2833         struct fdi_m_n m_n = {0};
2834         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2835         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2836         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2837         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2838         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2839         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2840         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2841         int lvds_reg = LVDS;
2842         u32 temp;
2843         int sdvo_pixel_multiply;
2844         int target_clock;
2845
2846         drm_vblank_pre_modeset(dev, pipe);
2847
2848         list_for_each_entry(connector, &mode_config->connector_list, head) {
2849                 struct intel_output *intel_output = to_intel_output(connector);
2850
2851                 if (!connector->encoder || connector->encoder->crtc != crtc)
2852                         continue;
2853
2854                 switch (intel_output->type) {
2855                 case INTEL_OUTPUT_LVDS:
2856                         is_lvds = true;
2857                         break;
2858                 case INTEL_OUTPUT_SDVO:
2859                 case INTEL_OUTPUT_HDMI:
2860                         is_sdvo = true;
2861                         if (intel_output->needs_tv_clock)
2862                                 is_tv = true;
2863                         break;
2864                 case INTEL_OUTPUT_DVO:
2865                         is_dvo = true;
2866                         break;
2867                 case INTEL_OUTPUT_TVOUT:
2868                         is_tv = true;
2869                         break;
2870                 case INTEL_OUTPUT_ANALOG:
2871                         is_crt = true;
2872                         break;
2873                 case INTEL_OUTPUT_DISPLAYPORT:
2874                         is_dp = true;
2875                         break;
2876                 case INTEL_OUTPUT_EDP:
2877                         is_edp = true;
2878                         break;
2879                 }
2880
2881                 num_outputs++;
2882         }
2883
2884         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2885                 refclk = dev_priv->lvds_ssc_freq * 1000;
2886                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2887                                         refclk / 1000);
2888         } else if (IS_I9XX(dev)) {
2889                 refclk = 96000;
2890                 if (IS_IGDNG(dev))
2891                         refclk = 120000; /* 120Mhz refclk */
2892         } else {
2893                 refclk = 48000;
2894         }
2895
2896
2897         /*
2898          * Returns a set of divisors for the desired target clock with the given
2899          * refclk, or FALSE.  The returned values represent the clock equation:
2900          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2901          */
2902         limit = intel_limit(crtc);
2903         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2904         if (!ok) {
2905                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2906                 drm_vblank_post_modeset(dev, pipe);
2907                 return -EINVAL;
2908         }
2909
2910         if (is_lvds && limit->find_reduced_pll &&
2911                         dev_priv->lvds_downclock_avail) {
2912                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2913                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2914                                                             dev_priv->lvds_downclock,
2915                                                             refclk,
2916                                                             &reduced_clock);
2917                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2918                         /*
2919                          * If the different P is found, it means that we can't
2920                          * switch the display clock by using the FP0/FP1.
2921                          * In such case we will disable the LVDS downclock
2922                          * feature.
2923                          */
2924                         DRM_DEBUG_KMS("Different P is found for "
2925                                                 "LVDS clock/downclock\n");
2926                         has_reduced_clock = 0;
2927                 }
2928         }
2929         /* SDVO TV has fixed PLL values depend on its clock range,
2930            this mirrors vbios setting. */
2931         if (is_sdvo && is_tv) {
2932                 if (adjusted_mode->clock >= 100000
2933                                 && adjusted_mode->clock < 140500) {
2934                         clock.p1 = 2;
2935                         clock.p2 = 10;
2936                         clock.n = 3;
2937                         clock.m1 = 16;
2938                         clock.m2 = 8;
2939                 } else if (adjusted_mode->clock >= 140500
2940                                 && adjusted_mode->clock <= 200000) {
2941                         clock.p1 = 1;
2942                         clock.p2 = 10;
2943                         clock.n = 6;
2944                         clock.m1 = 12;
2945                         clock.m2 = 8;
2946                 }
2947         }
2948
2949         /* FDI link */
2950         if (IS_IGDNG(dev)) {
2951                 int lane, link_bw, bpp;
2952                 /* eDP doesn't require FDI link, so just set DP M/N
2953                    according to current link config */
2954                 if (is_edp) {
2955                         struct drm_connector *edp;
2956                         target_clock = mode->clock;
2957                         edp = intel_pipe_get_output(crtc);
2958                         intel_edp_link_config(to_intel_output(edp),
2959                                         &lane, &link_bw);
2960                 } else {
2961                         /* DP over FDI requires target mode clock
2962                            instead of link clock */
2963                         if (is_dp)
2964                                 target_clock = mode->clock;
2965                         else
2966                                 target_clock = adjusted_mode->clock;
2967                         lane = 4;
2968                         link_bw = 270000;
2969                 }
2970
2971                 /* determine panel color depth */
2972                 temp = I915_READ(pipeconf_reg);
2973
2974                 switch (temp & PIPE_BPC_MASK) {
2975                 case PIPE_8BPC:
2976                         bpp = 24;
2977                         break;
2978                 case PIPE_10BPC:
2979                         bpp = 30;
2980                         break;
2981                 case PIPE_6BPC:
2982                         bpp = 18;
2983                         break;
2984                 case PIPE_12BPC:
2985                         bpp = 36;
2986                         break;
2987                 default:
2988                         DRM_ERROR("unknown pipe bpc value\n");
2989                         bpp = 24;
2990                 }
2991
2992                 igdng_compute_m_n(bpp, lane, target_clock,
2993                                   link_bw, &m_n);
2994         }
2995
2996         /* Ironlake: try to setup display ref clock before DPLL
2997          * enabling. This is only under driver's control after
2998          * PCH B stepping, previous chipset stepping should be
2999          * ignoring this setting.
3000          */
3001         if (IS_IGDNG(dev)) {
3002                 temp = I915_READ(PCH_DREF_CONTROL);
3003                 /* Always enable nonspread source */
3004                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3005                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3006                 I915_WRITE(PCH_DREF_CONTROL, temp);
3007                 POSTING_READ(PCH_DREF_CONTROL);
3008
3009                 temp &= ~DREF_SSC_SOURCE_MASK;
3010                 temp |= DREF_SSC_SOURCE_ENABLE;
3011                 I915_WRITE(PCH_DREF_CONTROL, temp);
3012                 POSTING_READ(PCH_DREF_CONTROL);
3013
3014                 udelay(200);
3015
3016                 if (is_edp) {
3017                         if (dev_priv->lvds_use_ssc) {
3018                                 temp |= DREF_SSC1_ENABLE;
3019                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3020                                 POSTING_READ(PCH_DREF_CONTROL);
3021
3022                                 udelay(200);
3023
3024                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3025                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3026                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3027                                 POSTING_READ(PCH_DREF_CONTROL);
3028                         } else {
3029                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3030                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3031                                 POSTING_READ(PCH_DREF_CONTROL);
3032                         }
3033                 }
3034         }
3035
3036         if (IS_IGD(dev)) {
3037                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3038                 if (has_reduced_clock)
3039                         fp2 = (1 << reduced_clock.n) << 16 |
3040                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3041         } else {
3042                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3043                 if (has_reduced_clock)
3044                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3045                                 reduced_clock.m2;
3046         }
3047
3048         if (!IS_IGDNG(dev))
3049                 dpll = DPLL_VGA_MODE_DIS;
3050
3051         if (IS_I9XX(dev)) {
3052                 if (is_lvds)
3053                         dpll |= DPLLB_MODE_LVDS;
3054                 else
3055                         dpll |= DPLLB_MODE_DAC_SERIAL;
3056                 if (is_sdvo) {
3057                         dpll |= DPLL_DVO_HIGH_SPEED;
3058                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3059                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3060                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3061                         else if (IS_IGDNG(dev))
3062                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3063                 }
3064                 if (is_dp)
3065                         dpll |= DPLL_DVO_HIGH_SPEED;
3066
3067                 /* compute bitmask from p1 value */
3068                 if (IS_IGD(dev))
3069                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
3070                 else {
3071                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3072                         /* also FPA1 */
3073                         if (IS_IGDNG(dev))
3074                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3075                         if (IS_G4X(dev) && has_reduced_clock)
3076                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3077                 }
3078                 switch (clock.p2) {
3079                 case 5:
3080                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3081                         break;
3082                 case 7:
3083                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3084                         break;
3085                 case 10:
3086                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3087                         break;
3088                 case 14:
3089                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3090                         break;
3091                 }
3092                 if (IS_I965G(dev) && !IS_IGDNG(dev))
3093                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3094         } else {
3095                 if (is_lvds) {
3096                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3097                 } else {
3098                         if (clock.p1 == 2)
3099                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3100                         else
3101                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3102                         if (clock.p2 == 4)
3103                                 dpll |= PLL_P2_DIVIDE_BY_4;
3104                 }
3105         }
3106
3107         if (is_sdvo && is_tv)
3108                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3109         else if (is_tv)
3110                 /* XXX: just matching BIOS for now */
3111                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3112                 dpll |= 3;
3113         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3114                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3115         else
3116                 dpll |= PLL_REF_INPUT_DREFCLK;
3117
3118         /* setup pipeconf */
3119         pipeconf = I915_READ(pipeconf_reg);
3120
3121         /* Set up the display plane register */
3122         dspcntr = DISPPLANE_GAMMA_ENABLE;
3123
3124         /* IGDNG's plane is forced to pipe, bit 24 is to
3125            enable color space conversion */
3126         if (!IS_IGDNG(dev)) {
3127                 if (pipe == 0)
3128                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3129                 else
3130                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3131         }
3132
3133         if (pipe == 0 && !IS_I965G(dev)) {
3134                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3135                  * core speed.
3136                  *
3137                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3138                  * pipe == 0 check?
3139                  */
3140                 if (mode->clock >
3141                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3142                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3143                 else
3144                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3145         }
3146
3147         dspcntr |= DISPLAY_PLANE_ENABLE;
3148         pipeconf |= PIPEACONF_ENABLE;
3149         dpll |= DPLL_VCO_ENABLE;
3150
3151
3152         /* Disable the panel fitter if it was on our pipe */
3153         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3154                 I915_WRITE(PFIT_CONTROL, 0);
3155
3156         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3157         drm_mode_debug_printmodeline(mode);
3158
3159         /* assign to IGDNG registers */
3160         if (IS_IGDNG(dev)) {
3161                 fp_reg = pch_fp_reg;
3162                 dpll_reg = pch_dpll_reg;
3163         }
3164
3165         if (is_edp) {
3166                 igdng_disable_pll_edp(crtc);
3167         } else if ((dpll & DPLL_VCO_ENABLE)) {
3168                 I915_WRITE(fp_reg, fp);
3169                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3170                 I915_READ(dpll_reg);
3171                 udelay(150);
3172         }
3173
3174         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3175          * This is an exception to the general rule that mode_set doesn't turn
3176          * things on.
3177          */
3178         if (is_lvds) {
3179                 u32 lvds;
3180
3181                 if (IS_IGDNG(dev))
3182                         lvds_reg = PCH_LVDS;
3183
3184                 lvds = I915_READ(lvds_reg);
3185                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3186                 /* set the corresponsding LVDS_BORDER bit */
3187                 lvds |= dev_priv->lvds_border_bits;
3188                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3189                  * set the DPLLs for dual-channel mode or not.
3190                  */
3191                 if (clock.p2 == 7)
3192                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3193                 else
3194                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3195
3196                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3197                  * appropriately here, but we need to look more thoroughly into how
3198                  * panels behave in the two modes.
3199                  */
3200
3201                 I915_WRITE(lvds_reg, lvds);
3202                 I915_READ(lvds_reg);
3203         }
3204         if (is_dp)
3205                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3206
3207         if (!is_edp) {
3208                 I915_WRITE(fp_reg, fp);
3209                 I915_WRITE(dpll_reg, dpll);
3210                 I915_READ(dpll_reg);
3211                 /* Wait for the clocks to stabilize. */
3212                 udelay(150);
3213
3214                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
3215                         if (is_sdvo) {
3216                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3217                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3218                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3219                         } else
3220                                 I915_WRITE(dpll_md_reg, 0);
3221                 } else {
3222                         /* write it again -- the BIOS does, after all */
3223                         I915_WRITE(dpll_reg, dpll);
3224                 }
3225                 I915_READ(dpll_reg);
3226                 /* Wait for the clocks to stabilize. */
3227                 udelay(150);
3228         }
3229
3230         if (is_lvds && has_reduced_clock && i915_powersave) {
3231                 I915_WRITE(fp_reg + 4, fp2);
3232                 intel_crtc->lowfreq_avail = true;
3233                 if (HAS_PIPE_CXSR(dev)) {
3234                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3235                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3236                 }
3237         } else {
3238                 I915_WRITE(fp_reg + 4, fp);
3239                 intel_crtc->lowfreq_avail = false;
3240                 if (HAS_PIPE_CXSR(dev)) {
3241                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3242                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3243                 }
3244         }
3245
3246         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3247                    ((adjusted_mode->crtc_htotal - 1) << 16));
3248         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3249                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3250         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3251                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3252         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3253                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3254         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3255                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3256         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3257                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3258         /* pipesrc and dspsize control the size that is scaled from, which should
3259          * always be the user's requested size.
3260          */
3261         if (!IS_IGDNG(dev)) {
3262                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3263                                 (mode->hdisplay - 1));
3264                 I915_WRITE(dsppos_reg, 0);
3265         }
3266         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3267
3268         if (IS_IGDNG(dev)) {
3269                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3270                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3271                 I915_WRITE(link_m1_reg, m_n.link_m);
3272                 I915_WRITE(link_n1_reg, m_n.link_n);
3273
3274                 if (is_edp) {
3275                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
3276                 } else {
3277                         /* enable FDI RX PLL too */
3278                         temp = I915_READ(fdi_rx_reg);
3279                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3280                         udelay(200);
3281                 }
3282         }
3283
3284         I915_WRITE(pipeconf_reg, pipeconf);
3285         I915_READ(pipeconf_reg);
3286
3287         intel_wait_for_vblank(dev);
3288
3289         if (IS_IGDNG(dev)) {
3290                 /* enable address swizzle for tiling buffer */
3291                 temp = I915_READ(DISP_ARB_CTL);
3292                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3293         }
3294
3295         I915_WRITE(dspcntr_reg, dspcntr);
3296
3297         /* Flush the plane changes */
3298         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3299
3300         if ((IS_I965G(dev) || plane == 0))
3301                 intel_update_fbc(crtc, &crtc->mode);
3302
3303         intel_update_watermarks(dev);
3304
3305         drm_vblank_post_modeset(dev, pipe);
3306
3307         return ret;
3308 }
3309
3310 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3311 void intel_crtc_load_lut(struct drm_crtc *crtc)
3312 {
3313         struct drm_device *dev = crtc->dev;
3314         struct drm_i915_private *dev_priv = dev->dev_private;
3315         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3316         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3317         int i;
3318
3319         /* The clocks have to be on to load the palette. */
3320         if (!crtc->enabled)
3321                 return;
3322
3323         /* use legacy palette for IGDNG */
3324         if (IS_IGDNG(dev))
3325                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3326                                                    LGC_PALETTE_B;
3327
3328         for (i = 0; i < 256; i++) {
3329                 I915_WRITE(palreg + 4 * i,
3330                            (intel_crtc->lut_r[i] << 16) |
3331                            (intel_crtc->lut_g[i] << 8) |
3332                            intel_crtc->lut_b[i]);
3333         }
3334 }
3335
3336 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3337                                  struct drm_file *file_priv,
3338                                  uint32_t handle,
3339                                  uint32_t width, uint32_t height)
3340 {
3341         struct drm_device *dev = crtc->dev;
3342         struct drm_i915_private *dev_priv = dev->dev_private;
3343         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3344         struct drm_gem_object *bo;
3345         struct drm_i915_gem_object *obj_priv;
3346         int pipe = intel_crtc->pipe;
3347         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3348         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3349         uint32_t temp = I915_READ(control);
3350         size_t addr;
3351         int ret;
3352
3353         DRM_DEBUG_KMS("\n");
3354
3355         /* if we want to turn off the cursor ignore width and height */
3356         if (!handle) {
3357                 DRM_DEBUG_KMS("cursor off\n");
3358                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3359                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3360                         temp |= CURSOR_MODE_DISABLE;
3361                 } else {
3362                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3363                 }
3364                 addr = 0;
3365                 bo = NULL;
3366                 mutex_lock(&dev->struct_mutex);
3367                 goto finish;
3368         }
3369
3370         /* Currently we only support 64x64 cursors */
3371         if (width != 64 || height != 64) {
3372                 DRM_ERROR("we currently only support 64x64 cursors\n");
3373                 return -EINVAL;
3374         }
3375
3376         bo = drm_gem_object_lookup(dev, file_priv, handle);
3377         if (!bo)
3378                 return -ENOENT;
3379
3380         obj_priv = bo->driver_private;
3381
3382         if (bo->size < width * height * 4) {
3383                 DRM_ERROR("buffer is to small\n");
3384                 ret = -ENOMEM;
3385                 goto fail;
3386         }
3387
3388         /* we only need to pin inside GTT if cursor is non-phy */
3389         mutex_lock(&dev->struct_mutex);
3390         if (!dev_priv->cursor_needs_physical) {
3391                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3392                 if (ret) {
3393                         DRM_ERROR("failed to pin cursor bo\n");
3394                         goto fail_locked;
3395                 }
3396                 addr = obj_priv->gtt_offset;
3397         } else {
3398                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3399                 if (ret) {
3400                         DRM_ERROR("failed to attach phys object\n");
3401                         goto fail_locked;
3402                 }
3403                 addr = obj_priv->phys_obj->handle->busaddr;
3404         }
3405
3406         if (!IS_I9XX(dev))
3407                 I915_WRITE(CURSIZE, (height << 12) | width);
3408
3409         /* Hooray for CUR*CNTR differences */
3410         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3411                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3412                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3413                 temp |= (pipe << 28); /* Connect to correct pipe */
3414         } else {
3415                 temp &= ~(CURSOR_FORMAT_MASK);
3416                 temp |= CURSOR_ENABLE;
3417                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3418         }
3419
3420  finish:
3421         I915_WRITE(control, temp);
3422         I915_WRITE(base, addr);
3423
3424         if (intel_crtc->cursor_bo) {
3425                 if (dev_priv->cursor_needs_physical) {
3426                         if (intel_crtc->cursor_bo != bo)
3427                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3428                 } else
3429                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3430                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3431         }
3432
3433         mutex_unlock(&dev->struct_mutex);
3434
3435         intel_crtc->cursor_addr = addr;
3436         intel_crtc->cursor_bo = bo;
3437
3438         return 0;
3439 fail:
3440         mutex_lock(&dev->struct_mutex);
3441 fail_locked:
3442         drm_gem_object_unreference(bo);
3443         mutex_unlock(&dev->struct_mutex);
3444         return ret;
3445 }
3446
3447 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3448 {
3449         struct drm_device *dev = crtc->dev;
3450         struct drm_i915_private *dev_priv = dev->dev_private;
3451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3452         struct intel_framebuffer *intel_fb;
3453         int pipe = intel_crtc->pipe;
3454         uint32_t temp = 0;
3455         uint32_t adder;
3456
3457         if (crtc->fb) {
3458                 intel_fb = to_intel_framebuffer(crtc->fb);
3459                 intel_mark_busy(dev, intel_fb->obj);
3460         }
3461
3462         if (x < 0) {
3463                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3464                 x = -x;
3465         }
3466         if (y < 0) {
3467                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3468                 y = -y;
3469         }
3470
3471         temp |= x << CURSOR_X_SHIFT;
3472         temp |= y << CURSOR_Y_SHIFT;
3473
3474         adder = intel_crtc->cursor_addr;
3475         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3476         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3477
3478         return 0;
3479 }
3480
3481 /** Sets the color ramps on behalf of RandR */
3482 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3483                                  u16 blue, int regno)
3484 {
3485         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3486
3487         intel_crtc->lut_r[regno] = red >> 8;
3488         intel_crtc->lut_g[regno] = green >> 8;
3489         intel_crtc->lut_b[regno] = blue >> 8;
3490 }
3491
3492 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3493                              u16 *blue, int regno)
3494 {
3495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496
3497         *red = intel_crtc->lut_r[regno] << 8;
3498         *green = intel_crtc->lut_g[regno] << 8;
3499         *blue = intel_crtc->lut_b[regno] << 8;
3500 }
3501
3502 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3503                                  u16 *blue, uint32_t size)
3504 {
3505         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3506         int i;
3507
3508         if (size != 256)
3509                 return;
3510
3511         for (i = 0; i < 256; i++) {
3512                 intel_crtc->lut_r[i] = red[i] >> 8;
3513                 intel_crtc->lut_g[i] = green[i] >> 8;
3514                 intel_crtc->lut_b[i] = blue[i] >> 8;
3515         }
3516
3517         intel_crtc_load_lut(crtc);
3518 }
3519
3520 /**
3521  * Get a pipe with a simple mode set on it for doing load-based monitor
3522  * detection.
3523  *
3524  * It will be up to the load-detect code to adjust the pipe as appropriate for
3525  * its requirements.  The pipe will be connected to no other outputs.
3526  *
3527  * Currently this code will only succeed if there is a pipe with no outputs
3528  * configured for it.  In the future, it could choose to temporarily disable
3529  * some outputs to free up a pipe for its use.
3530  *
3531  * \return crtc, or NULL if no pipes are available.
3532  */
3533
3534 /* VESA 640x480x72Hz mode to set on the pipe */
3535 static struct drm_display_mode load_detect_mode = {
3536         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3537                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3538 };
3539
3540 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3541                                             struct drm_display_mode *mode,
3542                                             int *dpms_mode)
3543 {
3544         struct intel_crtc *intel_crtc;
3545         struct drm_crtc *possible_crtc;
3546         struct drm_crtc *supported_crtc =NULL;
3547         struct drm_encoder *encoder = &intel_output->enc;
3548         struct drm_crtc *crtc = NULL;
3549         struct drm_device *dev = encoder->dev;
3550         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3551         struct drm_crtc_helper_funcs *crtc_funcs;
3552         int i = -1;
3553
3554         /*
3555          * Algorithm gets a little messy:
3556          *   - if the connector already has an assigned crtc, use it (but make
3557          *     sure it's on first)
3558          *   - try to find the first unused crtc that can drive this connector,
3559          *     and use that if we find one
3560          *   - if there are no unused crtcs available, try to use the first
3561          *     one we found that supports the connector
3562          */
3563
3564         /* See if we already have a CRTC for this connector */
3565         if (encoder->crtc) {
3566                 crtc = encoder->crtc;
3567                 /* Make sure the crtc and connector are running */
3568                 intel_crtc = to_intel_crtc(crtc);
3569                 *dpms_mode = intel_crtc->dpms_mode;
3570                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3571                         crtc_funcs = crtc->helper_private;
3572                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3573                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3574                 }
3575                 return crtc;
3576         }
3577
3578         /* Find an unused one (if possible) */
3579         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3580                 i++;
3581                 if (!(encoder->possible_crtcs & (1 << i)))
3582                         continue;
3583                 if (!possible_crtc->enabled) {
3584                         crtc = possible_crtc;
3585                         break;
3586                 }
3587                 if (!supported_crtc)
3588                         supported_crtc = possible_crtc;
3589         }
3590
3591         /*
3592          * If we didn't find an unused CRTC, don't use any.
3593          */
3594         if (!crtc) {
3595                 return NULL;
3596         }
3597
3598         encoder->crtc = crtc;
3599         intel_output->base.encoder = encoder;
3600         intel_output->load_detect_temp = true;
3601
3602         intel_crtc = to_intel_crtc(crtc);
3603         *dpms_mode = intel_crtc->dpms_mode;
3604
3605         if (!crtc->enabled) {
3606                 if (!mode)
3607                         mode = &load_detect_mode;
3608                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3609         } else {
3610                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3611                         crtc_funcs = crtc->helper_private;
3612                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3613                 }
3614
3615                 /* Add this connector to the crtc */
3616                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3617                 encoder_funcs->commit(encoder);
3618         }
3619         /* let the connector get through one full cycle before testing */
3620         intel_wait_for_vblank(dev);
3621
3622         return crtc;
3623 }
3624
3625 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3626 {
3627         struct drm_encoder *encoder = &intel_output->enc;
3628         struct drm_device *dev = encoder->dev;
3629         struct drm_crtc *crtc = encoder->crtc;
3630         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3631         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3632
3633         if (intel_output->load_detect_temp) {
3634                 encoder->crtc = NULL;
3635                 intel_output->base.encoder = NULL;
3636                 intel_output->load_detect_temp = false;
3637                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3638                 drm_helper_disable_unused_functions(dev);
3639         }
3640
3641         /* Switch crtc and output back off if necessary */
3642         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3643                 if (encoder->crtc == crtc)
3644                         encoder_funcs->dpms(encoder, dpms_mode);
3645                 crtc_funcs->dpms(crtc, dpms_mode);
3646         }
3647 }
3648
3649 /* Returns the clock of the currently programmed mode of the given pipe. */
3650 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3651 {
3652         struct drm_i915_private *dev_priv = dev->dev_private;
3653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3654         int pipe = intel_crtc->pipe;
3655         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3656         u32 fp;
3657         intel_clock_t clock;
3658
3659         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3660                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3661         else
3662                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3663
3664         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3665         if (IS_IGD(dev)) {
3666                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3667                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3668         } else {
3669                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3670                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3671         }
3672
3673         if (IS_I9XX(dev)) {
3674                 if (IS_IGD(dev))
3675                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3676                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3677                 else
3678                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3679                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3680
3681                 switch (dpll & DPLL_MODE_MASK) {
3682                 case DPLLB_MODE_DAC_SERIAL:
3683                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3684                                 5 : 10;
3685                         break;
3686                 case DPLLB_MODE_LVDS:
3687                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3688                                 7 : 14;
3689                         break;
3690                 default:
3691                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3692                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3693                         return 0;
3694                 }
3695
3696                 /* XXX: Handle the 100Mhz refclk */
3697                 intel_clock(dev, 96000, &clock);
3698         } else {
3699                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3700
3701                 if (is_lvds) {
3702                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3703                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3704                         clock.p2 = 14;
3705
3706                         if ((dpll & PLL_REF_INPUT_MASK) ==
3707                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3708                                 /* XXX: might not be 66MHz */
3709                                 intel_clock(dev, 66000, &clock);
3710                         } else
3711                                 intel_clock(dev, 48000, &clock);
3712                 } else {
3713                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3714                                 clock.p1 = 2;
3715                         else {
3716                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3717                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3718                         }
3719                         if (dpll & PLL_P2_DIVIDE_BY_4)
3720                                 clock.p2 = 4;
3721                         else
3722                                 clock.p2 = 2;
3723
3724                         intel_clock(dev, 48000, &clock);
3725                 }
3726         }
3727
3728         /* XXX: It would be nice to validate the clocks, but we can't reuse
3729          * i830PllIsValid() because it relies on the xf86_config connector
3730          * configuration being accurate, which it isn't necessarily.
3731          */
3732
3733         return clock.dot;
3734 }
3735
3736 /** Returns the currently programmed mode of the given pipe. */
3737 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3738                                              struct drm_crtc *crtc)
3739 {
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742         int pipe = intel_crtc->pipe;
3743         struct drm_display_mode *mode;
3744         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3745         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3746         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3747         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3748
3749         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3750         if (!mode)
3751                 return NULL;
3752
3753         mode->clock = intel_crtc_clock_get(dev, crtc);
3754         mode->hdisplay = (htot & 0xffff) + 1;
3755         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3756         mode->hsync_start = (hsync & 0xffff) + 1;
3757         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3758         mode->vdisplay = (vtot & 0xffff) + 1;
3759         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3760         mode->vsync_start = (vsync & 0xffff) + 1;
3761         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3762
3763         drm_mode_set_name(mode);
3764         drm_mode_set_crtcinfo(mode, 0);
3765
3766         return mode;
3767 }
3768
3769 #define GPU_IDLE_TIMEOUT 500 /* ms */
3770
3771 /* When this timer fires, we've been idle for awhile */
3772 static void intel_gpu_idle_timer(unsigned long arg)
3773 {
3774         struct drm_device *dev = (struct drm_device *)arg;
3775         drm_i915_private_t *dev_priv = dev->dev_private;
3776
3777         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3778
3779         dev_priv->busy = false;
3780
3781         queue_work(dev_priv->wq, &dev_priv->idle_work);
3782 }
3783
3784 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3785 {
3786         drm_i915_private_t *dev_priv = dev->dev_private;
3787
3788         if (IS_IGDNG(dev))
3789                 return;
3790
3791         if (!dev_priv->render_reclock_avail) {
3792                 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3793                 return;
3794         }
3795
3796         /* Restore render clock frequency to original value */
3797         if (IS_G4X(dev) || IS_I9XX(dev))
3798                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3799         else if (IS_I85X(dev))
3800                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3801         DRM_DEBUG_DRIVER("increasing render clock frequency\n");
3802
3803         /* Schedule downclock */
3804         if (schedule)
3805                 mod_timer(&dev_priv->idle_timer, jiffies +
3806                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3807 }
3808
3809 void intel_decrease_renderclock(struct drm_device *dev)
3810 {
3811         drm_i915_private_t *dev_priv = dev->dev_private;
3812
3813         if (IS_IGDNG(dev))
3814                 return;
3815
3816         if (!dev_priv->render_reclock_avail) {
3817                 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3818                 return;
3819         }
3820
3821         if (IS_G4X(dev)) {
3822                 u16 gcfgc;
3823
3824                 /* Adjust render clock... */
3825                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3826
3827                 /* Down to minimum... */
3828                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3829                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3830
3831                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3832         } else if (IS_I965G(dev)) {
3833                 u16 gcfgc;
3834
3835                 /* Adjust render clock... */
3836                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3837
3838                 /* Down to minimum... */
3839                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3840                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3841
3842                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3843         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3844                 u16 gcfgc;
3845
3846                 /* Adjust render clock... */
3847                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3848
3849                 /* Down to minimum... */
3850                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3851                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3852
3853                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3854         } else if (IS_I915G(dev)) {
3855                 u16 gcfgc;
3856
3857                 /* Adjust render clock... */
3858                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3859
3860                 /* Down to minimum... */
3861                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3862                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3863
3864                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3865         } else if (IS_I85X(dev)) {
3866                 u16 hpllcc;
3867
3868                 /* Adjust render clock... */
3869                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3870
3871                 /* Up to maximum... */
3872                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3873                 hpllcc |= GC_CLOCK_133_200;
3874
3875                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3876         }
3877         DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
3878 }
3879
3880 /* Note that no increase function is needed for this - increase_renderclock()
3881  *  will also rewrite these bits
3882  */
3883 void intel_decrease_displayclock(struct drm_device *dev)
3884 {
3885         if (IS_IGDNG(dev))
3886                 return;
3887
3888         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3889             IS_I915GM(dev)) {
3890                 u16 gcfgc;
3891
3892                 /* Adjust render clock... */
3893                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3894
3895                 /* Down to minimum... */
3896                 gcfgc &= ~0xf0;
3897                 gcfgc |= 0x80;
3898
3899                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3900         }
3901 }
3902
3903 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3904
3905 static void intel_crtc_idle_timer(unsigned long arg)
3906 {
3907         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3908         struct drm_crtc *crtc = &intel_crtc->base;
3909         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3910
3911         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3912
3913         intel_crtc->busy = false;
3914
3915         queue_work(dev_priv->wq, &dev_priv->idle_work);
3916 }
3917
3918 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3919 {
3920         struct drm_device *dev = crtc->dev;
3921         drm_i915_private_t *dev_priv = dev->dev_private;
3922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3923         int pipe = intel_crtc->pipe;
3924         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3925         int dpll = I915_READ(dpll_reg);
3926
3927         if (IS_IGDNG(dev))
3928                 return;
3929
3930         if (!dev_priv->lvds_downclock_avail)
3931                 return;
3932
3933         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3934                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3935
3936                 /* Unlock panel regs */
3937                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3938
3939                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3940                 I915_WRITE(dpll_reg, dpll);
3941                 dpll = I915_READ(dpll_reg);
3942                 intel_wait_for_vblank(dev);
3943                 dpll = I915_READ(dpll_reg);
3944                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3945                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3946
3947                 /* ...and lock them again */
3948                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3949         }
3950
3951         /* Schedule downclock */
3952         if (schedule)
3953                 mod_timer(&intel_crtc->idle_timer, jiffies +
3954                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3955 }
3956
3957 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3958 {
3959         struct drm_device *dev = crtc->dev;
3960         drm_i915_private_t *dev_priv = dev->dev_private;
3961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3962         int pipe = intel_crtc->pipe;
3963         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3964         int dpll = I915_READ(dpll_reg);
3965
3966         if (IS_IGDNG(dev))
3967                 return;
3968
3969         if (!dev_priv->lvds_downclock_avail)
3970                 return;
3971
3972         /*
3973          * Since this is called by a timer, we should never get here in
3974          * the manual case.
3975          */
3976         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3977                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3978
3979                 /* Unlock panel regs */
3980                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3981
3982                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3983                 I915_WRITE(dpll_reg, dpll);
3984                 dpll = I915_READ(dpll_reg);
3985                 intel_wait_for_vblank(dev);
3986                 dpll = I915_READ(dpll_reg);
3987                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3988                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3989
3990                 /* ...and lock them again */
3991                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3992         }
3993
3994 }
3995
3996 /**
3997  * intel_idle_update - adjust clocks for idleness
3998  * @work: work struct
3999  *
4000  * Either the GPU or display (or both) went idle.  Check the busy status
4001  * here and adjust the CRTC and GPU clocks as necessary.
4002  */
4003 static void intel_idle_update(struct work_struct *work)
4004 {
4005         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4006                                                     idle_work);
4007         struct drm_device *dev = dev_priv->dev;
4008         struct drm_crtc *crtc;
4009         struct intel_crtc *intel_crtc;
4010
4011         if (!i915_powersave)
4012                 return;
4013
4014         mutex_lock(&dev->struct_mutex);
4015
4016         /* GPU isn't processing, downclock it. */
4017         if (!dev_priv->busy) {
4018                 intel_decrease_renderclock(dev);
4019                 intel_decrease_displayclock(dev);
4020         }
4021
4022         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4023                 /* Skip inactive CRTCs */
4024                 if (!crtc->fb)
4025                         continue;
4026
4027                 intel_crtc = to_intel_crtc(crtc);
4028                 if (!intel_crtc->busy)
4029                         intel_decrease_pllclock(crtc);
4030         }
4031
4032         mutex_unlock(&dev->struct_mutex);
4033 }
4034
4035 /**
4036  * intel_mark_busy - mark the GPU and possibly the display busy
4037  * @dev: drm device
4038  * @obj: object we're operating on
4039  *
4040  * Callers can use this function to indicate that the GPU is busy processing
4041  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4042  * buffer), we'll also mark the display as busy, so we know to increase its
4043  * clock frequency.
4044  */
4045 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4046 {
4047         drm_i915_private_t *dev_priv = dev->dev_private;
4048         struct drm_crtc *crtc = NULL;
4049         struct intel_framebuffer *intel_fb;
4050         struct intel_crtc *intel_crtc;
4051
4052         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4053                 return;
4054
4055         if (!dev_priv->busy) {
4056                 dev_priv->busy = true;
4057                 intel_increase_renderclock(dev, true);
4058         } else {
4059                 mod_timer(&dev_priv->idle_timer, jiffies +
4060                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4061         }
4062
4063         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4064                 if (!crtc->fb)
4065                         continue;
4066
4067                 intel_crtc = to_intel_crtc(crtc);
4068                 intel_fb = to_intel_framebuffer(crtc->fb);
4069                 if (intel_fb->obj == obj) {
4070                         if (!intel_crtc->busy) {
4071                                 /* Non-busy -> busy, upclock */
4072                                 intel_increase_pllclock(crtc, true);
4073                                 intel_crtc->busy = true;
4074                         } else {
4075                                 /* Busy -> busy, put off timer */
4076                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4077                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4078                         }
4079                 }
4080         }
4081 }
4082
4083 static void intel_crtc_destroy(struct drm_crtc *crtc)
4084 {
4085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4086
4087         drm_crtc_cleanup(crtc);
4088         kfree(intel_crtc);
4089 }
4090
4091 struct intel_unpin_work {
4092         struct work_struct work;
4093         struct drm_device *dev;
4094         struct drm_gem_object *obj;
4095         struct drm_pending_vblank_event *event;
4096         int pending;
4097 };
4098
4099 static void intel_unpin_work_fn(struct work_struct *__work)
4100 {
4101         struct intel_unpin_work *work =
4102                 container_of(__work, struct intel_unpin_work, work);
4103
4104         mutex_lock(&work->dev->struct_mutex);
4105         i915_gem_object_unpin(work->obj);
4106         drm_gem_object_unreference(work->obj);
4107         mutex_unlock(&work->dev->struct_mutex);
4108         kfree(work);
4109 }
4110
4111 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4112 {
4113         drm_i915_private_t *dev_priv = dev->dev_private;
4114         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4116         struct intel_unpin_work *work;
4117         struct drm_i915_gem_object *obj_priv;
4118         struct drm_pending_vblank_event *e;
4119         struct timeval now;
4120         unsigned long flags;
4121
4122         /* Ignore early vblank irqs */
4123         if (intel_crtc == NULL)
4124                 return;
4125
4126         spin_lock_irqsave(&dev->event_lock, flags);
4127         work = intel_crtc->unpin_work;
4128         if (work == NULL || !work->pending) {
4129                 spin_unlock_irqrestore(&dev->event_lock, flags);
4130                 return;
4131         }
4132
4133         intel_crtc->unpin_work = NULL;
4134         drm_vblank_put(dev, intel_crtc->pipe);
4135
4136         if (work->event) {
4137                 e = work->event;
4138                 do_gettimeofday(&now);
4139                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4140                 e->event.tv_sec = now.tv_sec;
4141                 e->event.tv_usec = now.tv_usec;
4142                 list_add_tail(&e->base.link,
4143                               &e->base.file_priv->event_list);
4144                 wake_up_interruptible(&e->base.file_priv->event_wait);
4145         }
4146
4147         spin_unlock_irqrestore(&dev->event_lock, flags);
4148
4149         obj_priv = work->obj->driver_private;
4150         if (atomic_dec_and_test(&obj_priv->pending_flip))
4151                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4152         schedule_work(&work->work);
4153 }
4154
4155 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4156 {
4157         drm_i915_private_t *dev_priv = dev->dev_private;
4158         struct intel_crtc *intel_crtc =
4159                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4160         unsigned long flags;
4161
4162         spin_lock_irqsave(&dev->event_lock, flags);
4163         if (intel_crtc->unpin_work)
4164                 intel_crtc->unpin_work->pending = 1;
4165         spin_unlock_irqrestore(&dev->event_lock, flags);
4166 }
4167
4168 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4169                                 struct drm_framebuffer *fb,
4170                                 struct drm_pending_vblank_event *event)
4171 {
4172         struct drm_device *dev = crtc->dev;
4173         struct drm_i915_private *dev_priv = dev->dev_private;
4174         struct intel_framebuffer *intel_fb;
4175         struct drm_i915_gem_object *obj_priv;
4176         struct drm_gem_object *obj;
4177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178         struct intel_unpin_work *work;
4179         unsigned long flags;
4180         int ret;
4181         RING_LOCALS;
4182
4183         work = kzalloc(sizeof *work, GFP_KERNEL);
4184         if (work == NULL)
4185                 return -ENOMEM;
4186
4187         mutex_lock(&dev->struct_mutex);
4188
4189         work->event = event;
4190         work->dev = crtc->dev;
4191         intel_fb = to_intel_framebuffer(crtc->fb);
4192         work->obj = intel_fb->obj;
4193         INIT_WORK(&work->work, intel_unpin_work_fn);
4194
4195         /* We borrow the event spin lock for protecting unpin_work */
4196         spin_lock_irqsave(&dev->event_lock, flags);
4197         if (intel_crtc->unpin_work) {
4198                 spin_unlock_irqrestore(&dev->event_lock, flags);
4199                 kfree(work);
4200                 mutex_unlock(&dev->struct_mutex);
4201                 return -EBUSY;
4202         }
4203         intel_crtc->unpin_work = work;
4204         spin_unlock_irqrestore(&dev->event_lock, flags);
4205
4206         intel_fb = to_intel_framebuffer(fb);
4207         obj = intel_fb->obj;
4208
4209         ret = intel_pin_and_fence_fb_obj(dev, obj);
4210         if (ret != 0) {
4211                 kfree(work);
4212                 mutex_unlock(&dev->struct_mutex);
4213                 return ret;
4214         }
4215
4216         /* Reference the old fb object for the scheduled work. */
4217         drm_gem_object_reference(work->obj);
4218
4219         crtc->fb = fb;
4220         i915_gem_object_flush_write_domain(obj);
4221         drm_vblank_get(dev, intel_crtc->pipe);
4222         obj_priv = obj->driver_private;
4223         atomic_inc(&obj_priv->pending_flip);
4224
4225         BEGIN_LP_RING(4);
4226         OUT_RING(MI_DISPLAY_FLIP |
4227                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4228         OUT_RING(fb->pitch);
4229         OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4230         OUT_RING((fb->width << 16) | fb->height);
4231         ADVANCE_LP_RING();
4232
4233         mutex_unlock(&dev->struct_mutex);
4234
4235         return 0;
4236 }
4237
4238 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4239         .dpms = intel_crtc_dpms,
4240         .mode_fixup = intel_crtc_mode_fixup,
4241         .mode_set = intel_crtc_mode_set,
4242         .mode_set_base = intel_pipe_set_base,
4243         .prepare = intel_crtc_prepare,
4244         .commit = intel_crtc_commit,
4245         .load_lut = intel_crtc_load_lut,
4246 };
4247
4248 static const struct drm_crtc_funcs intel_crtc_funcs = {
4249         .cursor_set = intel_crtc_cursor_set,
4250         .cursor_move = intel_crtc_cursor_move,
4251         .gamma_set = intel_crtc_gamma_set,
4252         .set_config = drm_crtc_helper_set_config,
4253         .destroy = intel_crtc_destroy,
4254         .page_flip = intel_crtc_page_flip,
4255 };
4256
4257
4258 static void intel_crtc_init(struct drm_device *dev, int pipe)
4259 {
4260         struct intel_crtc *intel_crtc;
4261         int i;
4262
4263         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4264         if (intel_crtc == NULL)
4265                 return;
4266
4267         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4268
4269         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4270         intel_crtc->pipe = pipe;
4271         intel_crtc->plane = pipe;
4272         for (i = 0; i < 256; i++) {
4273                 intel_crtc->lut_r[i] = i;
4274                 intel_crtc->lut_g[i] = i;
4275                 intel_crtc->lut_b[i] = i;
4276         }
4277
4278         /* Swap pipes & planes for FBC on pre-965 */
4279         intel_crtc->pipe = pipe;
4280         intel_crtc->plane = pipe;
4281         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4282                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4283                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4284         }
4285
4286         intel_crtc->cursor_addr = 0;
4287         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4288         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4289
4290         intel_crtc->busy = false;
4291
4292         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4293                     (unsigned long)intel_crtc);
4294 }
4295
4296 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4297                                 struct drm_file *file_priv)
4298 {
4299         drm_i915_private_t *dev_priv = dev->dev_private;
4300         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4301         struct drm_mode_object *drmmode_obj;
4302         struct intel_crtc *crtc;
4303
4304         if (!dev_priv) {
4305                 DRM_ERROR("called with no initialization\n");
4306                 return -EINVAL;
4307         }
4308
4309         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4310                         DRM_MODE_OBJECT_CRTC);
4311
4312         if (!drmmode_obj) {
4313                 DRM_ERROR("no such CRTC id\n");
4314                 return -EINVAL;
4315         }
4316
4317         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4318         pipe_from_crtc_id->pipe = crtc->pipe;
4319
4320         return 0;
4321 }
4322
4323 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4324 {
4325         struct drm_crtc *crtc = NULL;
4326
4327         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4328                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4329                 if (intel_crtc->pipe == pipe)
4330                         break;
4331         }
4332         return crtc;
4333 }
4334
4335 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4336 {
4337         int index_mask = 0;
4338         struct drm_connector *connector;
4339         int entry = 0;
4340
4341         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4342                 struct intel_output *intel_output = to_intel_output(connector);
4343                 if (type_mask & intel_output->clone_mask)
4344                         index_mask |= (1 << entry);
4345                 entry++;
4346         }
4347         return index_mask;
4348 }
4349
4350
4351 static void intel_setup_outputs(struct drm_device *dev)
4352 {
4353         struct drm_i915_private *dev_priv = dev->dev_private;
4354         struct drm_connector *connector;
4355
4356         intel_crt_init(dev);
4357
4358         /* Set up integrated LVDS */
4359         if (IS_MOBILE(dev) && !IS_I830(dev))
4360                 intel_lvds_init(dev);
4361
4362         if (IS_IGDNG(dev)) {
4363                 int found;
4364
4365                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4366                         intel_dp_init(dev, DP_A);
4367
4368                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4369                         /* check SDVOB */
4370                         /* found = intel_sdvo_init(dev, HDMIB); */
4371                         found = 0;
4372                         if (!found)
4373                                 intel_hdmi_init(dev, HDMIB);
4374                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4375                                 intel_dp_init(dev, PCH_DP_B);
4376                 }
4377
4378                 if (I915_READ(HDMIC) & PORT_DETECTED)
4379                         intel_hdmi_init(dev, HDMIC);
4380
4381                 if (I915_READ(HDMID) & PORT_DETECTED)
4382                         intel_hdmi_init(dev, HDMID);
4383
4384                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4385                         intel_dp_init(dev, PCH_DP_C);
4386
4387                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4388                         intel_dp_init(dev, PCH_DP_D);
4389
4390         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4391                 bool found = false;
4392
4393                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4394                         found = intel_sdvo_init(dev, SDVOB);
4395                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4396                                 intel_hdmi_init(dev, SDVOB);
4397
4398                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
4399                                 intel_dp_init(dev, DP_B);
4400                 }
4401
4402                 /* Before G4X SDVOC doesn't have its own detect register */
4403
4404                 if (I915_READ(SDVOB) & SDVO_DETECTED)
4405                         found = intel_sdvo_init(dev, SDVOC);
4406
4407                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4408
4409                         if (SUPPORTS_INTEGRATED_HDMI(dev))
4410                                 intel_hdmi_init(dev, SDVOC);
4411                         if (SUPPORTS_INTEGRATED_DP(dev))
4412                                 intel_dp_init(dev, DP_C);
4413                 }
4414
4415                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4416                         intel_dp_init(dev, DP_D);
4417         } else if (IS_I8XX(dev))
4418                 intel_dvo_init(dev);
4419
4420         if (SUPPORTS_TV(dev))
4421                 intel_tv_init(dev);
4422
4423         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4424                 struct intel_output *intel_output = to_intel_output(connector);
4425                 struct drm_encoder *encoder = &intel_output->enc;
4426
4427                 encoder->possible_crtcs = intel_output->crtc_mask;
4428                 encoder->possible_clones = intel_connector_clones(dev,
4429                                                 intel_output->clone_mask);
4430         }
4431 }
4432
4433 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4434 {
4435         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4436         struct drm_device *dev = fb->dev;
4437
4438         if (fb->fbdev)
4439                 intelfb_remove(dev, fb);
4440
4441         drm_framebuffer_cleanup(fb);
4442         mutex_lock(&dev->struct_mutex);
4443         drm_gem_object_unreference(intel_fb->obj);
4444         mutex_unlock(&dev->struct_mutex);
4445
4446         kfree(intel_fb);
4447 }
4448
4449 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4450                                                 struct drm_file *file_priv,
4451                                                 unsigned int *handle)
4452 {
4453         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4454         struct drm_gem_object *object = intel_fb->obj;
4455
4456         return drm_gem_handle_create(file_priv, object, handle);
4457 }
4458
4459 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4460         .destroy = intel_user_framebuffer_destroy,
4461         .create_handle = intel_user_framebuffer_create_handle,
4462 };
4463
4464 int intel_framebuffer_create(struct drm_device *dev,
4465                              struct drm_mode_fb_cmd *mode_cmd,
4466                              struct drm_framebuffer **fb,
4467                              struct drm_gem_object *obj)
4468 {
4469         struct intel_framebuffer *intel_fb;
4470         int ret;
4471
4472         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4473         if (!intel_fb)
4474                 return -ENOMEM;
4475
4476         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4477         if (ret) {
4478                 DRM_ERROR("framebuffer init failed %d\n", ret);
4479                 return ret;
4480         }
4481
4482         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4483
4484         intel_fb->obj = obj;
4485
4486         *fb = &intel_fb->base;
4487
4488         return 0;
4489 }
4490
4491
4492 static struct drm_framebuffer *
4493 intel_user_framebuffer_create(struct drm_device *dev,
4494                               struct drm_file *filp,
4495                               struct drm_mode_fb_cmd *mode_cmd)
4496 {
4497         struct drm_gem_object *obj;
4498         struct drm_framebuffer *fb;
4499         int ret;
4500
4501         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4502         if (!obj)
4503                 return NULL;
4504
4505         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4506         if (ret) {
4507                 mutex_lock(&dev->struct_mutex);
4508                 drm_gem_object_unreference(obj);
4509                 mutex_unlock(&dev->struct_mutex);
4510                 return NULL;
4511         }
4512
4513         return fb;
4514 }
4515
4516 static const struct drm_mode_config_funcs intel_mode_funcs = {
4517         .fb_create = intel_user_framebuffer_create,
4518         .fb_changed = intelfb_probe,
4519 };
4520
4521 void intel_init_clock_gating(struct drm_device *dev)
4522 {
4523         struct drm_i915_private *dev_priv = dev->dev_private;
4524
4525         /*
4526          * Disable clock gating reported to work incorrectly according to the
4527          * specs, but enable as much else as we can.
4528          */
4529         if (IS_IGDNG(dev)) {
4530                 return;
4531         } else if (IS_G4X(dev)) {
4532                 uint32_t dspclk_gate;
4533                 I915_WRITE(RENCLK_GATE_D1, 0);
4534                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4535                        GS_UNIT_CLOCK_GATE_DISABLE |
4536                        CL_UNIT_CLOCK_GATE_DISABLE);
4537                 I915_WRITE(RAMCLK_GATE_D, 0);
4538                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4539                         OVRUNIT_CLOCK_GATE_DISABLE |
4540                         OVCUNIT_CLOCK_GATE_DISABLE;
4541                 if (IS_GM45(dev))
4542                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4543                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4544         } else if (IS_I965GM(dev)) {
4545                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4546                 I915_WRITE(RENCLK_GATE_D2, 0);
4547                 I915_WRITE(DSPCLK_GATE_D, 0);
4548                 I915_WRITE(RAMCLK_GATE_D, 0);
4549                 I915_WRITE16(DEUC, 0);
4550         } else if (IS_I965G(dev)) {
4551                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4552                        I965_RCC_CLOCK_GATE_DISABLE |
4553                        I965_RCPB_CLOCK_GATE_DISABLE |
4554                        I965_ISC_CLOCK_GATE_DISABLE |
4555                        I965_FBC_CLOCK_GATE_DISABLE);
4556                 I915_WRITE(RENCLK_GATE_D2, 0);
4557         } else if (IS_I9XX(dev)) {
4558                 u32 dstate = I915_READ(D_STATE);
4559
4560                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4561                         DSTATE_DOT_CLOCK_GATING;
4562                 I915_WRITE(D_STATE, dstate);
4563         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4564                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4565         } else if (IS_I830(dev)) {
4566                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4567         }
4568
4569         /*
4570          * GPU can automatically power down the render unit if given a page
4571          * to save state.
4572          */
4573         if (I915_HAS_RC6(dev)) {
4574                 struct drm_gem_object *pwrctx;
4575                 struct drm_i915_gem_object *obj_priv;
4576                 int ret;
4577
4578                 pwrctx = drm_gem_object_alloc(dev, 4096);
4579                 if (!pwrctx) {
4580                         DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4581                         goto out;
4582                 }
4583
4584                 ret = i915_gem_object_pin(pwrctx, 4096);
4585                 if (ret) {
4586                         DRM_ERROR("failed to pin power context: %d\n", ret);
4587                         drm_gem_object_unreference(pwrctx);
4588                         goto out;
4589                 }
4590
4591                 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4592
4593                 obj_priv = pwrctx->driver_private;
4594
4595                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4596                 I915_WRITE(MCHBAR_RENDER_STANDBY,
4597                            I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4598
4599                 dev_priv->pwrctx = pwrctx;
4600         }
4601
4602 out:
4603         return;
4604 }
4605
4606 /* Set up chip specific display functions */
4607 static void intel_init_display(struct drm_device *dev)
4608 {
4609         struct drm_i915_private *dev_priv = dev->dev_private;
4610
4611         /* We always want a DPMS function */
4612         if (IS_IGDNG(dev))
4613                 dev_priv->display.dpms = igdng_crtc_dpms;
4614         else
4615                 dev_priv->display.dpms = i9xx_crtc_dpms;
4616
4617         /* Only mobile has FBC, leave pointers NULL for other chips */
4618         if (IS_MOBILE(dev)) {
4619                 if (IS_GM45(dev)) {
4620                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4621                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4622                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4623                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4624                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4625                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4626                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4627                 }
4628                 /* 855GM needs testing */
4629         }
4630
4631         /* Returns the core display clock speed */
4632         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_IGDGM(dev)))
4633                 dev_priv->display.get_display_clock_speed =
4634                         i945_get_display_clock_speed;
4635         else if (IS_I915G(dev))
4636                 dev_priv->display.get_display_clock_speed =
4637                         i915_get_display_clock_speed;
4638         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4639                 dev_priv->display.get_display_clock_speed =
4640                         i9xx_misc_get_display_clock_speed;
4641         else if (IS_I915GM(dev))
4642                 dev_priv->display.get_display_clock_speed =
4643                         i915gm_get_display_clock_speed;
4644         else if (IS_I865G(dev))
4645                 dev_priv->display.get_display_clock_speed =
4646                         i865_get_display_clock_speed;
4647         else if (IS_I85X(dev))
4648                 dev_priv->display.get_display_clock_speed =
4649                         i855_get_display_clock_speed;
4650         else /* 852, 830 */
4651                 dev_priv->display.get_display_clock_speed =
4652                         i830_get_display_clock_speed;
4653
4654         /* For FIFO watermark updates */
4655         if (IS_IGDNG(dev))
4656                 dev_priv->display.update_wm = NULL;
4657         else if (IS_G4X(dev))
4658                 dev_priv->display.update_wm = g4x_update_wm;
4659         else if (IS_I965G(dev))
4660                 dev_priv->display.update_wm = i965_update_wm;
4661         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4662                 dev_priv->display.update_wm = i9xx_update_wm;
4663                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4664         } else {
4665                 if (IS_I85X(dev))
4666                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4667                 else if (IS_845G(dev))
4668                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4669                 else
4670                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4671                 dev_priv->display.update_wm = i830_update_wm;
4672         }
4673 }
4674
4675 void intel_modeset_init(struct drm_device *dev)
4676 {
4677         struct drm_i915_private *dev_priv = dev->dev_private;
4678         int num_pipe;
4679         int i;
4680
4681         drm_mode_config_init(dev);
4682
4683         dev->mode_config.min_width = 0;
4684         dev->mode_config.min_height = 0;
4685
4686         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4687
4688         intel_init_display(dev);
4689
4690         if (IS_I965G(dev)) {
4691                 dev->mode_config.max_width = 8192;
4692                 dev->mode_config.max_height = 8192;
4693         } else if (IS_I9XX(dev)) {
4694                 dev->mode_config.max_width = 4096;
4695                 dev->mode_config.max_height = 4096;
4696         } else {
4697                 dev->mode_config.max_width = 2048;
4698                 dev->mode_config.max_height = 2048;
4699         }
4700
4701         /* set memory base */
4702         if (IS_I9XX(dev))
4703                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4704         else
4705                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4706
4707         if (IS_MOBILE(dev) || IS_I9XX(dev))
4708                 num_pipe = 2;
4709         else
4710                 num_pipe = 1;
4711         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4712                   num_pipe, num_pipe > 1 ? "s" : "");
4713
4714         if (IS_I85X(dev))
4715                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4716         else if (IS_I9XX(dev) || IS_G4X(dev))
4717                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4718
4719         for (i = 0; i < num_pipe; i++) {
4720                 intel_crtc_init(dev, i);
4721         }
4722
4723         intel_setup_outputs(dev);
4724
4725         intel_init_clock_gating(dev);
4726
4727         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4728         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4729                     (unsigned long)dev);
4730
4731         intel_setup_overlay(dev);
4732 }
4733
4734 void intel_modeset_cleanup(struct drm_device *dev)
4735 {
4736         struct drm_i915_private *dev_priv = dev->dev_private;
4737         struct drm_crtc *crtc;
4738         struct intel_crtc *intel_crtc;
4739
4740         mutex_lock(&dev->struct_mutex);
4741
4742         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4743                 /* Skip inactive CRTCs */
4744                 if (!crtc->fb)
4745                         continue;
4746
4747                 intel_crtc = to_intel_crtc(crtc);
4748                 intel_increase_pllclock(crtc, false);
4749                 del_timer_sync(&intel_crtc->idle_timer);
4750         }
4751
4752         intel_increase_renderclock(dev, false);
4753         del_timer_sync(&dev_priv->idle_timer);
4754
4755         if (dev_priv->display.disable_fbc)
4756                 dev_priv->display.disable_fbc(dev);
4757
4758         if (dev_priv->pwrctx) {
4759                 struct drm_i915_gem_object *obj_priv;
4760
4761                 obj_priv = dev_priv->pwrctx->driver_private;
4762                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4763                 I915_READ(PWRCTXA);
4764                 i915_gem_object_unpin(dev_priv->pwrctx);
4765                 drm_gem_object_unreference(dev_priv->pwrctx);
4766         }
4767
4768         mutex_unlock(&dev->struct_mutex);
4769
4770         drm_mode_config_cleanup(dev);
4771 }
4772
4773
4774 /* current intel driver doesn't take advantage of encoders
4775    always give back the encoder for the connector
4776 */
4777 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4778 {
4779         struct intel_output *intel_output = to_intel_output(connector);
4780
4781         return &intel_output->enc;
4782 }
4783
4784 /*
4785  * set vga decode state - true == enable VGA decode
4786  */
4787 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4788 {
4789         struct drm_i915_private *dev_priv = dev->dev_private;
4790         u16 gmch_ctrl;
4791
4792         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4793         if (state)
4794                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4795         else
4796                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4797         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4798         return 0;
4799 }