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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30
  31 #include <asm/desc.h>
  32
  33 #include <asm/virtext.h>
  34 #include "trace.h"
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 #define IOPM_ALLOC_ORDER 2
  42 #define MSRPM_ALLOC_ORDER 1
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT            (1 <<  0)
  48 #define SVM_FEATURE_LBRV           (1 <<  1)
  49 #define SVM_FEATURE_SVML           (1 <<  2)
  50 #define SVM_FEATURE_NRIP           (1 <<  3)
  51 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  52
  53 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  54 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  55 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  56
  57 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  58
  59 static const u32 host_save_user_msrs[] = {
  60 #ifdef CONFIG_X86_64
  61         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  62         MSR_FS_BASE,
  63 #endif
  64         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  65 };
  66
  67 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  68
  69 struct kvm_vcpu;
  70
  71 struct nested_state {
  72         struct vmcb *hsave;
  73         u64 hsave_msr;
  74         u64 vm_cr_msr;
  75         u64 vmcb;
  76
  77         /* These are the merged vectors */
  78         u32 *msrpm;
  79
  80         /* gpa pointers to the real vectors */
  81         u64 vmcb_msrpm;
  82         u64 vmcb_iopm;
  83
  84         /* A VMEXIT is required but not yet emulated */
  85         bool exit_required;
  86
  87         /* cache for intercepts of the guest */
  88         u16 intercept_cr_read;
  89         u16 intercept_cr_write;
  90         u16 intercept_dr_read;
  91         u16 intercept_dr_write;
  92         u32 intercept_exceptions;
  93         u64 intercept;
  94
  95 };
  96
  97 #define MSRPM_OFFSETS   16
  98 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  99
 100 struct vcpu_svm {
 101         struct kvm_vcpu vcpu;
 102         struct vmcb *vmcb;
 103         unsigned long vmcb_pa;
 104         struct svm_cpu_data *svm_data;
 105         uint64_t asid_generation;
 106         uint64_t sysenter_esp;
 107         uint64_t sysenter_eip;
 108
 109         u64 next_rip;
 110
 111         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 112         u64 host_gs_base;
 113
 114         u32 *msrpm;
 115
 116         struct nested_state nested;
 117
 118         bool nmi_singlestep;
 119
 120         unsigned int3_injected;
 121         unsigned long int3_rip;
 122 };
 123
 124 #define MSR_INVALID                     0xffffffffU
 125
 126 static struct svm_direct_access_msrs {
 127         u32 index;   /* Index of the MSR */
 128         bool always; /* True if intercept is always on */
 129 } direct_access_msrs[] = {
 130         { .index = MSR_K6_STAR,                         .always = true  },
 131         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 132 #ifdef CONFIG_X86_64
 133         { .index = MSR_GS_BASE,                         .always = true  },
 134         { .index = MSR_FS_BASE,                         .always = true  },
 135         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 136         { .index = MSR_LSTAR,                           .always = true  },
 137         { .index = MSR_CSTAR,                           .always = true  },
 138         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 139 #endif
 140         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 141         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 142         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 143         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 144         { .index = MSR_INVALID,                         .always = false },
 145 };
 146
 147 /* enable NPT for AMD64 and X86 with PAE */
 148 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 149 static bool npt_enabled = true;
 150 #else
 151 static bool npt_enabled;
 152 #endif
 153 static int npt = 1;
 154
 155 module_param(npt, int, S_IRUGO);
 156
 157 static int nested = 1;
 158 module_param(nested, int, S_IRUGO);
 159
 160 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 161 static void svm_complete_interrupts(struct vcpu_svm *svm);
 162
 163 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 164 static int nested_svm_intercept(struct vcpu_svm *svm);
 165 static int nested_svm_vmexit(struct vcpu_svm *svm);
 166 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 167                                       bool has_error_code, u32 error_code);
 168
 169 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 170 {
 171         return container_of(vcpu, struct vcpu_svm, vcpu);
 172 }
 173
 174 static inline bool is_nested(struct vcpu_svm *svm)
 175 {
 176         return svm->nested.vmcb;
 177 }
 178
 179 static inline void enable_gif(struct vcpu_svm *svm)
 180 {
 181         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 182 }
 183
 184 static inline void disable_gif(struct vcpu_svm *svm)
 185 {
 186         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 187 }
 188
 189 static inline bool gif_set(struct vcpu_svm *svm)
 190 {
 191         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 192 }
 193
 194 static unsigned long iopm_base;
 195
 196 struct kvm_ldttss_desc {
 197         u16 limit0;
 198         u16 base0;
 199         unsigned base1:8, type:5, dpl:2, p:1;
 200         unsigned limit1:4, zero0:3, g:1, base2:8;
 201         u32 base3;
 202         u32 zero1;
 203 } __attribute__((packed));
 204
 205 struct svm_cpu_data {
 206         int cpu;
 207
 208         u64 asid_generation;
 209         u32 max_asid;
 210         u32 next_asid;
 211         struct kvm_ldttss_desc *tss_desc;
 212
 213         struct page *save_area;
 214 };
 215
 216 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 217 static uint32_t svm_features;
 218
 219 struct svm_init_data {
 220         int cpu;
 221         int r;
 222 };
 223
 224 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 225
 226 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 227 #define MSRS_RANGE_SIZE 2048
 228 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 229
 230 static u32 svm_msrpm_offset(u32 msr)
 231 {
 232         u32 offset;
 233         int i;
 234
 235         for (i = 0; i < NUM_MSR_MAPS; i++) {
 236                 if (msr < msrpm_ranges[i] ||
 237                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 238                         continue;
 239
 240                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 241                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 242
 243                 /* Now we have the u8 offset - but need the u32 offset */
 244                 return offset / 4;
 245         }
 246
 247         /* MSR not in any range */
 248         return MSR_INVALID;
 249 }
 250
 251 #define MAX_INST_SIZE 15
 252
 253 static inline u32 svm_has(u32 feat)
 254 {
 255         return svm_features & feat;
 256 }
 257
 258 static inline void clgi(void)
 259 {
 260         asm volatile (__ex(SVM_CLGI));
 261 }
 262
 263 static inline void stgi(void)
 264 {
 265         asm volatile (__ex(SVM_STGI));
 266 }
 267
 268 static inline void invlpga(unsigned long addr, u32 asid)
 269 {
 270         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 271 }
 272
 273 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 274 {
 275         to_svm(vcpu)->asid_generation--;
 276 }
 277
 278 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 279 {
 280         force_new_asid(vcpu);
 281 }
 282
 283 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 284 {
 285         if (!npt_enabled && !(efer & EFER_LMA))
 286                 efer &= ~EFER_LME;
 287
 288         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 289         vcpu->arch.efer = efer;
 290 }
 291
 292 static int is_external_interrupt(u32 info)
 293 {
 294         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 295         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 296 }
 297
 298 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 299 {
 300         struct vcpu_svm *svm = to_svm(vcpu);
 301         u32 ret = 0;
 302
 303         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 304                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 305         return ret & mask;
 306 }
 307
 308 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 309 {
 310         struct vcpu_svm *svm = to_svm(vcpu);
 311
 312         if (mask == 0)
 313                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 314         else
 315                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 316
 317 }
 318
 319 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 320 {
 321         struct vcpu_svm *svm = to_svm(vcpu);
 322
 323         if (svm->vmcb->control.next_rip != 0)
 324                 svm->next_rip = svm->vmcb->control.next_rip;
 325
 326         if (!svm->next_rip) {
 327                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 328                                 EMULATE_DONE)
 329                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 330                 return;
 331         }
 332         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 333                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 334                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 335
 336         kvm_rip_write(vcpu, svm->next_rip);
 337         svm_set_interrupt_shadow(vcpu, 0);
 338 }
 339
 340 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 341                                 bool has_error_code, u32 error_code,
 342                                 bool reinject)
 343 {
 344         struct vcpu_svm *svm = to_svm(vcpu);
 345
 346         /*
 347          * If we are within a nested VM we'd better #VMEXIT and let the guest
 348          * handle the exception
 349          */
 350         if (!reinject &&
 351             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 352                 return;
 353
 354         if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
 355                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 356
 357                 /*
 358                  * For guest debugging where we have to reinject #BP if some
 359                  * INT3 is guest-owned:
 360                  * Emulate nRIP by moving RIP forward. Will fail if injection
 361                  * raises a fault that is not intercepted. Still better than
 362                  * failing in all cases.
 363                  */
 364                 skip_emulated_instruction(&svm->vcpu);
 365                 rip = kvm_rip_read(&svm->vcpu);
 366                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 367                 svm->int3_injected = rip - old_rip;
 368         }
 369
 370         svm->vmcb->control.event_inj = nr
 371                 | SVM_EVTINJ_VALID
 372                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 373                 | SVM_EVTINJ_TYPE_EXEPT;
 374         svm->vmcb->control.event_inj_err = error_code;
 375 }
 376
 377 static int has_svm(void)
 378 {
 379         const char *msg;
 380
 381         if (!cpu_has_svm(&msg)) {
 382                 printk(KERN_INFO "has_svm: %s\n", msg);
 383                 return 0;
 384         }
 385
 386         return 1;
 387 }
 388
 389 static void svm_hardware_disable(void *garbage)
 390 {
 391         cpu_svm_disable();
 392 }
 393
 394 static int svm_hardware_enable(void *garbage)
 395 {
 396
 397         struct svm_cpu_data *sd;
 398         uint64_t efer;
 399         struct desc_ptr gdt_descr;
 400         struct desc_struct *gdt;
 401         int me = raw_smp_processor_id();
 402
 403         rdmsrl(MSR_EFER, efer);
 404         if (efer & EFER_SVME)
 405                 return -EBUSY;
 406
 407         if (!has_svm()) {
 408                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 409                        me);
 410                 return -EINVAL;
 411         }
 412         sd = per_cpu(svm_data, me);
 413
 414         if (!sd) {
 415                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 416                        me);
 417                 return -EINVAL;
 418         }
 419
 420         sd->asid_generation = 1;
 421         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 422         sd->next_asid = sd->max_asid + 1;
 423
 424         native_store_gdt(&gdt_descr);
 425         gdt = (struct desc_struct *)gdt_descr.address;
 426         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 427
 428         wrmsrl(MSR_EFER, efer | EFER_SVME);
 429
 430         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 431
 432         return 0;
 433 }
 434
 435 static void svm_cpu_uninit(int cpu)
 436 {
 437         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 438
 439         if (!sd)
 440                 return;
 441
 442         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 443         __free_page(sd->save_area);
 444         kfree(sd);
 445 }
 446
 447 static int svm_cpu_init(int cpu)
 448 {
 449         struct svm_cpu_data *sd;
 450         int r;
 451
 452         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 453         if (!sd)
 454                 return -ENOMEM;
 455         sd->cpu = cpu;
 456         sd->save_area = alloc_page(GFP_KERNEL);
 457         r = -ENOMEM;
 458         if (!sd->save_area)
 459                 goto err_1;
 460
 461         per_cpu(svm_data, cpu) = sd;
 462
 463         return 0;
 464
 465 err_1:
 466         kfree(sd);
 467         return r;
 468
 469 }
 470
 471 static bool valid_msr_intercept(u32 index)
 472 {
 473         int i;
 474
 475         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 476                 if (direct_access_msrs[i].index == index)
 477                         return true;
 478
 479         return false;
 480 }
 481
 482 static void set_msr_interception(u32 *msrpm, unsigned msr,
 483                                  int read, int write)
 484 {
 485         u8 bit_read, bit_write;
 486         unsigned long tmp;
 487         u32 offset;
 488
 489         /*
 490          * If this warning triggers extend the direct_access_msrs list at the
 491          * beginning of the file
 492          */
 493         WARN_ON(!valid_msr_intercept(msr));
 494
 495         offset    = svm_msrpm_offset(msr);
 496         bit_read  = 2 * (msr & 0x0f);
 497         bit_write = 2 * (msr & 0x0f) + 1;
 498         tmp       = msrpm[offset];
 499
 500         BUG_ON(offset == MSR_INVALID);
 501
 502         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 503         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 504
 505         msrpm[offset] = tmp;
 506 }
 507
 508 static void svm_vcpu_init_msrpm(u32 *msrpm)
 509 {
 510         int i;
 511
 512         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 513
 514         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 515                 if (!direct_access_msrs[i].always)
 516                         continue;
 517
 518                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 519         }
 520 }
 521
 522 static void add_msr_offset(u32 offset)
 523 {
 524         int i;
 525
 526         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 527
 528                 /* Offset already in list? */
 529                 if (msrpm_offsets[i] == offset)
 530                         return;
 531
 532                 /* Slot used by another offset? */
 533                 if (msrpm_offsets[i] != MSR_INVALID)
 534                         continue;
 535
 536                 /* Add offset to list */
 537                 msrpm_offsets[i] = offset;
 538
 539                 return;
 540         }
 541
 542         /*
 543          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 544          * increase MSRPM_OFFSETS in this case.
 545          */
 546         BUG();
 547 }
 548
 549 static void init_msrpm_offsets(void)
 550 {
 551         int i;
 552
 553         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 554
 555         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 556                 u32 offset;
 557
 558                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 559                 BUG_ON(offset == MSR_INVALID);
 560
 561                 add_msr_offset(offset);
 562         }
 563 }
 564
 565 static void svm_enable_lbrv(struct vcpu_svm *svm)
 566 {
 567         u32 *msrpm = svm->msrpm;
 568
 569         svm->vmcb->control.lbr_ctl = 1;
 570         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 571         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 572         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 573         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 574 }
 575
 576 static void svm_disable_lbrv(struct vcpu_svm *svm)
 577 {
 578         u32 *msrpm = svm->msrpm;
 579
 580         svm->vmcb->control.lbr_ctl = 0;
 581         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 582         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 583         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 584         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 585 }
 586
 587 static __init int svm_hardware_setup(void)
 588 {
 589         int cpu;
 590         struct page *iopm_pages;
 591         void *iopm_va;
 592         int r;
 593
 594         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 595
 596         if (!iopm_pages)
 597                 return -ENOMEM;
 598
 599         iopm_va = page_address(iopm_pages);
 600         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 601         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 602
 603         init_msrpm_offsets();
 604
 605         if (boot_cpu_has(X86_FEATURE_NX))
 606                 kvm_enable_efer_bits(EFER_NX);
 607
 608         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 609                 kvm_enable_efer_bits(EFER_FFXSR);
 610
 611         if (nested) {
 612                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 613                 kvm_enable_efer_bits(EFER_SVME);
 614         }
 615
 616         for_each_possible_cpu(cpu) {
 617                 r = svm_cpu_init(cpu);
 618                 if (r)
 619                         goto err;
 620         }
 621
 622         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 623
 624         if (!svm_has(SVM_FEATURE_NPT))
 625                 npt_enabled = false;
 626
 627         if (npt_enabled && !npt) {
 628                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 629                 npt_enabled = false;
 630         }
 631
 632         if (npt_enabled) {
 633                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 634                 kvm_enable_tdp();
 635         } else
 636                 kvm_disable_tdp();
 637
 638         return 0;
 639
 640 err:
 641         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 642         iopm_base = 0;
 643         return r;
 644 }
 645
 646 static __exit void svm_hardware_unsetup(void)
 647 {
 648         int cpu;
 649
 650         for_each_possible_cpu(cpu)
 651                 svm_cpu_uninit(cpu);
 652
 653         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 654         iopm_base = 0;
 655 }
 656
 657 static void init_seg(struct vmcb_seg *seg)
 658 {
 659         seg->selector = 0;
 660         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 661                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 662         seg->limit = 0xffff;
 663         seg->base = 0;
 664 }
 665
 666 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 667 {
 668         seg->selector = 0;
 669         seg->attrib = SVM_SELECTOR_P_MASK | type;
 670         seg->limit = 0xffff;
 671         seg->base = 0;
 672 }
 673
 674 static void init_vmcb(struct vcpu_svm *svm)
 675 {
 676         struct vmcb_control_area *control = &svm->vmcb->control;
 677         struct vmcb_save_area *save = &svm->vmcb->save;
 678
 679         svm->vcpu.fpu_active = 1;
 680
 681         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 682                                         INTERCEPT_CR3_MASK |
 683                                         INTERCEPT_CR4_MASK;
 684
 685         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 686                                         INTERCEPT_CR3_MASK |
 687                                         INTERCEPT_CR4_MASK |
 688                                         INTERCEPT_CR8_MASK;
 689
 690         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 691                                         INTERCEPT_DR1_MASK |
 692                                         INTERCEPT_DR2_MASK |
 693                                         INTERCEPT_DR3_MASK |
 694                                         INTERCEPT_DR4_MASK |
 695                                         INTERCEPT_DR5_MASK |
 696                                         INTERCEPT_DR6_MASK |
 697                                         INTERCEPT_DR7_MASK;
 698
 699         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 700                                         INTERCEPT_DR1_MASK |
 701                                         INTERCEPT_DR2_MASK |
 702                                         INTERCEPT_DR3_MASK |
 703                                         INTERCEPT_DR4_MASK |
 704                                         INTERCEPT_DR5_MASK |
 705                                         INTERCEPT_DR6_MASK |
 706                                         INTERCEPT_DR7_MASK;
 707
 708         control->intercept_exceptions = (1 << PF_VECTOR) |
 709                                         (1 << UD_VECTOR) |
 710                                         (1 << MC_VECTOR);
 711
 712
 713         control->intercept =    (1ULL << INTERCEPT_INTR) |
 714                                 (1ULL << INTERCEPT_NMI) |
 715                                 (1ULL << INTERCEPT_SMI) |
 716                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 717                                 (1ULL << INTERCEPT_CPUID) |
 718                                 (1ULL << INTERCEPT_INVD) |
 719                                 (1ULL << INTERCEPT_HLT) |
 720                                 (1ULL << INTERCEPT_INVLPG) |
 721                                 (1ULL << INTERCEPT_INVLPGA) |
 722                                 (1ULL << INTERCEPT_IOIO_PROT) |
 723                                 (1ULL << INTERCEPT_MSR_PROT) |
 724                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 725                                 (1ULL << INTERCEPT_SHUTDOWN) |
 726                                 (1ULL << INTERCEPT_VMRUN) |
 727                                 (1ULL << INTERCEPT_VMMCALL) |
 728                                 (1ULL << INTERCEPT_VMLOAD) |
 729                                 (1ULL << INTERCEPT_VMSAVE) |
 730                                 (1ULL << INTERCEPT_STGI) |
 731                                 (1ULL << INTERCEPT_CLGI) |
 732                                 (1ULL << INTERCEPT_SKINIT) |
 733                                 (1ULL << INTERCEPT_WBINVD) |
 734                                 (1ULL << INTERCEPT_MONITOR) |
 735                                 (1ULL << INTERCEPT_MWAIT);
 736
 737         control->iopm_base_pa = iopm_base;
 738         control->msrpm_base_pa = __pa(svm->msrpm);
 739         control->tsc_offset = 0;
 740         control->int_ctl = V_INTR_MASKING_MASK;
 741
 742         init_seg(&save->es);
 743         init_seg(&save->ss);
 744         init_seg(&save->ds);
 745         init_seg(&save->fs);
 746         init_seg(&save->gs);
 747
 748         save->cs.selector = 0xf000;
 749         /* Executable/Readable Code Segment */
 750         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 751                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 752         save->cs.limit = 0xffff;
 753         /*
 754          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 755          * be consistent with it.
 756          *
 757          * Replace when we have real mode working for vmx.
 758          */
 759         save->cs.base = 0xf0000;
 760
 761         save->gdtr.limit = 0xffff;
 762         save->idtr.limit = 0xffff;
 763
 764         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 765         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 766
 767         save->efer = EFER_SVME;
 768         save->dr6 = 0xffff0ff0;
 769         save->dr7 = 0x400;
 770         save->rflags = 2;
 771         save->rip = 0x0000fff0;
 772         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 773
 774         /*
 775          * This is the guest-visible cr0 value.
 776          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 777          */
 778         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 779         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 780
 781         save->cr4 = X86_CR4_PAE;
 782         /* rdx = ?? */
 783
 784         if (npt_enabled) {
 785                 /* Setup VMCB for Nested Paging */
 786                 control->nested_ctl = 1;
 787                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 788                                         (1ULL << INTERCEPT_INVLPG));
 789                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 790                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 791                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 792                 save->g_pat = 0x0007040600070406ULL;
 793                 save->cr3 = 0;
 794                 save->cr4 = 0;
 795         }
 796         force_new_asid(&svm->vcpu);
 797
 798         svm->nested.vmcb = 0;
 799         svm->vcpu.arch.hflags = 0;
 800
 801         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 802                 control->pause_filter_count = 3000;
 803                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 804         }
 805
 806         enable_gif(svm);
 807 }
 808
 809 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 810 {
 811         struct vcpu_svm *svm = to_svm(vcpu);
 812
 813         init_vmcb(svm);
 814
 815         if (!kvm_vcpu_is_bsp(vcpu)) {
 816                 kvm_rip_write(vcpu, 0);
 817                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 818                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 819         }
 820         vcpu->arch.regs_avail = ~0;
 821         vcpu->arch.regs_dirty = ~0;
 822
 823         return 0;
 824 }
 825
 826 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 827 {
 828         struct vcpu_svm *svm;
 829         struct page *page;
 830         struct page *msrpm_pages;
 831         struct page *hsave_page;
 832         struct page *nested_msrpm_pages;
 833         int err;
 834
 835         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 836         if (!svm) {
 837                 err = -ENOMEM;
 838                 goto out;
 839         }
 840
 841         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 842         if (err)
 843                 goto free_svm;
 844
 845         err = -ENOMEM;
 846         page = alloc_page(GFP_KERNEL);
 847         if (!page)
 848                 goto uninit;
 849
 850         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 851         if (!msrpm_pages)
 852                 goto free_page1;
 853
 854         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 855         if (!nested_msrpm_pages)
 856                 goto free_page2;
 857
 858         hsave_page = alloc_page(GFP_KERNEL);
 859         if (!hsave_page)
 860                 goto free_page3;
 861
 862         svm->nested.hsave = page_address(hsave_page);
 863
 864         svm->msrpm = page_address(msrpm_pages);
 865         svm_vcpu_init_msrpm(svm->msrpm);
 866
 867         svm->nested.msrpm = page_address(nested_msrpm_pages);
 868         svm_vcpu_init_msrpm(svm->nested.msrpm);
 869
 870         svm->vmcb = page_address(page);
 871         clear_page(svm->vmcb);
 872         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 873         svm->asid_generation = 0;
 874         init_vmcb(svm);
 875
 876         fx_init(&svm->vcpu);
 877         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 878         if (kvm_vcpu_is_bsp(&svm->vcpu))
 879                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 880
 881         return &svm->vcpu;
 882
 883 free_page3:
 884         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 885 free_page2:
 886         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 887 free_page1:
 888         __free_page(page);
 889 uninit:
 890         kvm_vcpu_uninit(&svm->vcpu);
 891 free_svm:
 892         kmem_cache_free(kvm_vcpu_cache, svm);
 893 out:
 894         return ERR_PTR(err);
 895 }
 896
 897 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 898 {
 899         struct vcpu_svm *svm = to_svm(vcpu);
 900
 901         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 902         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 903         __free_page(virt_to_page(svm->nested.hsave));
 904         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 905         kvm_vcpu_uninit(vcpu);
 906         kmem_cache_free(kvm_vcpu_cache, svm);
 907 }
 908
 909 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 910 {
 911         struct vcpu_svm *svm = to_svm(vcpu);
 912         int i;
 913
 914         if (unlikely(cpu != vcpu->cpu)) {
 915                 u64 delta;
 916
 917                 if (check_tsc_unstable()) {
 918                         /*
 919                          * Make sure that the guest sees a monotonically
 920                          * increasing TSC.
 921                          */
 922                         delta = vcpu->arch.host_tsc - native_read_tsc();
 923                         svm->vmcb->control.tsc_offset += delta;
 924                         if (is_nested(svm))
 925                                 svm->nested.hsave->control.tsc_offset += delta;
 926                 }
 927                 vcpu->cpu = cpu;
 928                 kvm_migrate_timers(vcpu);
 929                 svm->asid_generation = 0;
 930         }
 931
 932         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 933                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 934 }
 935
 936 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 937 {
 938         struct vcpu_svm *svm = to_svm(vcpu);
 939         int i;
 940
 941         ++vcpu->stat.host_state_reload;
 942         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 943                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 944
 945         vcpu->arch.host_tsc = native_read_tsc();
 946 }
 947
 948 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 949 {
 950         return to_svm(vcpu)->vmcb->save.rflags;
 951 }
 952
 953 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 954 {
 955         to_svm(vcpu)->vmcb->save.rflags = rflags;
 956 }
 957
 958 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 959 {
 960         switch (reg) {
 961         case VCPU_EXREG_PDPTR:
 962                 BUG_ON(!npt_enabled);
 963                 load_pdptrs(vcpu, vcpu->arch.cr3);
 964                 break;
 965         default:
 966                 BUG();
 967         }
 968 }
 969
 970 static void svm_set_vintr(struct vcpu_svm *svm)
 971 {
 972         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 973 }
 974
 975 static void svm_clear_vintr(struct vcpu_svm *svm)
 976 {
 977         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 978 }
 979
 980 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 981 {
 982         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 983
 984         switch (seg) {
 985         case VCPU_SREG_CS: return &save->cs;
 986         case VCPU_SREG_DS: return &save->ds;
 987         case VCPU_SREG_ES: return &save->es;
 988         case VCPU_SREG_FS: return &save->fs;
 989         case VCPU_SREG_GS: return &save->gs;
 990         case VCPU_SREG_SS: return &save->ss;
 991         case VCPU_SREG_TR: return &save->tr;
 992         case VCPU_SREG_LDTR: return &save->ldtr;
 993         }
 994         BUG();
 995         return NULL;
 996 }
 997
 998 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 999 {
1000         struct vmcb_seg *s = svm_seg(vcpu, seg);
1001
1002         return s->base;
1003 }
1004
1005 static void svm_get_segment(struct kvm_vcpu *vcpu,
1006                             struct kvm_segment *var, int seg)
1007 {
1008         struct vmcb_seg *s = svm_seg(vcpu, seg);
1009
1010         var->base = s->base;
1011         var->limit = s->limit;
1012         var->selector = s->selector;
1013         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1014         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1015         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1016         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1017         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1018         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1019         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1020         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1021
1022         /*
1023          * AMD's VMCB does not have an explicit unusable field, so emulate it
1024          * for cross vendor migration purposes by "not present"
1025          */
1026         var->unusable = !var->present || (var->type == 0);
1027
1028         switch (seg) {
1029         case VCPU_SREG_CS:
1030                 /*
1031                  * SVM always stores 0 for the 'G' bit in the CS selector in
1032                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1033                  * Intel's VMENTRY has a check on the 'G' bit.
1034                  */
1035                 var->g = s->limit > 0xfffff;
1036                 break;
1037         case VCPU_SREG_TR:
1038                 /*
1039                  * Work around a bug where the busy flag in the tr selector
1040                  * isn't exposed
1041                  */
1042                 var->type |= 0x2;
1043                 break;
1044         case VCPU_SREG_DS:
1045         case VCPU_SREG_ES:
1046         case VCPU_SREG_FS:
1047         case VCPU_SREG_GS:
1048                 /*
1049                  * The accessed bit must always be set in the segment
1050                  * descriptor cache, although it can be cleared in the
1051                  * descriptor, the cached bit always remains at 1. Since
1052                  * Intel has a check on this, set it here to support
1053                  * cross-vendor migration.
1054                  */
1055                 if (!var->unusable)
1056                         var->type |= 0x1;
1057                 break;
1058         case VCPU_SREG_SS:
1059                 /*
1060                  * On AMD CPUs sometimes the DB bit in the segment
1061                  * descriptor is left as 1, although the whole segment has
1062                  * been made unusable. Clear it here to pass an Intel VMX
1063                  * entry check when cross vendor migrating.
1064                  */
1065                 if (var->unusable)
1066                         var->db = 0;
1067                 break;
1068         }
1069 }
1070
1071 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1072 {
1073         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1074
1075         return save->cpl;
1076 }
1077
1078 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1079 {
1080         struct vcpu_svm *svm = to_svm(vcpu);
1081
1082         dt->size = svm->vmcb->save.idtr.limit;
1083         dt->address = svm->vmcb->save.idtr.base;
1084 }
1085
1086 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1087 {
1088         struct vcpu_svm *svm = to_svm(vcpu);
1089
1090         svm->vmcb->save.idtr.limit = dt->size;
1091         svm->vmcb->save.idtr.base = dt->address ;
1092 }
1093
1094 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1095 {
1096         struct vcpu_svm *svm = to_svm(vcpu);
1097
1098         dt->size = svm->vmcb->save.gdtr.limit;
1099         dt->address = svm->vmcb->save.gdtr.base;
1100 }
1101
1102 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1103 {
1104         struct vcpu_svm *svm = to_svm(vcpu);
1105
1106         svm->vmcb->save.gdtr.limit = dt->size;
1107         svm->vmcb->save.gdtr.base = dt->address ;
1108 }
1109
1110 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1111 {
1112 }
1113
1114 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1115 {
1116 }
1117
1118 static void update_cr0_intercept(struct vcpu_svm *svm)
1119 {
1120         struct vmcb *vmcb = svm->vmcb;
1121         ulong gcr0 = svm->vcpu.arch.cr0;
1122         u64 *hcr0 = &svm->vmcb->save.cr0;
1123
1124         if (!svm->vcpu.fpu_active)
1125                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1126         else
1127                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1128                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1129
1130
1131         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1132                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1133                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1134                 if (is_nested(svm)) {
1135                         struct vmcb *hsave = svm->nested.hsave;
1136
1137                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1138                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1139                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1140                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1141                 }
1142         } else {
1143                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1144                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1145                 if (is_nested(svm)) {
1146                         struct vmcb *hsave = svm->nested.hsave;
1147
1148                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1149                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1150                 }
1151         }
1152 }
1153
1154 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1155 {
1156         struct vcpu_svm *svm = to_svm(vcpu);
1157
1158         if (is_nested(svm)) {
1159                 /*
1160                  * We are here because we run in nested mode, the host kvm
1161                  * intercepts cr0 writes but the l1 hypervisor does not.
1162                  * But the L1 hypervisor may intercept selective cr0 writes.
1163                  * This needs to be checked here.
1164                  */
1165                 unsigned long old, new;
1166
1167                 /* Remove bits that would trigger a real cr0 write intercept */
1168                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1169                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1170
1171                 if (old == new) {
1172                         /* cr0 write with ts and mp unchanged */
1173                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1174                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1175                                 return;
1176                 }
1177         }
1178
1179 #ifdef CONFIG_X86_64
1180         if (vcpu->arch.efer & EFER_LME) {
1181                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1182                         vcpu->arch.efer |= EFER_LMA;
1183                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1184                 }
1185
1186                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1187                         vcpu->arch.efer &= ~EFER_LMA;
1188                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1189                 }
1190         }
1191 #endif
1192         vcpu->arch.cr0 = cr0;
1193
1194         if (!npt_enabled)
1195                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1196
1197         if (!vcpu->fpu_active)
1198                 cr0 |= X86_CR0_TS;
1199         /*
1200          * re-enable caching here because the QEMU bios
1201          * does not do it - this results in some delay at
1202          * reboot
1203          */
1204         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1205         svm->vmcb->save.cr0 = cr0;
1206         update_cr0_intercept(svm);
1207 }
1208
1209 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1210 {
1211         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1212         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1213
1214         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1215                 force_new_asid(vcpu);
1216
1217         vcpu->arch.cr4 = cr4;
1218         if (!npt_enabled)
1219                 cr4 |= X86_CR4_PAE;
1220         cr4 |= host_cr4_mce;
1221         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1222 }
1223
1224 static void svm_set_segment(struct kvm_vcpu *vcpu,
1225                             struct kvm_segment *var, int seg)
1226 {
1227         struct vcpu_svm *svm = to_svm(vcpu);
1228         struct vmcb_seg *s = svm_seg(vcpu, seg);
1229
1230         s->base = var->base;
1231         s->limit = var->limit;
1232         s->selector = var->selector;
1233         if (var->unusable)
1234                 s->attrib = 0;
1235         else {
1236                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1237                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1238                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1239                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1240                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1241                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1242                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1243                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1244         }
1245         if (seg == VCPU_SREG_CS)
1246                 svm->vmcb->save.cpl
1247                         = (svm->vmcb->save.cs.attrib
1248                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1249
1250 }
1251
1252 static void update_db_intercept(struct kvm_vcpu *vcpu)
1253 {
1254         struct vcpu_svm *svm = to_svm(vcpu);
1255
1256         svm->vmcb->control.intercept_exceptions &=
1257                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1258
1259         if (svm->nmi_singlestep)
1260                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1261
1262         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1263                 if (vcpu->guest_debug &
1264                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1265                         svm->vmcb->control.intercept_exceptions |=
1266                                 1 << DB_VECTOR;
1267                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1268                         svm->vmcb->control.intercept_exceptions |=
1269                                 1 << BP_VECTOR;
1270         } else
1271                 vcpu->guest_debug = 0;
1272 }
1273
1274 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1275 {
1276         struct vcpu_svm *svm = to_svm(vcpu);
1277
1278         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1279                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1280         else
1281                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1282
1283         update_db_intercept(vcpu);
1284 }
1285
1286 static void load_host_msrs(struct kvm_vcpu *vcpu)
1287 {
1288 #ifdef CONFIG_X86_64
1289         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1290 #endif
1291 }
1292
1293 static void save_host_msrs(struct kvm_vcpu *vcpu)
1294 {
1295 #ifdef CONFIG_X86_64
1296         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1297 #endif
1298 }
1299
1300 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1301 {
1302         if (sd->next_asid > sd->max_asid) {
1303                 ++sd->asid_generation;
1304                 sd->next_asid = 1;
1305                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1306         }
1307
1308         svm->asid_generation = sd->asid_generation;
1309         svm->vmcb->control.asid = sd->next_asid++;
1310 }
1311
1312 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1313 {
1314         struct vcpu_svm *svm = to_svm(vcpu);
1315
1316         svm->vmcb->save.dr7 = value;
1317 }
1318
1319 static int pf_interception(struct vcpu_svm *svm)
1320 {
1321         u64 fault_address;
1322         u32 error_code;
1323
1324         fault_address  = svm->vmcb->control.exit_info_2;
1325         error_code = svm->vmcb->control.exit_info_1;
1326
1327         trace_kvm_page_fault(fault_address, error_code);
1328         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1329                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1330         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1331 }
1332
1333 static int db_interception(struct vcpu_svm *svm)
1334 {
1335         struct kvm_run *kvm_run = svm->vcpu.run;
1336
1337         if (!(svm->vcpu.guest_debug &
1338               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1339                 !svm->nmi_singlestep) {
1340                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1341                 return 1;
1342         }
1343
1344         if (svm->nmi_singlestep) {
1345                 svm->nmi_singlestep = false;
1346                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1347                         svm->vmcb->save.rflags &=
1348                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1349                 update_db_intercept(&svm->vcpu);
1350         }
1351
1352         if (svm->vcpu.guest_debug &
1353             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1354                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1355                 kvm_run->debug.arch.pc =
1356                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1357                 kvm_run->debug.arch.exception = DB_VECTOR;
1358                 return 0;
1359         }
1360
1361         return 1;
1362 }
1363
1364 static int bp_interception(struct vcpu_svm *svm)
1365 {
1366         struct kvm_run *kvm_run = svm->vcpu.run;
1367
1368         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1369         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1370         kvm_run->debug.arch.exception = BP_VECTOR;
1371         return 0;
1372 }
1373
1374 static int ud_interception(struct vcpu_svm *svm)
1375 {
1376         int er;
1377
1378         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1379         if (er != EMULATE_DONE)
1380                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1381         return 1;
1382 }
1383
1384 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1385 {
1386         struct vcpu_svm *svm = to_svm(vcpu);
1387         u32 excp;
1388
1389         if (is_nested(svm)) {
1390                 u32 h_excp, n_excp;
1391
1392                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1393                 n_excp  = svm->nested.intercept_exceptions;
1394                 h_excp &= ~(1 << NM_VECTOR);
1395                 excp    = h_excp | n_excp;
1396         } else {
1397                 excp  = svm->vmcb->control.intercept_exceptions;
1398                 excp &= ~(1 << NM_VECTOR);
1399         }
1400
1401         svm->vmcb->control.intercept_exceptions = excp;
1402
1403         svm->vcpu.fpu_active = 1;
1404         update_cr0_intercept(svm);
1405 }
1406
1407 static int nm_interception(struct vcpu_svm *svm)
1408 {
1409         svm_fpu_activate(&svm->vcpu);
1410         return 1;
1411 }
1412
1413 static void svm_handle_mce(struct vcpu_svm *svm)
1414 {
1415         /*
1416          * On an #MC intercept the MCE handler is not called automatically in
1417          * the host. So do it by hand here.
1418          */
1419         asm volatile (
1420                 "int $0x12\n");
1421         /* not sure if we ever come back to this point */
1422
1423         return;
1424 }
1425
1426 static int mc_interception(struct vcpu_svm *svm)
1427 {
1428         return 1;
1429 }
1430
1431 static int shutdown_interception(struct vcpu_svm *svm)
1432 {
1433         struct kvm_run *kvm_run = svm->vcpu.run;
1434
1435         /*
1436          * VMCB is undefined after a SHUTDOWN intercept
1437          * so reinitialize it.
1438          */
1439         clear_page(svm->vmcb);
1440         init_vmcb(svm);
1441
1442         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1443         return 0;
1444 }
1445
1446 static int io_interception(struct vcpu_svm *svm)
1447 {
1448         struct kvm_vcpu *vcpu = &svm->vcpu;
1449         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1450         int size, in, string;
1451         unsigned port;
1452
1453         ++svm->vcpu.stat.io_exits;
1454         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1455         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1456         if (string || in)
1457                 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
1458
1459         port = io_info >> 16;
1460         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1461         svm->next_rip = svm->vmcb->control.exit_info_2;
1462         skip_emulated_instruction(&svm->vcpu);
1463
1464         return kvm_fast_pio_out(vcpu, size, port);
1465 }
1466
1467 static int nmi_interception(struct vcpu_svm *svm)
1468 {
1469         return 1;
1470 }
1471
1472 static int intr_interception(struct vcpu_svm *svm)
1473 {
1474         ++svm->vcpu.stat.irq_exits;
1475         return 1;
1476 }
1477
1478 static int nop_on_interception(struct vcpu_svm *svm)
1479 {
1480         return 1;
1481 }
1482
1483 static int halt_interception(struct vcpu_svm *svm)
1484 {
1485         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1486         skip_emulated_instruction(&svm->vcpu);
1487         return kvm_emulate_halt(&svm->vcpu);
1488 }
1489
1490 static int vmmcall_interception(struct vcpu_svm *svm)
1491 {
1492         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1493         skip_emulated_instruction(&svm->vcpu);
1494         kvm_emulate_hypercall(&svm->vcpu);
1495         return 1;
1496 }
1497
1498 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1499 {
1500         if (!(svm->vcpu.arch.efer & EFER_SVME)
1501             || !is_paging(&svm->vcpu)) {
1502                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1503                 return 1;
1504         }
1505
1506         if (svm->vmcb->save.cpl) {
1507                 kvm_inject_gp(&svm->vcpu, 0);
1508                 return 1;
1509         }
1510
1511        return 0;
1512 }
1513
1514 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1515                                       bool has_error_code, u32 error_code)
1516 {
1517         int vmexit;
1518
1519         if (!is_nested(svm))
1520                 return 0;
1521
1522         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1523         svm->vmcb->control.exit_code_hi = 0;
1524         svm->vmcb->control.exit_info_1 = error_code;
1525         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1526
1527         vmexit = nested_svm_intercept(svm);
1528         if (vmexit == NESTED_EXIT_DONE)
1529                 svm->nested.exit_required = true;
1530
1531         return vmexit;
1532 }
1533
1534 /* This function returns true if it is save to enable the irq window */
1535 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1536 {
1537         if (!is_nested(svm))
1538                 return true;
1539
1540         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1541                 return true;
1542
1543         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1544                 return false;
1545
1546         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1547         svm->vmcb->control.exit_info_1 = 0;
1548         svm->vmcb->control.exit_info_2 = 0;
1549
1550         if (svm->nested.intercept & 1ULL) {
1551                 /*
1552                  * The #vmexit can't be emulated here directly because this
1553                  * code path runs with irqs and preemtion disabled. A
1554                  * #vmexit emulation might sleep. Only signal request for
1555                  * the #vmexit here.
1556                  */
1557                 svm->nested.exit_required = true;
1558                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1559                 return false;
1560         }
1561
1562         return true;
1563 }
1564
1565 /* This function returns true if it is save to enable the nmi window */
1566 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1567 {
1568         if (!is_nested(svm))
1569                 return true;
1570
1571         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1572                 return true;
1573
1574         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1575         svm->nested.exit_required = true;
1576
1577         return false;
1578 }
1579
1580 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1581 {
1582         struct page *page;
1583
1584         might_sleep();
1585
1586         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1587         if (is_error_page(page))
1588                 goto error;
1589
1590         *_page = page;
1591
1592         return kmap(page);
1593
1594 error:
1595         kvm_release_page_clean(page);
1596         kvm_inject_gp(&svm->vcpu, 0);
1597
1598         return NULL;
1599 }
1600
1601 static void nested_svm_unmap(struct page *page)
1602 {
1603         kunmap(page);
1604         kvm_release_page_dirty(page);
1605 }
1606
1607 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1608 {
1609         unsigned port;
1610         u8 val, bit;
1611         u64 gpa;
1612
1613         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1614                 return NESTED_EXIT_HOST;
1615
1616         port = svm->vmcb->control.exit_info_1 >> 16;
1617         gpa  = svm->nested.vmcb_iopm + (port / 8);
1618         bit  = port % 8;
1619         val  = 0;
1620
1621         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1622                 val &= (1 << bit);
1623
1624         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1625 }
1626
1627 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1628 {
1629         u32 offset, msr, value;
1630         int write, mask;
1631
1632         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1633                 return NESTED_EXIT_HOST;
1634
1635         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1636         offset = svm_msrpm_offset(msr);
1637         write  = svm->vmcb->control.exit_info_1 & 1;
1638         mask   = 1 << ((2 * (msr & 0xf)) + write);
1639
1640         if (offset == MSR_INVALID)
1641                 return NESTED_EXIT_DONE;
1642
1643         /* Offset is in 32 bit units but need in 8 bit units */
1644         offset *= 4;
1645
1646         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1647                 return NESTED_EXIT_DONE;
1648
1649         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1650 }
1651
1652 static int nested_svm_exit_special(struct vcpu_svm *svm)
1653 {
1654         u32 exit_code = svm->vmcb->control.exit_code;
1655
1656         switch (exit_code) {
1657         case SVM_EXIT_INTR:
1658         case SVM_EXIT_NMI:
1659         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1660                 return NESTED_EXIT_HOST;
1661         case SVM_EXIT_NPF:
1662                 /* For now we are always handling NPFs when using them */
1663                 if (npt_enabled)
1664                         return NESTED_EXIT_HOST;
1665                 break;
1666         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1667                 /* When we're shadowing, trap PFs */
1668                 if (!npt_enabled)
1669                         return NESTED_EXIT_HOST;
1670                 break;
1671         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1672                 nm_interception(svm);
1673                 break;
1674         default:
1675                 break;
1676         }
1677
1678         return NESTED_EXIT_CONTINUE;
1679 }
1680
1681 /*
1682  * If this function returns true, this #vmexit was already handled
1683  */
1684 static int nested_svm_intercept(struct vcpu_svm *svm)
1685 {
1686         u32 exit_code = svm->vmcb->control.exit_code;
1687         int vmexit = NESTED_EXIT_HOST;
1688
1689         switch (exit_code) {
1690         case SVM_EXIT_MSR:
1691                 vmexit = nested_svm_exit_handled_msr(svm);
1692                 break;
1693         case SVM_EXIT_IOIO:
1694                 vmexit = nested_svm_intercept_ioio(svm);
1695                 break;
1696         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1697                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1698                 if (svm->nested.intercept_cr_read & cr_bits)
1699                         vmexit = NESTED_EXIT_DONE;
1700                 break;
1701         }
1702         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1703                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1704                 if (svm->nested.intercept_cr_write & cr_bits)
1705                         vmexit = NESTED_EXIT_DONE;
1706                 break;
1707         }
1708         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1709                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1710                 if (svm->nested.intercept_dr_read & dr_bits)
1711                         vmexit = NESTED_EXIT_DONE;
1712                 break;
1713         }
1714         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1715                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1716                 if (svm->nested.intercept_dr_write & dr_bits)
1717                         vmexit = NESTED_EXIT_DONE;
1718                 break;
1719         }
1720         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1721                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1722                 if (svm->nested.intercept_exceptions & excp_bits)
1723                         vmexit = NESTED_EXIT_DONE;
1724                 break;
1725         }
1726         case SVM_EXIT_ERR: {
1727                 vmexit = NESTED_EXIT_DONE;
1728                 break;
1729         }
1730         default: {
1731                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1732                 if (svm->nested.intercept & exit_bits)
1733                         vmexit = NESTED_EXIT_DONE;
1734         }
1735         }
1736
1737         return vmexit;
1738 }
1739
1740 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1741 {
1742         int vmexit;
1743
1744         vmexit = nested_svm_intercept(svm);
1745
1746         if (vmexit == NESTED_EXIT_DONE)
1747                 nested_svm_vmexit(svm);
1748
1749         return vmexit;
1750 }
1751
1752 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1753 {
1754         struct vmcb_control_area *dst  = &dst_vmcb->control;
1755         struct vmcb_control_area *from = &from_vmcb->control;
1756
1757         dst->intercept_cr_read    = from->intercept_cr_read;
1758         dst->intercept_cr_write   = from->intercept_cr_write;
1759         dst->intercept_dr_read    = from->intercept_dr_read;
1760         dst->intercept_dr_write   = from->intercept_dr_write;
1761         dst->intercept_exceptions = from->intercept_exceptions;
1762         dst->intercept            = from->intercept;
1763         dst->iopm_base_pa         = from->iopm_base_pa;
1764         dst->msrpm_base_pa        = from->msrpm_base_pa;
1765         dst->tsc_offset           = from->tsc_offset;
1766         dst->asid                 = from->asid;
1767         dst->tlb_ctl              = from->tlb_ctl;
1768         dst->int_ctl              = from->int_ctl;
1769         dst->int_vector           = from->int_vector;
1770         dst->int_state            = from->int_state;
1771         dst->exit_code            = from->exit_code;
1772         dst->exit_code_hi         = from->exit_code_hi;
1773         dst->exit_info_1          = from->exit_info_1;
1774         dst->exit_info_2          = from->exit_info_2;
1775         dst->exit_int_info        = from->exit_int_info;
1776         dst->exit_int_info_err    = from->exit_int_info_err;
1777         dst->nested_ctl           = from->nested_ctl;
1778         dst->event_inj            = from->event_inj;
1779         dst->event_inj_err        = from->event_inj_err;
1780         dst->nested_cr3           = from->nested_cr3;
1781         dst->lbr_ctl              = from->lbr_ctl;
1782 }
1783
1784 static int nested_svm_vmexit(struct vcpu_svm *svm)
1785 {
1786         struct vmcb *nested_vmcb;
1787         struct vmcb *hsave = svm->nested.hsave;
1788         struct vmcb *vmcb = svm->vmcb;
1789         struct page *page;
1790
1791         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1792                                        vmcb->control.exit_info_1,
1793                                        vmcb->control.exit_info_2,
1794                                        vmcb->control.exit_int_info,
1795                                        vmcb->control.exit_int_info_err);
1796
1797         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1798         if (!nested_vmcb)
1799                 return 1;
1800
1801         /* Exit nested SVM mode */
1802         svm->nested.vmcb = 0;
1803
1804         /* Give the current vmcb to the guest */
1805         disable_gif(svm);
1806
1807         nested_vmcb->save.es     = vmcb->save.es;
1808         nested_vmcb->save.cs     = vmcb->save.cs;
1809         nested_vmcb->save.ss     = vmcb->save.ss;
1810         nested_vmcb->save.ds     = vmcb->save.ds;
1811         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1812         nested_vmcb->save.idtr   = vmcb->save.idtr;
1813         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1814         nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1815         nested_vmcb->save.cr2    = vmcb->save.cr2;
1816         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1817         nested_vmcb->save.rflags = vmcb->save.rflags;
1818         nested_vmcb->save.rip    = vmcb->save.rip;
1819         nested_vmcb->save.rsp    = vmcb->save.rsp;
1820         nested_vmcb->save.rax    = vmcb->save.rax;
1821         nested_vmcb->save.dr7    = vmcb->save.dr7;
1822         nested_vmcb->save.dr6    = vmcb->save.dr6;
1823         nested_vmcb->save.cpl    = vmcb->save.cpl;
1824
1825         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1826         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1827         nested_vmcb->control.int_state         = vmcb->control.int_state;
1828         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1829         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1830         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1831         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1832         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1833         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1834
1835         /*
1836          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1837          * to make sure that we do not lose injected events. So check event_inj
1838          * here and copy it to exit_int_info if it is valid.
1839          * Exit_int_info and event_inj can't be both valid because the case
1840          * below only happens on a VMRUN instruction intercept which has
1841          * no valid exit_int_info set.
1842          */
1843         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1844                 struct vmcb_control_area *nc = &nested_vmcb->control;
1845
1846                 nc->exit_int_info     = vmcb->control.event_inj;
1847                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1848         }
1849
1850         nested_vmcb->control.tlb_ctl           = 0;
1851         nested_vmcb->control.event_inj         = 0;
1852         nested_vmcb->control.event_inj_err     = 0;
1853
1854         /* We always set V_INTR_MASKING and remember the old value in hflags */
1855         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1856                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1857
1858         /* Restore the original control entries */
1859         copy_vmcb_control_area(vmcb, hsave);
1860
1861         kvm_clear_exception_queue(&svm->vcpu);
1862         kvm_clear_interrupt_queue(&svm->vcpu);
1863
1864         /* Restore selected save entries */
1865         svm->vmcb->save.es = hsave->save.es;
1866         svm->vmcb->save.cs = hsave->save.cs;
1867         svm->vmcb->save.ss = hsave->save.ss;
1868         svm->vmcb->save.ds = hsave->save.ds;
1869         svm->vmcb->save.gdtr = hsave->save.gdtr;
1870         svm->vmcb->save.idtr = hsave->save.idtr;
1871         svm->vmcb->save.rflags = hsave->save.rflags;
1872         svm_set_efer(&svm->vcpu, hsave->save.efer);
1873         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1874         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1875         if (npt_enabled) {
1876                 svm->vmcb->save.cr3 = hsave->save.cr3;
1877                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1878         } else {
1879                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1880         }
1881         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1882         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1883         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1884         svm->vmcb->save.dr7 = 0;
1885         svm->vmcb->save.cpl = 0;
1886         svm->vmcb->control.exit_int_info = 0;
1887
1888         nested_svm_unmap(page);
1889
1890         kvm_mmu_reset_context(&svm->vcpu);
1891         kvm_mmu_load(&svm->vcpu);
1892
1893         return 0;
1894 }
1895
1896 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1897 {
1898         /*
1899          * This function merges the msr permission bitmaps of kvm and the
1900          * nested vmcb. It is omptimized in that it only merges the parts where
1901          * the kvm msr permission bitmap may contain zero bits
1902          */
1903         int i;
1904
1905         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1906                 return true;
1907
1908         for (i = 0; i < MSRPM_OFFSETS; i++) {
1909                 u32 value, p;
1910                 u64 offset;
1911
1912                 if (msrpm_offsets[i] == 0xffffffff)
1913                         break;
1914
1915                 p      = msrpm_offsets[i];
1916                 offset = svm->nested.vmcb_msrpm + (p * 4);
1917
1918                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
1919                         return false;
1920
1921                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
1922         }
1923
1924         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1925
1926         return true;
1927 }
1928
1929 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1930 {
1931         struct vmcb *nested_vmcb;
1932         struct vmcb *hsave = svm->nested.hsave;
1933         struct vmcb *vmcb = svm->vmcb;
1934         struct page *page;
1935         u64 vmcb_gpa;
1936
1937         vmcb_gpa = svm->vmcb->save.rax;
1938
1939         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1940         if (!nested_vmcb)
1941                 return false;
1942
1943         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
1944                                nested_vmcb->save.rip,
1945                                nested_vmcb->control.int_ctl,
1946                                nested_vmcb->control.event_inj,
1947                                nested_vmcb->control.nested_ctl);
1948
1949         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
1950                                     nested_vmcb->control.intercept_cr_write,
1951                                     nested_vmcb->control.intercept_exceptions,
1952                                     nested_vmcb->control.intercept);
1953
1954         /* Clear internal status */
1955         kvm_clear_exception_queue(&svm->vcpu);
1956         kvm_clear_interrupt_queue(&svm->vcpu);
1957
1958         /*
1959          * Save the old vmcb, so we don't need to pick what we save, but can
1960          * restore everything when a VMEXIT occurs
1961          */
1962         hsave->save.es     = vmcb->save.es;
1963         hsave->save.cs     = vmcb->save.cs;
1964         hsave->save.ss     = vmcb->save.ss;
1965         hsave->save.ds     = vmcb->save.ds;
1966         hsave->save.gdtr   = vmcb->save.gdtr;
1967         hsave->save.idtr   = vmcb->save.idtr;
1968         hsave->save.efer   = svm->vcpu.arch.efer;
1969         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
1970         hsave->save.cr4    = svm->vcpu.arch.cr4;
1971         hsave->save.rflags = vmcb->save.rflags;
1972         hsave->save.rip    = svm->next_rip;
1973         hsave->save.rsp    = vmcb->save.rsp;
1974         hsave->save.rax    = vmcb->save.rax;
1975         if (npt_enabled)
1976                 hsave->save.cr3    = vmcb->save.cr3;
1977         else
1978                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1979
1980         copy_vmcb_control_area(hsave, vmcb);
1981
1982         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1983                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1984         else
1985                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1986
1987         /* Load the nested guest state */
1988         svm->vmcb->save.es = nested_vmcb->save.es;
1989         svm->vmcb->save.cs = nested_vmcb->save.cs;
1990         svm->vmcb->save.ss = nested_vmcb->save.ss;
1991         svm->vmcb->save.ds = nested_vmcb->save.ds;
1992         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1993         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1994         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1995         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1996         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1997         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1998         if (npt_enabled) {
1999                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2000                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2001         } else
2002                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2003
2004         /* Guest paging mode is active - reset mmu */
2005         kvm_mmu_reset_context(&svm->vcpu);
2006
2007         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2008         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2009         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2010         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2011
2012         /* In case we don't even reach vcpu_run, the fields are not updated */
2013         svm->vmcb->save.rax = nested_vmcb->save.rax;
2014         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2015         svm->vmcb->save.rip = nested_vmcb->save.rip;
2016         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2017         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2018         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2019
2020         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2021         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2022
2023         /* cache intercepts */
2024         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
2025         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
2026         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
2027         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
2028         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2029         svm->nested.intercept            = nested_vmcb->control.intercept;
2030
2031         force_new_asid(&svm->vcpu);
2032         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2033         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2034                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2035         else
2036                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2037
2038         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2039                 /* We only want the cr8 intercept bits of the guest */
2040                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2041                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2042         }
2043
2044         /* We don't want to see VMMCALLs from a nested guest */
2045         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2046
2047         /*
2048          * We don't want a nested guest to be more powerful than the guest, so
2049          * all intercepts are ORed
2050          */
2051         svm->vmcb->control.intercept_cr_read |=
2052                 nested_vmcb->control.intercept_cr_read;
2053         svm->vmcb->control.intercept_cr_write |=
2054                 nested_vmcb->control.intercept_cr_write;
2055         svm->vmcb->control.intercept_dr_read |=
2056                 nested_vmcb->control.intercept_dr_read;
2057         svm->vmcb->control.intercept_dr_write |=
2058                 nested_vmcb->control.intercept_dr_write;
2059         svm->vmcb->control.intercept_exceptions |=
2060                 nested_vmcb->control.intercept_exceptions;
2061
2062         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2063
2064         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2065         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2066         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2067         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2068         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2069         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2070
2071         nested_svm_unmap(page);
2072
2073         /* nested_vmcb is our indicator if nested SVM is activated */
2074         svm->nested.vmcb = vmcb_gpa;
2075
2076         enable_gif(svm);
2077
2078         return true;
2079 }
2080
2081 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2082 {
2083         to_vmcb->save.fs = from_vmcb->save.fs;
2084         to_vmcb->save.gs = from_vmcb->save.gs;
2085         to_vmcb->save.tr = from_vmcb->save.tr;
2086         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2087         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2088         to_vmcb->save.star = from_vmcb->save.star;
2089         to_vmcb->save.lstar = from_vmcb->save.lstar;
2090         to_vmcb->save.cstar = from_vmcb->save.cstar;
2091         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2092         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2093         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2094         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2095 }
2096
2097 static int vmload_interception(struct vcpu_svm *svm)
2098 {
2099         struct vmcb *nested_vmcb;
2100         struct page *page;
2101
2102         if (nested_svm_check_permissions(svm))
2103                 return 1;
2104
2105         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2106         skip_emulated_instruction(&svm->vcpu);
2107
2108         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2109         if (!nested_vmcb)
2110                 return 1;
2111
2112         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2113         nested_svm_unmap(page);
2114
2115         return 1;
2116 }
2117
2118 static int vmsave_interception(struct vcpu_svm *svm)
2119 {
2120         struct vmcb *nested_vmcb;
2121         struct page *page;
2122
2123         if (nested_svm_check_permissions(svm))
2124                 return 1;
2125
2126         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2127         skip_emulated_instruction(&svm->vcpu);
2128
2129         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2130         if (!nested_vmcb)
2131                 return 1;
2132
2133         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2134         nested_svm_unmap(page);
2135
2136         return 1;
2137 }
2138
2139 static int vmrun_interception(struct vcpu_svm *svm)
2140 {
2141         if (nested_svm_check_permissions(svm))
2142                 return 1;
2143
2144         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2145         skip_emulated_instruction(&svm->vcpu);
2146
2147         if (!nested_svm_vmrun(svm))
2148                 return 1;
2149
2150         if (!nested_svm_vmrun_msrpm(svm))
2151                 goto failed;
2152
2153         return 1;
2154
2155 failed:
2156
2157         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2158         svm->vmcb->control.exit_code_hi = 0;
2159         svm->vmcb->control.exit_info_1  = 0;
2160         svm->vmcb->control.exit_info_2  = 0;
2161
2162         nested_svm_vmexit(svm);
2163
2164         return 1;
2165 }
2166
2167 static int stgi_interception(struct vcpu_svm *svm)
2168 {
2169         if (nested_svm_check_permissions(svm))
2170                 return 1;
2171
2172         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2173         skip_emulated_instruction(&svm->vcpu);
2174
2175         enable_gif(svm);
2176
2177         return 1;
2178 }
2179
2180 static int clgi_interception(struct vcpu_svm *svm)
2181 {
2182         if (nested_svm_check_permissions(svm))
2183                 return 1;
2184
2185         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2186         skip_emulated_instruction(&svm->vcpu);
2187
2188         disable_gif(svm);
2189
2190         /* After a CLGI no interrupts should come */
2191         svm_clear_vintr(svm);
2192         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2193
2194         return 1;
2195 }
2196
2197 static int invlpga_interception(struct vcpu_svm *svm)
2198 {
2199         struct kvm_vcpu *vcpu = &svm->vcpu;
2200
2201         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2202                           vcpu->arch.regs[VCPU_REGS_RAX]);
2203
2204         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2205         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2206
2207         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2208         skip_emulated_instruction(&svm->vcpu);
2209         return 1;
2210 }
2211
2212 static int skinit_interception(struct vcpu_svm *svm)
2213 {
2214         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2215
2216         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2217         return 1;
2218 }
2219
2220 static int invalid_op_interception(struct vcpu_svm *svm)
2221 {
2222         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2223         return 1;
2224 }
2225
2226 static int task_switch_interception(struct vcpu_svm *svm)
2227 {
2228         u16 tss_selector;
2229         int reason;
2230         int int_type = svm->vmcb->control.exit_int_info &
2231                 SVM_EXITINTINFO_TYPE_MASK;
2232         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2233         uint32_t type =
2234                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2235         uint32_t idt_v =
2236                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2237         bool has_error_code = false;
2238         u32 error_code = 0;
2239
2240         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2241
2242         if (svm->vmcb->control.exit_info_2 &
2243             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2244                 reason = TASK_SWITCH_IRET;
2245         else if (svm->vmcb->control.exit_info_2 &
2246                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2247                 reason = TASK_SWITCH_JMP;
2248         else if (idt_v)
2249                 reason = TASK_SWITCH_GATE;
2250         else
2251                 reason = TASK_SWITCH_CALL;
2252
2253         if (reason == TASK_SWITCH_GATE) {
2254                 switch (type) {
2255                 case SVM_EXITINTINFO_TYPE_NMI:
2256                         svm->vcpu.arch.nmi_injected = false;
2257                         break;
2258                 case SVM_EXITINTINFO_TYPE_EXEPT:
2259                         if (svm->vmcb->control.exit_info_2 &
2260                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2261                                 has_error_code = true;
2262                                 error_code =
2263                                         (u32)svm->vmcb->control.exit_info_2;
2264                         }
2265                         kvm_clear_exception_queue(&svm->vcpu);
2266                         break;
2267                 case SVM_EXITINTINFO_TYPE_INTR:
2268                         kvm_clear_interrupt_queue(&svm->vcpu);
2269                         break;
2270                 default:
2271                         break;
2272                 }
2273         }
2274
2275         if (reason != TASK_SWITCH_GATE ||
2276             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2277             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2278              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2279                 skip_emulated_instruction(&svm->vcpu);
2280
2281         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2282                                 has_error_code, error_code) == EMULATE_FAIL) {
2283                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2284                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2285                 svm->vcpu.run->internal.ndata = 0;
2286                 return 0;
2287         }
2288         return 1;
2289 }
2290
2291 static int cpuid_interception(struct vcpu_svm *svm)
2292 {
2293         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2294         kvm_emulate_cpuid(&svm->vcpu);
2295         return 1;
2296 }
2297
2298 static int iret_interception(struct vcpu_svm *svm)
2299 {
2300         ++svm->vcpu.stat.nmi_window_exits;
2301         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2302         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2303         return 1;
2304 }
2305
2306 static int invlpg_interception(struct vcpu_svm *svm)
2307 {
2308         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2309                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2310         return 1;
2311 }
2312
2313 static int emulate_on_interception(struct vcpu_svm *svm)
2314 {
2315         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2316                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2317         return 1;
2318 }
2319
2320 static int cr8_write_interception(struct vcpu_svm *svm)
2321 {
2322         struct kvm_run *kvm_run = svm->vcpu.run;
2323
2324         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2325         /* instruction emulation calls kvm_set_cr8() */
2326         emulate_instruction(&svm->vcpu, 0, 0, 0);
2327         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2328                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2329                 return 1;
2330         }
2331         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2332                 return 1;
2333         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2334         return 0;
2335 }
2336
2337 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2338 {
2339         struct vcpu_svm *svm = to_svm(vcpu);
2340
2341         switch (ecx) {
2342         case MSR_IA32_TSC: {
2343                 u64 tsc_offset;
2344
2345                 if (is_nested(svm))
2346                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2347                 else
2348                         tsc_offset = svm->vmcb->control.tsc_offset;
2349
2350                 *data = tsc_offset + native_read_tsc();
2351                 break;
2352         }
2353         case MSR_K6_STAR:
2354                 *data = svm->vmcb->save.star;
2355                 break;
2356 #ifdef CONFIG_X86_64
2357         case MSR_LSTAR:
2358                 *data = svm->vmcb->save.lstar;
2359                 break;
2360         case MSR_CSTAR:
2361                 *data = svm->vmcb->save.cstar;
2362                 break;
2363         case MSR_KERNEL_GS_BASE:
2364                 *data = svm->vmcb->save.kernel_gs_base;
2365                 break;
2366         case MSR_SYSCALL_MASK:
2367                 *data = svm->vmcb->save.sfmask;
2368                 break;
2369 #endif
2370         case MSR_IA32_SYSENTER_CS:
2371                 *data = svm->vmcb->save.sysenter_cs;
2372                 break;
2373         case MSR_IA32_SYSENTER_EIP:
2374                 *data = svm->sysenter_eip;
2375                 break;
2376         case MSR_IA32_SYSENTER_ESP:
2377                 *data = svm->sysenter_esp;
2378                 break;
2379         /*
2380          * Nobody will change the following 5 values in the VMCB so we can
2381          * safely return them on rdmsr. They will always be 0 until LBRV is
2382          * implemented.
2383          */
2384         case MSR_IA32_DEBUGCTLMSR:
2385                 *data = svm->vmcb->save.dbgctl;
2386                 break;
2387         case MSR_IA32_LASTBRANCHFROMIP:
2388                 *data = svm->vmcb->save.br_from;
2389                 break;
2390         case MSR_IA32_LASTBRANCHTOIP:
2391                 *data = svm->vmcb->save.br_to;
2392                 break;
2393         case MSR_IA32_LASTINTFROMIP:
2394                 *data = svm->vmcb->save.last_excp_from;
2395                 break;
2396         case MSR_IA32_LASTINTTOIP:
2397                 *data = svm->vmcb->save.last_excp_to;
2398                 break;
2399         case MSR_VM_HSAVE_PA:
2400                 *data = svm->nested.hsave_msr;
2401                 break;
2402         case MSR_VM_CR:
2403                 *data = svm->nested.vm_cr_msr;
2404                 break;
2405         case MSR_IA32_UCODE_REV:
2406                 *data = 0x01000065;
2407                 break;
2408         default:
2409                 return kvm_get_msr_common(vcpu, ecx, data);
2410         }
2411         return 0;
2412 }
2413
2414 static int rdmsr_interception(struct vcpu_svm *svm)
2415 {
2416         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2417         u64 data;
2418
2419         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2420                 trace_kvm_msr_read_ex(ecx);
2421                 kvm_inject_gp(&svm->vcpu, 0);
2422         } else {
2423                 trace_kvm_msr_read(ecx, data);
2424
2425                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2426                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2427                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2428                 skip_emulated_instruction(&svm->vcpu);
2429         }
2430         return 1;
2431 }
2432
2433 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2434 {
2435         struct vcpu_svm *svm = to_svm(vcpu);
2436         int svm_dis, chg_mask;
2437
2438         if (data & ~SVM_VM_CR_VALID_MASK)
2439                 return 1;
2440
2441         chg_mask = SVM_VM_CR_VALID_MASK;
2442
2443         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2444                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2445
2446         svm->nested.vm_cr_msr &= ~chg_mask;
2447         svm->nested.vm_cr_msr |= (data & chg_mask);
2448
2449         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2450
2451         /* check for svm_disable while efer.svme is set */
2452         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2453                 return 1;
2454
2455         return 0;
2456 }
2457
2458 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2459 {
2460         struct vcpu_svm *svm = to_svm(vcpu);
2461
2462         switch (ecx) {
2463         case MSR_IA32_TSC: {
2464                 u64 tsc_offset = data - native_read_tsc();
2465                 u64 g_tsc_offset = 0;
2466
2467                 if (is_nested(svm)) {
2468                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2469                                        svm->nested.hsave->control.tsc_offset;
2470                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2471                 }
2472
2473                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2474
2475                 break;
2476         }
2477         case MSR_K6_STAR:
2478                 svm->vmcb->save.star = data;
2479                 break;
2480 #ifdef CONFIG_X86_64
2481         case MSR_LSTAR:
2482                 svm->vmcb->save.lstar = data;
2483                 break;
2484         case MSR_CSTAR:
2485                 svm->vmcb->save.cstar = data;
2486                 break;
2487         case MSR_KERNEL_GS_BASE:
2488                 svm->vmcb->save.kernel_gs_base = data;
2489                 break;
2490         case MSR_SYSCALL_MASK:
2491                 svm->vmcb->save.sfmask = data;
2492                 break;
2493 #endif
2494         case MSR_IA32_SYSENTER_CS:
2495                 svm->vmcb->save.sysenter_cs = data;
2496                 break;
2497         case MSR_IA32_SYSENTER_EIP:
2498                 svm->sysenter_eip = data;
2499                 svm->vmcb->save.sysenter_eip = data;
2500                 break;
2501         case MSR_IA32_SYSENTER_ESP:
2502                 svm->sysenter_esp = data;
2503                 svm->vmcb->save.sysenter_esp = data;
2504                 break;
2505         case MSR_IA32_DEBUGCTLMSR:
2506                 if (!svm_has(SVM_FEATURE_LBRV)) {
2507                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2508                                         __func__, data);
2509                         break;
2510                 }
2511                 if (data & DEBUGCTL_RESERVED_BITS)
2512                         return 1;
2513
2514                 svm->vmcb->save.dbgctl = data;
2515                 if (data & (1ULL<<0))
2516                         svm_enable_lbrv(svm);
2517                 else
2518                         svm_disable_lbrv(svm);
2519                 break;
2520         case MSR_VM_HSAVE_PA:
2521                 svm->nested.hsave_msr = data;
2522                 break;
2523         case MSR_VM_CR:
2524                 return svm_set_vm_cr(vcpu, data);
2525         case MSR_VM_IGNNE:
2526                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2527                 break;
2528         default:
2529                 return kvm_set_msr_common(vcpu, ecx, data);
2530         }
2531         return 0;
2532 }
2533
2534 static int wrmsr_interception(struct vcpu_svm *svm)
2535 {
2536         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2537         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2538                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2539
2540
2541         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2542         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2543                 trace_kvm_msr_write_ex(ecx, data);
2544                 kvm_inject_gp(&svm->vcpu, 0);
2545         } else {
2546                 trace_kvm_msr_write(ecx, data);
2547                 skip_emulated_instruction(&svm->vcpu);
2548         }
2549         return 1;
2550 }
2551
2552 static int msr_interception(struct vcpu_svm *svm)
2553 {
2554         if (svm->vmcb->control.exit_info_1)
2555                 return wrmsr_interception(svm);
2556         else
2557                 return rdmsr_interception(svm);
2558 }
2559
2560 static int interrupt_window_interception(struct vcpu_svm *svm)
2561 {
2562         struct kvm_run *kvm_run = svm->vcpu.run;
2563
2564         svm_clear_vintr(svm);
2565         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2566         /*
2567          * If the user space waits to inject interrupts, exit as soon as
2568          * possible
2569          */
2570         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2571             kvm_run->request_interrupt_window &&
2572             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2573                 ++svm->vcpu.stat.irq_window_exits;
2574                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2575                 return 0;
2576         }
2577
2578         return 1;
2579 }
2580
2581 static int pause_interception(struct vcpu_svm *svm)
2582 {
2583         kvm_vcpu_on_spin(&(svm->vcpu));
2584         return 1;
2585 }
2586
2587 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2588         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2589         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2590         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2591         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2592         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2593         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2594         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2595         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2596         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2597         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2598         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2599         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2600         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2601         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2602         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2603         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2604         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2605         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2606         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2607         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2608         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2609         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2610         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2611         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2612         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2613         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2614         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2615         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2616         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2617         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2618         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2619         [SVM_EXIT_INTR]                         = intr_interception,
2620         [SVM_EXIT_NMI]                          = nmi_interception,
2621         [SVM_EXIT_SMI]                          = nop_on_interception,
2622         [SVM_EXIT_INIT]                         = nop_on_interception,
2623         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2624         [SVM_EXIT_CPUID]                        = cpuid_interception,
2625         [SVM_EXIT_IRET]                         = iret_interception,
2626         [SVM_EXIT_INVD]                         = emulate_on_interception,
2627         [SVM_EXIT_PAUSE]                        = pause_interception,
2628         [SVM_EXIT_HLT]                          = halt_interception,
2629         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2630         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2631         [SVM_EXIT_IOIO]                         = io_interception,
2632         [SVM_EXIT_MSR]                          = msr_interception,
2633         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2634         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2635         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2636         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2637         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2638         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2639         [SVM_EXIT_STGI]                         = stgi_interception,
2640         [SVM_EXIT_CLGI]                         = clgi_interception,
2641         [SVM_EXIT_SKINIT]                       = skinit_interception,
2642         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2643         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2644         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2645         [SVM_EXIT_NPF]                          = pf_interception,
2646 };
2647
2648 static int handle_exit(struct kvm_vcpu *vcpu)
2649 {
2650         struct vcpu_svm *svm = to_svm(vcpu);
2651         struct kvm_run *kvm_run = vcpu->run;
2652         u32 exit_code = svm->vmcb->control.exit_code;
2653
2654         trace_kvm_exit(exit_code, vcpu);
2655
2656         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2657                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2658         if (npt_enabled)
2659                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2660
2661         if (unlikely(svm->nested.exit_required)) {
2662                 nested_svm_vmexit(svm);
2663                 svm->nested.exit_required = false;
2664
2665                 return 1;
2666         }
2667
2668         if (is_nested(svm)) {
2669                 int vmexit;
2670
2671                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2672                                         svm->vmcb->control.exit_info_1,
2673                                         svm->vmcb->control.exit_info_2,
2674                                         svm->vmcb->control.exit_int_info,
2675                                         svm->vmcb->control.exit_int_info_err);
2676
2677                 vmexit = nested_svm_exit_special(svm);
2678
2679                 if (vmexit == NESTED_EXIT_CONTINUE)
2680                         vmexit = nested_svm_exit_handled(svm);
2681
2682                 if (vmexit == NESTED_EXIT_DONE)
2683                         return 1;
2684         }
2685
2686         svm_complete_interrupts(svm);
2687
2688         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2689                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2690                 kvm_run->fail_entry.hardware_entry_failure_reason
2691                         = svm->vmcb->control.exit_code;
2692                 return 0;
2693         }
2694
2695         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2696             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2697             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2698                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2699                        "exit_code 0x%x\n",
2700                        __func__, svm->vmcb->control.exit_int_info,
2701                        exit_code);
2702
2703         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2704             || !svm_exit_handlers[exit_code]) {
2705                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2706                 kvm_run->hw.hardware_exit_reason = exit_code;
2707                 return 0;
2708         }
2709
2710         return svm_exit_handlers[exit_code](svm);
2711 }
2712
2713 static void reload_tss(struct kvm_vcpu *vcpu)
2714 {
2715         int cpu = raw_smp_processor_id();
2716
2717         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2718         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2719         load_TR_desc();
2720 }
2721
2722 static void pre_svm_run(struct vcpu_svm *svm)
2723 {
2724         int cpu = raw_smp_processor_id();
2725
2726         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2727
2728         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2729         /* FIXME: handle wraparound of asid_generation */
2730         if (svm->asid_generation != sd->asid_generation)
2731                 new_asid(svm, sd);
2732 }
2733
2734 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2735 {
2736         struct vcpu_svm *svm = to_svm(vcpu);
2737
2738         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2739         vcpu->arch.hflags |= HF_NMI_MASK;
2740         svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2741         ++vcpu->stat.nmi_injections;
2742 }
2743
2744 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2745 {
2746         struct vmcb_control_area *control;
2747
2748         trace_kvm_inj_virq(irq);
2749
2750         ++svm->vcpu.stat.irq_injections;
2751         control = &svm->vmcb->control;
2752         control->int_vector = irq;
2753         control->int_ctl &= ~V_INTR_PRIO_MASK;
2754         control->int_ctl |= V_IRQ_MASK |
2755                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2756 }
2757
2758 static void svm_set_irq(struct kvm_vcpu *vcpu)
2759 {
2760         struct vcpu_svm *svm = to_svm(vcpu);
2761
2762         BUG_ON(!(gif_set(svm)));
2763
2764         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2765                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2766 }
2767
2768 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2769 {
2770         struct vcpu_svm *svm = to_svm(vcpu);
2771
2772         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2773                 return;
2774
2775         if (irr == -1)
2776                 return;
2777
2778         if (tpr >= irr)
2779                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2780 }
2781
2782 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2783 {
2784         struct vcpu_svm *svm = to_svm(vcpu);
2785         struct vmcb *vmcb = svm->vmcb;
2786         int ret;
2787         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2788               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2789         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2790
2791         return ret;
2792 }
2793
2794 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2795 {
2796         struct vcpu_svm *svm = to_svm(vcpu);
2797
2798         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2799 }
2800
2801 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2802 {
2803         struct vcpu_svm *svm = to_svm(vcpu);
2804
2805         if (masked) {
2806                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2807                 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2808         } else {
2809                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2810                 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2811         }
2812 }
2813
2814 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2815 {
2816         struct vcpu_svm *svm = to_svm(vcpu);
2817         struct vmcb *vmcb = svm->vmcb;
2818         int ret;
2819
2820         if (!gif_set(svm) ||
2821              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2822                 return 0;
2823
2824         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2825
2826         if (is_nested(svm))
2827                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2828
2829         return ret;
2830 }
2831
2832 static void enable_irq_window(struct kvm_vcpu *vcpu)
2833 {
2834         struct vcpu_svm *svm = to_svm(vcpu);
2835
2836         /*
2837          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2838          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
2839          * get that intercept, this function will be called again though and
2840          * we'll get the vintr intercept.
2841          */
2842         if (gif_set(svm) && nested_svm_intr(svm)) {
2843                 svm_set_vintr(svm);
2844                 svm_inject_irq(svm, 0x0);
2845         }
2846 }
2847
2848 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2849 {
2850         struct vcpu_svm *svm = to_svm(vcpu);
2851
2852         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2853             == HF_NMI_MASK)
2854                 return; /* IRET will cause a vm exit */
2855
2856         /*
2857          * Something prevents NMI from been injected. Single step over possible
2858          * problem (IRET or exception injection or interrupt shadow)
2859          */
2860         svm->nmi_singlestep = true;
2861         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2862         update_db_intercept(vcpu);
2863 }
2864
2865 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2866 {
2867         return 0;
2868 }
2869
2870 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2871 {
2872         force_new_asid(vcpu);
2873 }
2874
2875 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2876 {
2877 }
2878
2879 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2880 {
2881         struct vcpu_svm *svm = to_svm(vcpu);
2882
2883         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2884                 return;
2885
2886         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2887                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2888                 kvm_set_cr8(vcpu, cr8);
2889         }
2890 }
2891
2892 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2893 {
2894         struct vcpu_svm *svm = to_svm(vcpu);
2895         u64 cr8;
2896
2897         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2898                 return;
2899
2900         cr8 = kvm_get_cr8(vcpu);
2901         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2902         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2903 }
2904
2905 static void svm_complete_interrupts(struct vcpu_svm *svm)
2906 {
2907         u8 vector;
2908         int type;
2909         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2910         unsigned int3_injected = svm->int3_injected;
2911
2912         svm->int3_injected = 0;
2913
2914         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2915                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2916
2917         svm->vcpu.arch.nmi_injected = false;
2918         kvm_clear_exception_queue(&svm->vcpu);
2919         kvm_clear_interrupt_queue(&svm->vcpu);
2920
2921         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2922                 return;
2923
2924         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2925         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2926
2927         switch (type) {
2928         case SVM_EXITINTINFO_TYPE_NMI:
2929                 svm->vcpu.arch.nmi_injected = true;
2930                 break;
2931         case SVM_EXITINTINFO_TYPE_EXEPT:
2932                 /*
2933                  * In case of software exceptions, do not reinject the vector,
2934                  * but re-execute the instruction instead. Rewind RIP first
2935                  * if we emulated INT3 before.
2936                  */
2937                 if (kvm_exception_is_soft(vector)) {
2938                         if (vector == BP_VECTOR && int3_injected &&
2939                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2940                                 kvm_rip_write(&svm->vcpu,
2941                                               kvm_rip_read(&svm->vcpu) -
2942                                               int3_injected);
2943                         break;
2944                 }
2945                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2946                         u32 err = svm->vmcb->control.exit_int_info_err;
2947                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
2948
2949                 } else
2950                         kvm_requeue_exception(&svm->vcpu, vector);
2951                 break;
2952         case SVM_EXITINTINFO_TYPE_INTR:
2953                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2954                 break;
2955         default:
2956                 break;
2957         }
2958 }
2959
2960 #ifdef CONFIG_X86_64
2961 #define R "r"
2962 #else
2963 #define R "e"
2964 #endif
2965
2966 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2967 {
2968         struct vcpu_svm *svm = to_svm(vcpu);
2969         u16 fs_selector;
2970         u16 gs_selector;
2971         u16 ldt_selector;
2972
2973         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2974         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2975         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2976
2977         /*
2978          * A vmexit emulation is required before the vcpu can be executed
2979          * again.
2980          */
2981         if (unlikely(svm->nested.exit_required))
2982                 return;
2983
2984         pre_svm_run(svm);
2985
2986         sync_lapic_to_cr8(vcpu);
2987
2988         save_host_msrs(vcpu);
2989         fs_selector = kvm_read_fs();
2990         gs_selector = kvm_read_gs();
2991         ldt_selector = kvm_read_ldt();
2992         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2993         /* required for live migration with NPT */
2994         if (npt_enabled)
2995                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2996
2997         clgi();
2998
2999         local_irq_enable();
3000
3001         asm volatile (
3002                 "push %%"R"bp; \n\t"
3003                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3004                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3005                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3006                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3007                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3008                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3009 #ifdef CONFIG_X86_64
3010                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3011                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3012                 "mov %c[r10](%[svm]), %%r10 \n\t"
3013                 "mov %c[r11](%[svm]), %%r11 \n\t"
3014                 "mov %c[r12](%[svm]), %%r12 \n\t"
3015                 "mov %c[r13](%[svm]), %%r13 \n\t"
3016                 "mov %c[r14](%[svm]), %%r14 \n\t"
3017                 "mov %c[r15](%[svm]), %%r15 \n\t"
3018 #endif
3019
3020                 /* Enter guest mode */
3021                 "push %%"R"ax \n\t"
3022                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3023                 __ex(SVM_VMLOAD) "\n\t"
3024                 __ex(SVM_VMRUN) "\n\t"
3025                 __ex(SVM_VMSAVE) "\n\t"
3026                 "pop %%"R"ax \n\t"
3027
3028                 /* Save guest registers, load host registers */
3029                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3030                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3031                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3032                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3033                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3034                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3035 #ifdef CONFIG_X86_64
3036                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3037                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3038                 "mov %%r10, %c[r10](%[svm]) \n\t"
3039                 "mov %%r11, %c[r11](%[svm]) \n\t"
3040                 "mov %%r12, %c[r12](%[svm]) \n\t"
3041                 "mov %%r13, %c[r13](%[svm]) \n\t"
3042                 "mov %%r14, %c[r14](%[svm]) \n\t"
3043                 "mov %%r15, %c[r15](%[svm]) \n\t"
3044 #endif
3045                 "pop %%"R"bp"
3046                 :
3047                 : [svm]"a"(svm),
3048                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3049                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3050                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3051                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3052                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3053                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3054                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3055 #ifdef CONFIG_X86_64
3056                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3057                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3058                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3059                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3060                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3061                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3062                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3063                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3064 #endif
3065                 : "cc", "memory"
3066                 , R"bx", R"cx", R"dx", R"si", R"di"
3067 #ifdef CONFIG_X86_64
3068                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3069 #endif
3070                 );
3071
3072         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3073         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3074         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3075         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3076
3077         kvm_load_fs(fs_selector);
3078         kvm_load_gs(gs_selector);
3079         kvm_load_ldt(ldt_selector);
3080         load_host_msrs(vcpu);
3081
3082         reload_tss(vcpu);
3083
3084         local_irq_disable();
3085
3086         stgi();
3087
3088         sync_cr8_to_lapic(vcpu);
3089
3090         svm->next_rip = 0;
3091
3092         if (npt_enabled) {
3093                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3094                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3095         }
3096
3097         /*
3098          * We need to handle MC intercepts here before the vcpu has a chance to
3099          * change the physical cpu
3100          */
3101         if (unlikely(svm->vmcb->control.exit_code ==
3102                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3103                 svm_handle_mce(svm);
3104 }
3105
3106 #undef R
3107
3108 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3109 {
3110         struct vcpu_svm *svm = to_svm(vcpu);
3111
3112         if (npt_enabled) {
3113                 svm->vmcb->control.nested_cr3 = root;
3114                 force_new_asid(vcpu);
3115                 return;
3116         }
3117
3118         svm->vmcb->save.cr3 = root;
3119         force_new_asid(vcpu);
3120 }
3121
3122 static int is_disabled(void)
3123 {
3124         u64 vm_cr;
3125
3126         rdmsrl(MSR_VM_CR, vm_cr);
3127         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3128                 return 1;
3129
3130         return 0;
3131 }
3132
3133 static void
3134 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3135 {
3136         /*
3137          * Patch in the VMMCALL instruction:
3138          */
3139         hypercall[0] = 0x0f;
3140         hypercall[1] = 0x01;
3141         hypercall[2] = 0xd9;
3142 }
3143
3144 static void svm_check_processor_compat(void *rtn)
3145 {
3146         *(int *)rtn = 0;
3147 }
3148
3149 static bool svm_cpu_has_accelerated_tpr(void)
3150 {
3151         return false;
3152 }
3153
3154 static int get_npt_level(void)
3155 {
3156 #ifdef CONFIG_X86_64
3157         return PT64_ROOT_LEVEL;
3158 #else
3159         return PT32E_ROOT_LEVEL;
3160 #endif
3161 }
3162
3163 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3164 {
3165         return 0;
3166 }
3167
3168 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3169 {
3170 }
3171
3172 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3173 {
3174         switch (func) {
3175         case 0x8000000A:
3176                 entry->eax = 1; /* SVM revision 1 */
3177                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3178                                    ASID emulation to nested SVM */
3179                 entry->ecx = 0; /* Reserved */
3180                 entry->edx = 0; /* Do not support any additional features */
3181
3182                 break;
3183         }
3184 }
3185
3186 static const struct trace_print_flags svm_exit_reasons_str[] = {
3187         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3188         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3189         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3190         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3191         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3192         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3193         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3194         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3195         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3196         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3197         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3198         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3199         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3200         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3201         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3202         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3203         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3204         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3205         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3206         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3207         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3208         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3209         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3210         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3211         { SVM_EXIT_INTR,                        "interrupt" },
3212         { SVM_EXIT_NMI,                         "nmi" },
3213         { SVM_EXIT_SMI,                         "smi" },
3214         { SVM_EXIT_INIT,                        "init" },
3215         { SVM_EXIT_VINTR,                       "vintr" },
3216         { SVM_EXIT_CPUID,                       "cpuid" },
3217         { SVM_EXIT_INVD,                        "invd" },
3218         { SVM_EXIT_HLT,                         "hlt" },
3219         { SVM_EXIT_INVLPG,                      "invlpg" },
3220         { SVM_EXIT_INVLPGA,                     "invlpga" },
3221         { SVM_EXIT_IOIO,                        "io" },
3222         { SVM_EXIT_MSR,                         "msr" },
3223         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3224         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3225         { SVM_EXIT_VMRUN,                       "vmrun" },
3226         { SVM_EXIT_VMMCALL,                     "hypercall" },
3227         { SVM_EXIT_VMLOAD,                      "vmload" },
3228         { SVM_EXIT_VMSAVE,                      "vmsave" },
3229         { SVM_EXIT_STGI,                        "stgi" },
3230         { SVM_EXIT_CLGI,                        "clgi" },
3231         { SVM_EXIT_SKINIT,                      "skinit" },
3232         { SVM_EXIT_WBINVD,                      "wbinvd" },
3233         { SVM_EXIT_MONITOR,                     "monitor" },
3234         { SVM_EXIT_MWAIT,                       "mwait" },
3235         { SVM_EXIT_NPF,                         "npf" },
3236         { -1, NULL }
3237 };
3238
3239 static int svm_get_lpage_level(void)
3240 {
3241         return PT_PDPE_LEVEL;
3242 }
3243
3244 static bool svm_rdtscp_supported(void)
3245 {
3246         return false;
3247 }
3248
3249 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3250 {
3251         struct vcpu_svm *svm = to_svm(vcpu);
3252
3253         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3254         if (is_nested(svm))
3255                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3256         update_cr0_intercept(svm);
3257 }
3258
3259 static struct kvm_x86_ops svm_x86_ops = {
3260         .cpu_has_kvm_support = has_svm,
3261         .disabled_by_bios = is_disabled,
3262         .hardware_setup = svm_hardware_setup,
3263         .hardware_unsetup = svm_hardware_unsetup,
3264         .check_processor_compatibility = svm_check_processor_compat,
3265         .hardware_enable = svm_hardware_enable,
3266         .hardware_disable = svm_hardware_disable,
3267         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3268
3269         .vcpu_create = svm_create_vcpu,
3270         .vcpu_free = svm_free_vcpu,
3271         .vcpu_reset = svm_vcpu_reset,
3272
3273         .prepare_guest_switch = svm_prepare_guest_switch,
3274         .vcpu_load = svm_vcpu_load,
3275         .vcpu_put = svm_vcpu_put,
3276
3277         .set_guest_debug = svm_guest_debug,
3278         .get_msr = svm_get_msr,
3279         .set_msr = svm_set_msr,
3280         .get_segment_base = svm_get_segment_base,
3281         .get_segment = svm_get_segment,
3282         .set_segment = svm_set_segment,
3283         .get_cpl = svm_get_cpl,
3284         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3285         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3286         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3287         .set_cr0 = svm_set_cr0,
3288         .set_cr3 = svm_set_cr3,
3289         .set_cr4 = svm_set_cr4,
3290         .set_efer = svm_set_efer,
3291         .get_idt = svm_get_idt,
3292         .set_idt = svm_set_idt,
3293         .get_gdt = svm_get_gdt,
3294         .set_gdt = svm_set_gdt,
3295         .set_dr7 = svm_set_dr7,
3296         .cache_reg = svm_cache_reg,
3297         .get_rflags = svm_get_rflags,
3298         .set_rflags = svm_set_rflags,
3299         .fpu_activate = svm_fpu_activate,
3300         .fpu_deactivate = svm_fpu_deactivate,
3301
3302         .tlb_flush = svm_flush_tlb,
3303
3304         .run = svm_vcpu_run,
3305         .handle_exit = handle_exit,
3306         .skip_emulated_instruction = skip_emulated_instruction,
3307         .set_interrupt_shadow = svm_set_interrupt_shadow,
3308         .get_interrupt_shadow = svm_get_interrupt_shadow,
3309         .patch_hypercall = svm_patch_hypercall,
3310         .set_irq = svm_set_irq,
3311         .set_nmi = svm_inject_nmi,
3312         .queue_exception = svm_queue_exception,
3313         .interrupt_allowed = svm_interrupt_allowed,
3314         .nmi_allowed = svm_nmi_allowed,
3315         .get_nmi_mask = svm_get_nmi_mask,
3316         .set_nmi_mask = svm_set_nmi_mask,
3317         .enable_nmi_window = enable_nmi_window,
3318         .enable_irq_window = enable_irq_window,
3319         .update_cr8_intercept = update_cr8_intercept,
3320
3321         .set_tss_addr = svm_set_tss_addr,
3322         .get_tdp_level = get_npt_level,
3323         .get_mt_mask = svm_get_mt_mask,
3324
3325         .exit_reasons_str = svm_exit_reasons_str,
3326         .get_lpage_level = svm_get_lpage_level,
3327
3328         .cpuid_update = svm_cpuid_update,
3329
3330         .rdtscp_supported = svm_rdtscp_supported,
3331
3332         .set_supported_cpuid = svm_set_supported_cpuid,
3333 };
3334
3335 static int __init svm_init(void)
3336 {
3337         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3338                         __alignof__(struct vcpu_svm), THIS_MODULE);
3339 }
3340
3341 static void __exit svm_exit(void)
3342 {
3343         kvm_exit();
3344 }
3345
3346 module_init(svm_init)
3347 module_exit(svm_exit)