2 * 8253/8254 interval timer emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2006 Intel Corporation
6 * Copyright (c) 2007 Keir Fraser, XenSource Inc
7 * Copyright (c) 2008 Intel Corporation
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * Sheng Yang <sheng.yang@intel.com>
29 * Based on QEMU and Xen.
32 #define pr_fmt(fmt) "pit: " fmt
34 #include <linux/kvm_host.h>
35 #include <linux/slab.h>
41 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
43 #define mod_64(x, y) ((x) % (y))
46 #define RW_STATE_LSB 1
47 #define RW_STATE_MSB 2
48 #define RW_STATE_WORD0 3
49 #define RW_STATE_WORD1 4
51 /* Compute with 96 bit intermediate result: (a*b)/c */
52 static u64 muldiv64(u64 a, u32 b, u32 c)
63 rl = (u64)u.l.low * (u64)b;
64 rh = (u64)u.l.high * (u64)b;
66 res.l.high = div64_u64(rh, c);
67 res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
71 static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
73 struct kvm_kpit_channel_state *c =
74 &kvm->arch.vpit->pit_state.channels[channel];
76 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
82 /* XXX: just disable/enable counting */
88 /* Restart counting on rising edge. */
90 c->count_load_time = ktime_get();
97 static int pit_get_gate(struct kvm *kvm, int channel)
99 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
101 return kvm->arch.vpit->pit_state.channels[channel].gate;
104 static s64 __kpit_elapsed(struct kvm *kvm)
108 struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
110 if (!ps->pit_timer.period)
114 * The Counter does not stop when it reaches zero. In
115 * Modes 0, 1, 4, and 5 the Counter ``wraps around'' to
116 * the highest count, either FFFF hex for binary counting
117 * or 9999 for BCD counting, and continues counting.
118 * Modes 2 and 3 are periodic; the Counter reloads
119 * itself with the initial count and continues counting
122 remaining = hrtimer_get_remaining(&ps->pit_timer.timer);
123 elapsed = ps->pit_timer.period - ktime_to_ns(remaining);
124 elapsed = mod_64(elapsed, ps->pit_timer.period);
129 static s64 kpit_elapsed(struct kvm *kvm, struct kvm_kpit_channel_state *c,
133 return __kpit_elapsed(kvm);
135 return ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
138 static int pit_get_count(struct kvm *kvm, int channel)
140 struct kvm_kpit_channel_state *c =
141 &kvm->arch.vpit->pit_state.channels[channel];
145 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
147 t = kpit_elapsed(kvm, c, channel);
148 d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
155 counter = (c->count - d) & 0xffff;
158 /* XXX: may be incorrect for odd counts */
159 counter = c->count - (mod_64((2 * d), c->count));
162 counter = c->count - mod_64(d, c->count);
168 static int pit_get_out(struct kvm *kvm, int channel)
170 struct kvm_kpit_channel_state *c =
171 &kvm->arch.vpit->pit_state.channels[channel];
175 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
177 t = kpit_elapsed(kvm, c, channel);
178 d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
183 out = (d >= c->count);
186 out = (d < c->count);
189 out = ((mod_64(d, c->count) == 0) && (d != 0));
192 out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
196 out = (d == c->count);
203 static void pit_latch_count(struct kvm *kvm, int channel)
205 struct kvm_kpit_channel_state *c =
206 &kvm->arch.vpit->pit_state.channels[channel];
208 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
210 if (!c->count_latched) {
211 c->latched_count = pit_get_count(kvm, channel);
212 c->count_latched = c->rw_mode;
216 static void pit_latch_status(struct kvm *kvm, int channel)
218 struct kvm_kpit_channel_state *c =
219 &kvm->arch.vpit->pit_state.channels[channel];
221 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
223 if (!c->status_latched) {
224 /* TODO: Return NULL COUNT (bit 6). */
225 c->status = ((pit_get_out(kvm, channel) << 7) |
229 c->status_latched = 1;
233 int pit_has_pending_timer(struct kvm_vcpu *vcpu)
235 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
237 if (pit && kvm_vcpu_is_bsp(vcpu) && pit->pit_state.irq_ack)
238 return atomic_read(&pit->pit_state.pit_timer.pending);
242 static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
244 struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
246 raw_spin_lock(&ps->inject_lock);
247 if (atomic_dec_return(&ps->pit_timer.pending) < 0)
248 atomic_inc(&ps->pit_timer.pending);
250 raw_spin_unlock(&ps->inject_lock);
253 void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
255 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
256 struct hrtimer *timer;
258 if (!kvm_vcpu_is_bsp(vcpu) || !pit)
261 timer = &pit->pit_state.pit_timer.timer;
262 if (hrtimer_cancel(timer))
263 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
266 static void destroy_pit_timer(struct kvm_timer *pt)
268 pr_debug("execute del timer!\n");
269 hrtimer_cancel(&pt->timer);
272 static bool kpit_is_periodic(struct kvm_timer *ktimer)
274 struct kvm_kpit_state *ps = container_of(ktimer, struct kvm_kpit_state,
276 return ps->is_periodic;
279 static struct kvm_timer_ops kpit_ops = {
280 .is_periodic = kpit_is_periodic,
283 static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
285 struct kvm_timer *pt = &ps->pit_timer;
288 interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);
290 pr_debug("create pit timer, interval is %llu nsec\n", interval);
292 /* TODO The new value only affected after the retriggered */
293 hrtimer_cancel(&pt->timer);
294 pt->period = interval;
295 ps->is_periodic = is_period;
297 pt->timer.function = kvm_timer_fn;
298 pt->t_ops = &kpit_ops;
299 pt->kvm = ps->pit->kvm;
300 pt->vcpu = pt->kvm->bsp_vcpu;
302 atomic_set(&pt->pending, 0);
305 hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
309 static void pit_load_count(struct kvm *kvm, int channel, u32 val)
311 struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
313 WARN_ON(!mutex_is_locked(&ps->lock));
315 pr_debug("load_count val is %d, channel is %d\n", val, channel);
318 * The largest possible initial count is 0; this is equivalent
319 * to 216 for binary counting and 104 for BCD counting.
324 ps->channels[channel].count = val;
327 ps->channels[channel].count_load_time = ktime_get();
331 /* Two types of timer
332 * mode 1 is one shot, mode 2 is period, otherwise del timer */
333 switch (ps->channels[0].mode) {
336 /* FIXME: enhance mode 4 precision */
338 if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)) {
339 create_pit_timer(ps, val, 0);
344 if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)){
345 create_pit_timer(ps, val, 1);
349 destroy_pit_timer(&ps->pit_timer);
353 void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val, int hpet_legacy_start)
356 if (hpet_legacy_start) {
357 /* save existing mode for later reenablement */
358 saved_mode = kvm->arch.vpit->pit_state.channels[0].mode;
359 kvm->arch.vpit->pit_state.channels[0].mode = 0xff; /* disable timer */
360 pit_load_count(kvm, channel, val);
361 kvm->arch.vpit->pit_state.channels[0].mode = saved_mode;
363 pit_load_count(kvm, channel, val);
367 static inline struct kvm_pit *dev_to_pit(struct kvm_io_device *dev)
369 return container_of(dev, struct kvm_pit, dev);
372 static inline struct kvm_pit *speaker_to_pit(struct kvm_io_device *dev)
374 return container_of(dev, struct kvm_pit, speaker_dev);
377 static inline int pit_in_range(gpa_t addr)
379 return ((addr >= KVM_PIT_BASE_ADDRESS) &&
380 (addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
383 static int pit_ioport_write(struct kvm_io_device *this,
384 gpa_t addr, int len, const void *data)
386 struct kvm_pit *pit = dev_to_pit(this);
387 struct kvm_kpit_state *pit_state = &pit->pit_state;
388 struct kvm *kvm = pit->kvm;
390 struct kvm_kpit_channel_state *s;
391 u32 val = *(u32 *) data;
392 if (!pit_in_range(addr))
396 addr &= KVM_PIT_CHANNEL_MASK;
398 mutex_lock(&pit_state->lock);
401 pr_debug("write addr is 0x%x, len is %d, val is 0x%x\n",
402 (unsigned int)addr, len, val);
407 /* Read-Back Command. */
408 for (channel = 0; channel < 3; channel++) {
409 s = &pit_state->channels[channel];
410 if (val & (2 << channel)) {
412 pit_latch_count(kvm, channel);
414 pit_latch_status(kvm, channel);
418 /* Select Counter <channel>. */
419 s = &pit_state->channels[channel];
420 access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
422 pit_latch_count(kvm, channel);
425 s->read_state = access;
426 s->write_state = access;
427 s->mode = (val >> 1) & 7;
435 s = &pit_state->channels[addr];
436 switch (s->write_state) {
439 pit_load_count(kvm, addr, val);
442 pit_load_count(kvm, addr, val << 8);
445 s->write_latch = val;
446 s->write_state = RW_STATE_WORD1;
449 pit_load_count(kvm, addr, s->write_latch | (val << 8));
450 s->write_state = RW_STATE_WORD0;
455 mutex_unlock(&pit_state->lock);
459 static int pit_ioport_read(struct kvm_io_device *this,
460 gpa_t addr, int len, void *data)
462 struct kvm_pit *pit = dev_to_pit(this);
463 struct kvm_kpit_state *pit_state = &pit->pit_state;
464 struct kvm *kvm = pit->kvm;
466 struct kvm_kpit_channel_state *s;
467 if (!pit_in_range(addr))
470 addr &= KVM_PIT_CHANNEL_MASK;
474 s = &pit_state->channels[addr];
476 mutex_lock(&pit_state->lock);
478 if (s->status_latched) {
479 s->status_latched = 0;
481 } else if (s->count_latched) {
482 switch (s->count_latched) {
485 ret = s->latched_count & 0xff;
486 s->count_latched = 0;
489 ret = s->latched_count >> 8;
490 s->count_latched = 0;
493 ret = s->latched_count & 0xff;
494 s->count_latched = RW_STATE_MSB;
498 switch (s->read_state) {
501 count = pit_get_count(kvm, addr);
505 count = pit_get_count(kvm, addr);
506 ret = (count >> 8) & 0xff;
509 count = pit_get_count(kvm, addr);
511 s->read_state = RW_STATE_WORD1;
514 count = pit_get_count(kvm, addr);
515 ret = (count >> 8) & 0xff;
516 s->read_state = RW_STATE_WORD0;
521 if (len > sizeof(ret))
523 memcpy(data, (char *)&ret, len);
525 mutex_unlock(&pit_state->lock);
529 static int speaker_ioport_write(struct kvm_io_device *this,
530 gpa_t addr, int len, const void *data)
532 struct kvm_pit *pit = speaker_to_pit(this);
533 struct kvm_kpit_state *pit_state = &pit->pit_state;
534 struct kvm *kvm = pit->kvm;
535 u32 val = *(u32 *) data;
536 if (addr != KVM_SPEAKER_BASE_ADDRESS)
539 mutex_lock(&pit_state->lock);
540 pit_state->speaker_data_on = (val >> 1) & 1;
541 pit_set_gate(kvm, 2, val & 1);
542 mutex_unlock(&pit_state->lock);
546 static int speaker_ioport_read(struct kvm_io_device *this,
547 gpa_t addr, int len, void *data)
549 struct kvm_pit *pit = speaker_to_pit(this);
550 struct kvm_kpit_state *pit_state = &pit->pit_state;
551 struct kvm *kvm = pit->kvm;
552 unsigned int refresh_clock;
554 if (addr != KVM_SPEAKER_BASE_ADDRESS)
557 /* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
558 refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
560 mutex_lock(&pit_state->lock);
561 ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) |
562 (pit_get_out(kvm, 2) << 5) | (refresh_clock << 4));
563 if (len > sizeof(ret))
565 memcpy(data, (char *)&ret, len);
566 mutex_unlock(&pit_state->lock);
570 void kvm_pit_reset(struct kvm_pit *pit)
573 struct kvm_kpit_channel_state *c;
575 mutex_lock(&pit->pit_state.lock);
576 pit->pit_state.flags = 0;
577 for (i = 0; i < 3; i++) {
578 c = &pit->pit_state.channels[i];
581 pit_load_count(pit->kvm, i, 0);
583 mutex_unlock(&pit->pit_state.lock);
585 atomic_set(&pit->pit_state.pit_timer.pending, 0);
586 pit->pit_state.irq_ack = 1;
589 static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask)
591 struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier);
594 atomic_set(&pit->pit_state.pit_timer.pending, 0);
595 pit->pit_state.irq_ack = 1;
599 static const struct kvm_io_device_ops pit_dev_ops = {
600 .read = pit_ioport_read,
601 .write = pit_ioport_write,
604 static const struct kvm_io_device_ops speaker_dev_ops = {
605 .read = speaker_ioport_read,
606 .write = speaker_ioport_write,
609 /* Caller must hold slots_lock */
610 struct kvm_pit *kvm_create_pit(struct kvm *kvm, u32 flags)
613 struct kvm_kpit_state *pit_state;
616 pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
620 pit->irq_source_id = kvm_request_irq_source_id(kvm);
621 if (pit->irq_source_id < 0) {
626 mutex_init(&pit->pit_state.lock);
627 mutex_lock(&pit->pit_state.lock);
628 raw_spin_lock_init(&pit->pit_state.inject_lock);
630 kvm->arch.vpit = pit;
633 pit_state = &pit->pit_state;
634 pit_state->pit = pit;
635 hrtimer_init(&pit_state->pit_timer.timer,
636 CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
637 pit_state->irq_ack_notifier.gsi = 0;
638 pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq;
639 kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
640 pit_state->pit_timer.reinject = true;
641 mutex_unlock(&pit->pit_state.lock);
645 pit->mask_notifier.func = pit_mask_notifer;
646 kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
648 kvm_iodevice_init(&pit->dev, &pit_dev_ops);
649 ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &pit->dev);
653 if (flags & KVM_PIT_SPEAKER_DUMMY) {
654 kvm_iodevice_init(&pit->speaker_dev, &speaker_dev_ops);
655 ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS,
658 goto fail_unregister;
664 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &pit->dev);
667 kvm_unregister_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
668 kvm_unregister_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
669 kvm_free_irq_source_id(kvm, pit->irq_source_id);
675 void kvm_free_pit(struct kvm *kvm)
677 struct hrtimer *timer;
679 if (kvm->arch.vpit) {
680 kvm_unregister_irq_mask_notifier(kvm, 0,
681 &kvm->arch.vpit->mask_notifier);
682 kvm_unregister_irq_ack_notifier(kvm,
683 &kvm->arch.vpit->pit_state.irq_ack_notifier);
684 mutex_lock(&kvm->arch.vpit->pit_state.lock);
685 timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
686 hrtimer_cancel(timer);
687 kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
688 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
689 kfree(kvm->arch.vpit);
693 static void __inject_pit_timer_intr(struct kvm *kvm)
695 struct kvm_vcpu *vcpu;
698 kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
699 kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
702 * Provides NMI watchdog support via Virtual Wire mode.
703 * The route is: PIT -> PIC -> LVT0 in NMI mode.
705 * Note: Our Virtual Wire implementation is simplified, only
706 * propagating PIT interrupts to all VCPUs when they have set
707 * LVT0 to NMI delivery. Other PIC interrupts are just sent to
708 * VCPU0, and only if its LVT0 is in EXTINT mode.
710 if (kvm->arch.vapics_in_nmi_mode > 0)
711 kvm_for_each_vcpu(i, vcpu, kvm)
712 kvm_apic_nmi_wd_deliver(vcpu);
715 void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
717 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
718 struct kvm *kvm = vcpu->kvm;
719 struct kvm_kpit_state *ps;
723 ps = &pit->pit_state;
725 /* Try to inject pending interrupts when
726 * last one has been acked.
728 raw_spin_lock(&ps->inject_lock);
729 if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
733 raw_spin_unlock(&ps->inject_lock);
735 __inject_pit_timer_intr(kvm);