2 * 'traps.c' handles hardware traps and faults after we have saved some
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2007 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/hardirq.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
22 #include <linux/bug.h>
23 #include <linux/debug_locks.h>
24 #include <linux/kdebug.h>
25 #include <linux/kexec.h>
26 #include <linux/limits.h>
27 #include <linux/proc_fs.h>
28 #include <linux/seq_file.h>
29 #include <linux/sysfs.h>
30 #include <asm/system.h>
31 #include <asm/uaccess.h>
33 #include <asm/kprobes.h>
36 # define TRAP_RESERVED_INST 4
37 # define TRAP_ILLEGAL_SLOT_INST 6
38 # define TRAP_ADDRESS_ERROR 9
39 # ifdef CONFIG_CPU_SH2A
41 # define TRAP_FPU_ERROR 13
42 # define TRAP_DIVZERO_ERROR 17
43 # define TRAP_DIVOVF_ERROR 18
46 #define TRAP_RESERVED_INST 12
47 #define TRAP_ILLEGAL_SLOT_INST 13
50 static unsigned long se_user;
51 static unsigned long se_sys;
52 static unsigned long se_half;
53 static unsigned long se_word;
54 static unsigned long se_dword;
55 static unsigned long se_multi;
56 /* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not
58 static int se_usermode = 3;
59 /* 0: no warning 1: print a warning message, disabled by default */
60 static int se_kernmode_warn;
63 static const char *se_usermode_action[] = {
72 static int alignment_proc_show(struct seq_file *m, void *v)
74 seq_printf(m, "User:\t\t%lu\n", se_user);
75 seq_printf(m, "System:\t\t%lu\n", se_sys);
76 seq_printf(m, "Half:\t\t%lu\n", se_half);
77 seq_printf(m, "Word:\t\t%lu\n", se_word);
78 seq_printf(m, "DWord:\t\t%lu\n", se_dword);
79 seq_printf(m, "Multi:\t\t%lu\n", se_multi);
80 seq_printf(m, "User faults:\t%i (%s)\n", se_usermode,
81 se_usermode_action[se_usermode]);
82 seq_printf(m, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn,
83 se_kernmode_warn ? "+warn" : "");
87 static int alignment_proc_open(struct inode *inode, struct file *file)
89 return single_open(file, alignment_proc_show, NULL);
92 static ssize_t alignment_proc_write(struct file *file,
93 const char __user *buffer, size_t count, loff_t *pos)
95 int *data = PDE(file->f_path.dentry->d_inode)->data;
99 if (get_user(mode, buffer))
101 if (mode >= '0' && mode <= '5')
107 static const struct file_operations alignment_proc_fops = {
108 .owner = THIS_MODULE,
109 .open = alignment_proc_open,
112 .release = single_release,
113 .write = alignment_proc_write,
117 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
122 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
124 for (p = bottom & ~31; p < top; ) {
125 printk("%04lx: ", p & 0xffff);
127 for (i = 0; i < 8; i++, p += 4) {
130 if (p < bottom || p >= top)
133 if (__get_user(val, (unsigned int __user *)p)) {
137 printk("%08x ", val);
144 static DEFINE_SPINLOCK(die_lock);
146 void die(const char * str, struct pt_regs * regs, long err)
148 static int die_counter;
152 spin_lock_irq(&die_lock);
156 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
157 sysfs_printk_last_file();
161 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
162 task_pid_nr(current), task_stack_page(current) + 1);
164 if (!user_mode(regs) || in_interrupt())
165 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
166 (unsigned long)task_stack_page(current));
168 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
171 add_taint(TAINT_DIE);
172 spin_unlock_irq(&die_lock);
175 if (kexec_should_crash(current))
179 panic("Fatal exception in interrupt");
182 panic("Fatal exception");
187 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
190 if (!user_mode(regs))
195 * try and fix up kernelspace address errors
196 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
197 * - kernel/userspace interfaces cause a jump to an appropriate handler
198 * - other kernel errors are bad
200 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
202 if (!user_mode(regs)) {
203 const struct exception_table_entry *fixup;
204 fixup = search_exception_tables(regs->pc);
206 regs->pc = fixup->fixup;
214 static inline void sign_extend(unsigned int count, unsigned char *dst)
216 #ifdef __LITTLE_ENDIAN__
217 if ((count == 1) && dst[0] & 0x80) {
222 if ((count == 2) && dst[1] & 0x80) {
227 if ((count == 1) && dst[3] & 0x80) {
232 if ((count == 2) && dst[2] & 0x80) {
239 static struct mem_access user_mem_access = {
245 * handle an instruction that does an unaligned memory access by emulating the
247 * - note that PC _may not_ point to the faulting instruction
248 * (if that instruction is in a branch delay slot)
249 * - return 0 if emulation okay, -EFAULT on existential error
251 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
252 struct mem_access *ma)
254 int ret, index, count;
255 unsigned long *rm, *rn;
256 unsigned char *src, *dst;
257 unsigned char __user *srcu, *dstu;
259 index = (instruction>>8)&15; /* 0x0F00 */
260 rn = ®s->regs[index];
262 index = (instruction>>4)&15; /* 0x00F0 */
263 rm = ®s->regs[index];
265 count = 1<<(instruction&3);
268 case 1: se_half += 1; break;
269 case 2: se_word += 1; break;
270 case 4: se_dword += 1; break;
271 case 8: se_multi += 1; break; /* ??? */
275 switch (instruction>>12) {
276 case 0: /* mov.[bwl] to/from memory via r0+rn */
277 if (instruction & 8) {
279 srcu = (unsigned char __user *)*rm;
280 srcu += regs->regs[0];
281 dst = (unsigned char *)rn;
282 *(unsigned long *)dst = 0;
284 #if !defined(__LITTLE_ENDIAN__)
287 if (ma->from(dst, srcu, count))
290 sign_extend(count, dst);
293 src = (unsigned char *)rm;
294 #if !defined(__LITTLE_ENDIAN__)
297 dstu = (unsigned char __user *)*rn;
298 dstu += regs->regs[0];
300 if (ma->to(dstu, src, count))
306 case 1: /* mov.l Rm,@(disp,Rn) */
307 src = (unsigned char*) rm;
308 dstu = (unsigned char __user *)*rn;
309 dstu += (instruction&0x000F)<<2;
311 if (ma->to(dstu, src, 4))
316 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
319 src = (unsigned char*) rm;
320 dstu = (unsigned char __user *)*rn;
321 #if !defined(__LITTLE_ENDIAN__)
324 if (ma->to(dstu, src, count))
329 case 5: /* mov.l @(disp,Rm),Rn */
330 srcu = (unsigned char __user *)*rm;
331 srcu += (instruction & 0x000F) << 2;
332 dst = (unsigned char *)rn;
333 *(unsigned long *)dst = 0;
335 if (ma->from(dst, srcu, 4))
340 case 6: /* mov.[bwl] from memory, possibly with post-increment */
341 srcu = (unsigned char __user *)*rm;
344 dst = (unsigned char*) rn;
345 *(unsigned long*)dst = 0;
347 #if !defined(__LITTLE_ENDIAN__)
350 if (ma->from(dst, srcu, count))
352 sign_extend(count, dst);
357 switch ((instruction&0xFF00)>>8) {
358 case 0x81: /* mov.w R0,@(disp,Rn) */
359 src = (unsigned char *) ®s->regs[0];
360 #if !defined(__LITTLE_ENDIAN__)
363 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
364 dstu += (instruction & 0x000F) << 1;
366 if (ma->to(dstu, src, 2))
371 case 0x85: /* mov.w @(disp,Rm),R0 */
372 srcu = (unsigned char __user *)*rm;
373 srcu += (instruction & 0x000F) << 1;
374 dst = (unsigned char *) ®s->regs[0];
375 *(unsigned long *)dst = 0;
377 #if !defined(__LITTLE_ENDIAN__)
380 if (ma->from(dst, srcu, 2))
391 /* Argh. Address not only misaligned but also non-existent.
392 * Raise an EFAULT and see if it's trapped
394 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
399 * emulate the instruction in the delay slot
400 * - fetches the instruction from PC+2
402 static inline int handle_delayslot(struct pt_regs *regs,
403 insn_size_t old_instruction,
404 struct mem_access *ma)
406 insn_size_t instruction;
407 void __user *addr = (void __user *)(regs->pc +
408 instruction_size(old_instruction));
410 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
411 /* the instruction-fetch faulted */
416 die("delay-slot-insn faulting in handle_unaligned_delayslot",
420 return handle_unaligned_ins(instruction, regs, ma);
424 * handle an instruction that does an unaligned memory access
425 * - have to be careful of branch delay-slot instructions that fault
427 * - if the branch would be taken PC points to the branch
428 * - if the branch would not be taken, PC points to delay-slot
430 * - PC always points to delayed branch
431 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
434 /* Macros to determine offset from current PC for branch instructions */
435 /* Explicit type coercion is used to force sign extension where needed */
436 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
437 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
439 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
440 struct mem_access *ma, int expected)
446 * XXX: We can't handle mixed 16/32-bit instructions yet
448 if (instruction_size(instruction) != 2)
451 index = (instruction>>8)&15; /* 0x0F00 */
452 rm = regs->regs[index];
454 /* shout about fixups */
455 if (!expected && printk_ratelimit())
456 printk(KERN_NOTICE "Fixing up unaligned %s access "
457 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
458 user_mode(regs) ? "userspace" : "kernel",
459 current->comm, task_pid_nr(current),
460 (void *)regs->pc, instruction);
463 switch (instruction&0xF000) {
465 if (instruction==0x000B) {
467 ret = handle_delayslot(regs, instruction, ma);
471 else if ((instruction&0x00FF)==0x0023) {
473 ret = handle_delayslot(regs, instruction, ma);
477 else if ((instruction&0x00FF)==0x0003) {
479 ret = handle_delayslot(regs, instruction, ma);
481 regs->pr = regs->pc + 4;
486 /* mov.[bwl] to/from memory via r0+rn */
491 case 0x1000: /* mov.l Rm,@(disp,Rn) */
494 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
498 if ((instruction&0x00FF)==0x002B) {
500 ret = handle_delayslot(regs, instruction, ma);
504 else if ((instruction&0x00FF)==0x000B) {
506 ret = handle_delayslot(regs, instruction, ma);
508 regs->pr = regs->pc + 4;
513 /* mov.[bwl] to/from memory via r0+rn */
518 case 0x5000: /* mov.l @(disp,Rm),Rn */
521 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
524 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
525 switch (instruction&0x0F00) {
526 case 0x0100: /* mov.w R0,@(disp,Rm) */
528 case 0x0500: /* mov.w @(disp,Rm),R0 */
530 case 0x0B00: /* bf lab - no delayslot*/
532 case 0x0F00: /* bf/s lab */
533 ret = handle_delayslot(regs, instruction, ma);
535 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
536 if ((regs->sr & 0x00000001) != 0)
537 regs->pc += 4; /* next after slot */
540 regs->pc += SH_PC_8BIT_OFFSET(instruction);
543 case 0x0900: /* bt lab - no delayslot */
545 case 0x0D00: /* bt/s lab */
546 ret = handle_delayslot(regs, instruction, ma);
548 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
549 if ((regs->sr & 0x00000001) == 0)
550 regs->pc += 4; /* next after slot */
553 regs->pc += SH_PC_8BIT_OFFSET(instruction);
559 case 0xA000: /* bra label */
560 ret = handle_delayslot(regs, instruction, ma);
562 regs->pc += SH_PC_12BIT_OFFSET(instruction);
565 case 0xB000: /* bsr label */
566 ret = handle_delayslot(regs, instruction, ma);
568 regs->pr = regs->pc + 4;
569 regs->pc += SH_PC_12BIT_OFFSET(instruction);
575 /* handle non-delay-slot instruction */
577 ret = handle_unaligned_ins(instruction, regs, ma);
579 regs->pc += instruction_size(instruction);
584 * Handle various address error exceptions:
585 * - instruction address error:
587 * PC >= 0x80000000 in user mode
588 * - data address error (read and write)
589 * misaligned data access
590 * access to >= 0x80000000 is user mode
591 * Unfortuntaly we can't distinguish between instruction address error
592 * and data address errors caused by read accesses.
594 asmlinkage void do_address_error(struct pt_regs *regs,
595 unsigned long writeaccess,
596 unsigned long address)
598 unsigned long error_code = 0;
601 insn_size_t instruction;
604 /* Intentional ifdef */
605 #ifdef CONFIG_CPU_HAS_SR_RB
606 error_code = lookup_exception_vector();
611 if (user_mode(regs)) {
612 int si_code = BUS_ADRERR;
619 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
620 sizeof(instruction))) {
626 /* shout about userspace fixups */
628 printk(KERN_NOTICE "Unaligned userspace access "
629 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
630 current->comm, current->pid, (void *)regs->pc,
640 regs->pc += instruction_size(instruction);
645 /* bad PC is not something we can fix */
647 si_code = BUS_ADRALN;
652 tmp = handle_unaligned_access(instruction, regs,
653 &user_mem_access, 0);
659 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
660 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
663 info.si_signo = SIGBUS;
665 info.si_code = si_code;
666 info.si_addr = (void __user *)address;
667 force_sig_info(SIGBUS, &info, current);
672 die("unaligned program counter", regs, error_code);
675 if (copy_from_user(&instruction, (void __user *)(regs->pc),
676 sizeof(instruction))) {
677 /* Argh. Fault on the instruction itself.
678 This should never happen non-SMP
681 die("insn faulting in do_address_error", regs, 0);
684 if (se_kernmode_warn)
685 printk(KERN_NOTICE "Unaligned kernel access "
686 "on behalf of \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
687 current->comm, current->pid, (void *)regs->pc,
690 handle_unaligned_access(instruction, regs,
691 &user_mem_access, 0);
698 * SH-DSP support gerg@snapgear.com.
700 int is_dsp_inst(struct pt_regs *regs)
702 unsigned short inst = 0;
705 * Safe guard if DSP mode is already enabled or we're lacking
706 * the DSP altogether.
708 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
711 get_user(inst, ((unsigned short *) regs->pc));
715 /* Check for any type of DSP or support instruction */
716 if ((inst == 0xf000) || (inst == 0x4000))
722 #define is_dsp_inst(regs) (0)
723 #endif /* CONFIG_SH_DSP */
725 #ifdef CONFIG_CPU_SH2A
726 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
727 unsigned long r6, unsigned long r7,
728 struct pt_regs __regs)
733 case TRAP_DIVZERO_ERROR:
734 info.si_code = FPE_INTDIV;
736 case TRAP_DIVOVF_ERROR:
737 info.si_code = FPE_INTOVF;
741 force_sig_info(SIGFPE, &info, current);
745 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
746 unsigned long r6, unsigned long r7,
747 struct pt_regs __regs)
749 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
750 unsigned long error_code;
751 struct task_struct *tsk = current;
753 #ifdef CONFIG_SH_FPU_EMU
754 unsigned short inst = 0;
757 get_user(inst, (unsigned short*)regs->pc);
759 err = do_fpu_inst(inst, regs);
761 regs->pc += instruction_size(inst);
764 /* not a FPU inst. */
768 /* Check if it's a DSP instruction */
769 if (is_dsp_inst(regs)) {
770 /* Enable DSP mode, and restart instruction. */
773 tsk->thread.dsp_status.status |= SR_DSP;
778 error_code = lookup_exception_vector();
781 force_sig(SIGILL, tsk);
782 die_if_no_fixup("reserved instruction", regs, error_code);
785 #ifdef CONFIG_SH_FPU_EMU
786 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
789 * bfs: 8fxx: PC+=d*2+4;
790 * bts: 8dxx: PC+=d*2+4;
791 * bra: axxx: PC+=D*2+4;
792 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
793 * braf:0x23: PC+=Rn*2+4;
794 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
796 * jsr: 4x0b: PC=Rn after PR=PC+4;
799 if (((inst & 0xf000) == 0xb000) || /* bsr */
800 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
801 ((inst & 0xf0ff) == 0x400b)) /* jsr */
802 regs->pr = regs->pc + 4;
804 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
805 regs->pc += SH_PC_8BIT_OFFSET(inst);
809 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
810 regs->pc += SH_PC_12BIT_OFFSET(inst);
814 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
815 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
819 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
820 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
824 if ((inst & 0xffff) == 0x000b) { /* rts */
833 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
834 unsigned long r6, unsigned long r7,
835 struct pt_regs __regs)
837 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
839 struct task_struct *tsk = current;
841 if (kprobe_handle_illslot(regs->pc) == 0)
844 #ifdef CONFIG_SH_FPU_EMU
845 get_user(inst, (unsigned short *)regs->pc + 1);
846 if (!do_fpu_inst(inst, regs)) {
847 get_user(inst, (unsigned short *)regs->pc);
848 if (!emulate_branch(inst, regs))
850 /* fault in branch.*/
852 /* not a FPU inst. */
855 inst = lookup_exception_vector();
858 force_sig(SIGILL, tsk);
859 die_if_no_fixup("illegal slot instruction", regs, inst);
862 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
863 unsigned long r6, unsigned long r7,
864 struct pt_regs __regs)
866 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
869 ex = lookup_exception_vector();
870 die_if_kernel("exception", regs, ex);
873 #if defined(CONFIG_SH_STANDARD_BIOS)
874 void *gdb_vbr_vector;
876 static inline void __init gdb_vbr_init(void)
878 register unsigned long vbr;
881 * Read the old value of the VBR register to initialise
882 * the vector through which debug and BIOS traps are
883 * delegated by the Linux trap handler.
885 asm volatile("stc vbr, %0" : "=r" (vbr));
887 gdb_vbr_vector = (void *)(vbr + 0x100);
888 printk("Setting GDB trap vector to 0x%08lx\n",
889 (unsigned long)gdb_vbr_vector);
893 void __cpuinit per_cpu_trap_init(void)
895 extern void *vbr_base;
897 #ifdef CONFIG_SH_STANDARD_BIOS
898 if (raw_smp_processor_id() == 0)
902 /* NOTE: The VBR value should be at P1
903 (or P2, virtural "fixed" address space).
904 It's definitely should not in physical address. */
906 asm volatile("ldc %0, vbr"
912 void *set_exception_table_vec(unsigned int vec, void *handler)
914 extern void *exception_handling_table[];
917 old_handler = exception_handling_table[vec];
918 exception_handling_table[vec] = handler;
922 void __init trap_init(void)
924 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
925 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
927 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
928 defined(CONFIG_SH_FPU_EMU)
930 * For SH-4 lacking an FPU, treat floating point instructions as
931 * reserved. They'll be handled in the math-emu case, or faulted on
934 set_exception_table_evt(0x800, do_reserved_inst);
935 set_exception_table_evt(0x820, do_illegal_slot_inst);
936 #elif defined(CONFIG_SH_FPU)
937 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
938 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
941 #ifdef CONFIG_CPU_SH2
942 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
944 #ifdef CONFIG_CPU_SH2A
945 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
946 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
948 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
953 set_exception_table_vec(TRAP_UBC, break_point_trap);
956 /* Setup VBR for boot cpu */
960 void show_stack(struct task_struct *tsk, unsigned long *sp)
967 sp = (unsigned long *)current_stack_pointer;
969 sp = (unsigned long *)tsk->thread.sp;
971 stack = (unsigned long)sp;
972 dump_mem("Stack: ", stack, THREAD_SIZE +
973 (unsigned long)task_stack_page(tsk));
974 show_trace(tsk, sp, NULL);
977 void dump_stack(void)
979 show_stack(NULL, NULL);
981 EXPORT_SYMBOL(dump_stack);
983 #ifdef CONFIG_PROC_FS
985 * This needs to be done after sysctl_init, otherwise sys/ will be
986 * overwritten. Actually, this shouldn't be in sys/ at all since
987 * it isn't a sysctl, and it doesn't contain sysctl information.
988 * We now locate it in /proc/cpu/alignment instead.
990 static int __init alignment_init(void)
992 struct proc_dir_entry *dir, *res;
994 dir = proc_mkdir("cpu", NULL);
998 res = proc_create_data("alignment", S_IWUSR | S_IRUGO, dir,
999 &alignment_proc_fops, &se_usermode);
1003 res = proc_create_data("kernel_alignment", S_IWUSR | S_IRUGO, dir,
1004 &alignment_proc_fops, &se_kernmode_warn);
1011 fs_initcall(alignment_init);