2 * Cell Broadband Engine OProfile Support
4 * (C) Copyright IBM Corporation 2006
6 * Author: David Erb (djerb@us.ibm.com)
8 * Carl Love <carll@us.ibm.com>
9 * Maynard Johnson <maynardj@us.ibm.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/cpufreq.h>
18 #include <linux/delay.h>
19 #include <linux/init.h>
20 #include <linux/jiffies.h>
21 #include <linux/kthread.h>
22 #include <linux/oprofile.h>
23 #include <linux/percpu.h>
24 #include <linux/smp.h>
25 #include <linux/spinlock.h>
26 #include <linux/timer.h>
27 #include <asm/cell-pmu.h>
28 #include <asm/cputable.h>
29 #include <asm/firmware.h>
31 #include <asm/oprofile_impl.h>
32 #include <asm/processor.h>
34 #include <asm/ptrace.h>
37 #include <asm/system.h>
38 #include <asm/cell-regs.h>
40 #include "../platforms/cell/interrupt.h"
41 #include "cell/pr_util.h"
43 #define PPU_PROFILING 0
44 #define SPU_PROFILING_CYCLES 1
45 #define SPU_PROFILING_EVENTS 2
47 #define SPU_EVENT_NUM_START 4100
48 #define SPU_EVENT_NUM_STOP 4399
49 #define SPU_PROFILE_EVENT_ADDR 4363 /* spu, address trace, decimal */
50 #define SPU_PROFILE_EVENT_ADDR_MASK_A 0x146 /* sub unit set to zero */
51 #define SPU_PROFILE_EVENT_ADDR_MASK_B 0x186 /* sub unit set to zero */
53 #define NUM_SPUS_PER_NODE 8
54 #define SPU_CYCLES_EVENT_NUM 2 /* event number for SPU_CYCLES */
56 #define PPU_CYCLES_EVENT_NUM 1 /* event number for CYCLES */
57 #define PPU_CYCLES_GRP_NUM 1 /* special group number for identifying
60 #define CBE_COUNT_ALL_CYCLES 0x42800000 /* PPU cycle event specifier */
62 #define NUM_THREADS 2 /* number of physical threads in
65 #define NUM_DEBUG_BUS_WORDS 4
66 #define NUM_INPUT_BUS_WORDS 2
68 #define MAX_SPU_COUNT 0xFFFFFF /* maximum 24 bit LFSR value */
70 /* Minumum HW interval timer setting to send value to trace buffer is 10 cycle.
71 * To configure counter to send value every N cycles set counter to
74 #define NUM_INTERVAL_CYC 0xFFFFFFFF - 10
77 * spu_cycle_reset is the number of cycles between samples.
78 * This variable is used for SPU profiling and should ONLY be set
79 * at the beginning of cell_reg_setup; otherwise, it's read-only.
81 static unsigned int spu_cycle_reset;
82 static unsigned int profiling_mode;
83 static int spu_evnt_phys_spu_indx;
85 struct pmc_cntrl_data {
89 unsigned long enabled;
93 * ibm,cbe-perftools rtas parameters
96 u16 cpu; /* Processor to modify */
97 u16 sub_unit; /* hw subunit this applies to (if applicable)*/
98 short int signal_group; /* Signal Group to Enable/Disable */
99 u8 bus_word; /* Enable/Disable on this Trace/Trigger/Event
100 * Bus Word(s) (bitmask)
102 u8 bit; /* Trigger/Event bit (if applicable) */
106 * rtas call arguments
110 SUBFUNC_ACTIVATE = 2,
111 SUBFUNC_DEACTIVATE = 3,
115 PASSTHRU_DISABLE = 2,
130 u32 debug_bus_control;
131 struct pm_cntrl pm_cntrl;
132 u32 pm07_cntrl[NR_PHYS_CTRS];
135 #define GET_SUB_UNIT(x) ((x & 0x0000f000) >> 12)
136 #define GET_BUS_WORD(x) ((x & 0x000000f0) >> 4)
137 #define GET_BUS_TYPE(x) ((x & 0x00000300) >> 8)
138 #define GET_POLARITY(x) ((x & 0x00000002) >> 1)
139 #define GET_COUNT_CYCLES(x) (x & 0x00000001)
140 #define GET_INPUT_CONTROL(x) ((x & 0x00000004) >> 2)
142 static DEFINE_PER_CPU(unsigned long[NR_PHYS_CTRS], pmc_values);
143 static unsigned long spu_pm_cnt[MAX_NUMNODES * NUM_SPUS_PER_NODE];
144 static struct pmc_cntrl_data pmc_cntrl[NUM_THREADS][NR_PHYS_CTRS];
147 * The CELL profiling code makes rtas calls to setup the debug bus to
148 * route the performance signals. Additionally, SPU profiling requires
149 * a second rtas call to setup the hardware to capture the SPU PCs.
150 * The EIO error value is returned if the token lookups or the rtas
151 * call fail. The EIO error number is the best choice of the existing
152 * error numbers. The probability of rtas related error is very low. But
153 * by returning EIO and printing additional information to dmsg the user
154 * will know that OProfile did not start and dmesg will tell them why.
155 * OProfile does not support returning errors on Stop. Not a huge issue
156 * since failure to reset the debug bus or stop the SPU PC collection is
157 * not a fatel issue. Chances are if the Stop failed, Start doesn't work
162 * Interpetation of hdw_thread:
163 * 0 - even virtual cpus 0, 2, 4,...
164 * 1 - odd virtual cpus 1, 3, 5, ...
166 * FIXME: this is strictly wrong, we need to clean this up in a number
167 * of places. It works for now. -arnd
169 static u32 hdw_thread;
171 static u32 virt_cntr_inter_mask;
172 static struct timer_list timer_virt_cntr;
173 static struct timer_list timer_spu_event_swap;
176 * pm_signal needs to be global since it is initialized in
177 * cell_reg_setup at the time when the necessary information
180 static struct pm_signal pm_signal[NR_PHYS_CTRS];
181 static int pm_rtas_token; /* token for debug bus setup call */
182 static int spu_rtas_token; /* token for SPU cycle profiling */
184 static u32 reset_value[NR_PHYS_CTRS];
185 static int num_counters;
186 static int oprofile_running;
187 static DEFINE_SPINLOCK(cntr_lock);
189 static u32 ctr_enabled;
191 static unsigned char input_bus[NUM_INPUT_BUS_WORDS];
194 * Firmware interface functions
197 rtas_ibm_cbe_perftools(int subfunc, int passthru,
198 void *address, unsigned long length)
200 u64 paddr = __pa(address);
202 return rtas_call(pm_rtas_token, 5, 1, NULL, subfunc,
203 passthru, paddr >> 32, paddr & 0xffffffff, length);
206 static void pm_rtas_reset_signals(u32 node)
209 struct pm_signal pm_signal_local;
212 * The debug bus is being set to the passthru disable state.
213 * However, the FW still expects atleast one legal signal routing
214 * entry or it will return an error on the arguments. If we don't
215 * supply a valid entry, we must ignore all return values. Ignoring
216 * all return values means we might miss an error we should be
220 /* fw expects physical cpu #. */
221 pm_signal_local.cpu = node;
222 pm_signal_local.signal_group = 21;
223 pm_signal_local.bus_word = 1;
224 pm_signal_local.sub_unit = 0;
225 pm_signal_local.bit = 0;
227 ret = rtas_ibm_cbe_perftools(SUBFUNC_RESET, PASSTHRU_DISABLE,
229 sizeof(struct pm_signal));
233 * Not a fatal error. For Oprofile stop, the oprofile
234 * functions do not support returning an error for
235 * failure to stop OProfile.
237 printk(KERN_WARNING "%s: rtas returned: %d\n",
241 static int pm_rtas_activate_signals(u32 node, u32 count)
245 struct pm_signal pm_signal_local[NR_PHYS_CTRS];
248 * There is no debug setup required for the cycles event.
249 * Note that only events in the same group can be used.
250 * Otherwise, there will be conflicts in correctly routing
251 * the signals on the debug bus. It is the responsiblity
252 * of the OProfile user tool to check the events are in
256 for (j = 0; j < count; j++) {
257 if (pm_signal[j].signal_group != PPU_CYCLES_GRP_NUM) {
259 /* fw expects physical cpu # */
260 pm_signal_local[i].cpu = node;
261 pm_signal_local[i].signal_group
262 = pm_signal[j].signal_group;
263 pm_signal_local[i].bus_word = pm_signal[j].bus_word;
264 pm_signal_local[i].sub_unit = pm_signal[j].sub_unit;
265 pm_signal_local[i].bit = pm_signal[j].bit;
271 ret = rtas_ibm_cbe_perftools(SUBFUNC_ACTIVATE, PASSTHRU_ENABLE,
273 i * sizeof(struct pm_signal));
276 printk(KERN_WARNING "%s: rtas returned: %d\n",
286 * PM Signal functions
288 static void set_pm_event(u32 ctr, int event, u32 unit_mask)
292 u32 bus_word, bus_type, count_cycles, polarity, input_control;
295 if (event == PPU_CYCLES_EVENT_NUM) {
296 /* Special Event: Count all cpu cycles */
297 pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES;
298 p = &(pm_signal[ctr]);
299 p->signal_group = PPU_CYCLES_GRP_NUM;
305 pm_regs.pm07_cntrl[ctr] = 0;
308 bus_word = GET_BUS_WORD(unit_mask);
309 bus_type = GET_BUS_TYPE(unit_mask);
310 count_cycles = GET_COUNT_CYCLES(unit_mask);
311 polarity = GET_POLARITY(unit_mask);
312 input_control = GET_INPUT_CONTROL(unit_mask);
313 signal_bit = (event % 100);
315 p = &(pm_signal[ctr]);
317 p->signal_group = event / 100;
318 p->bus_word = bus_word;
319 p->sub_unit = GET_SUB_UNIT(unit_mask);
321 pm_regs.pm07_cntrl[ctr] = 0;
322 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);
323 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);
324 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);
327 * Some of the islands signal selection is based on 64 bit words.
328 * The debug bus words are 32 bits, the input words to the performance
329 * counters are defined as 32 bits. Need to convert the 64 bit island
330 * specification to the appropriate 32 input bit and bus word for the
331 * performance counter event selection. See the CELL Performance
332 * monitoring signals manual and the Perf cntr hardware descriptions
335 if (input_control == 0) {
336 if (signal_bit > 31) {
340 else if (bus_word == 0xc)
344 if ((bus_type == 0) && p->signal_group >= 60)
346 if ((bus_type == 1) && p->signal_group >= 50)
349 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit);
351 pm_regs.pm07_cntrl[ctr] = 0;
355 for (i = 0; i < NUM_DEBUG_BUS_WORDS; i++) {
356 if (bus_word & (1 << i)) {
357 pm_regs.debug_bus_control |=
358 (bus_type << (30 - (2 * i)));
360 for (j = 0; j < NUM_INPUT_BUS_WORDS; j++) {
361 if (input_bus[j] == 0xff) {
363 pm_regs.group_control |=
364 (i << (30 - (2 * j)));
375 static void write_pm_cntrl(int cpu)
378 * Oprofile will use 32 bit counters, set bits 7:10 to 0
379 * pmregs.pm_cntrl is a global
383 if (pm_regs.pm_cntrl.enable == 1)
384 val |= CBE_PM_ENABLE_PERF_MON;
386 if (pm_regs.pm_cntrl.stop_at_max == 1)
387 val |= CBE_PM_STOP_AT_MAX;
389 if (pm_regs.pm_cntrl.trace_mode != 0)
390 val |= CBE_PM_TRACE_MODE_SET(pm_regs.pm_cntrl.trace_mode);
392 if (pm_regs.pm_cntrl.trace_buf_ovflw == 1)
393 val |= CBE_PM_TRACE_BUF_OVFLW(pm_regs.pm_cntrl.trace_buf_ovflw);
394 if (pm_regs.pm_cntrl.freeze == 1)
395 val |= CBE_PM_FREEZE_ALL_CTRS;
397 val |= CBE_PM_SPU_ADDR_TRACE_SET(pm_regs.pm_cntrl.spu_addr_trace);
400 * Routine set_count_mode must be called previously to set
401 * the count mode based on the user selection of user and kernel.
403 val |= CBE_PM_COUNT_MODE_SET(pm_regs.pm_cntrl.count_mode);
404 cbe_write_pm(cpu, pm_control, val);
408 set_count_mode(u32 kernel, u32 user)
411 * The user must specify user and kernel if they want them. If
412 * neither is specified, OProfile will count in hypervisor mode.
413 * pm_regs.pm_cntrl is a global
417 pm_regs.pm_cntrl.count_mode = CBE_COUNT_ALL_MODES;
419 pm_regs.pm_cntrl.count_mode =
420 CBE_COUNT_SUPERVISOR_MODE;
423 pm_regs.pm_cntrl.count_mode = CBE_COUNT_PROBLEM_MODE;
425 pm_regs.pm_cntrl.count_mode =
426 CBE_COUNT_HYPERVISOR_MODE;
430 static inline void enable_ctr(u32 cpu, u32 ctr, u32 *pm07_cntrl)
433 pm07_cntrl[ctr] |= CBE_PM_CTR_ENABLE;
434 cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]);
438 * Oprofile is expected to collect data on all CPUs simultaneously.
439 * However, there is one set of performance counters per node. There are
440 * two hardware threads or virtual CPUs on each node. Hence, OProfile must
441 * multiplex in time the performance counter collection on the two virtual
442 * CPUs. The multiplexing of the performance counters is done by this
443 * virtual counter routine.
445 * The pmc_values used below is defined as 'per-cpu' but its use is
446 * more akin to 'per-node'. We need to store two sets of counter
447 * values per node -- one for the previous run and one for the next.
448 * The per-cpu[NR_PHYS_CTRS] gives us the storage we need. Each odd/even
449 * pair of per-cpu arrays is used for storing the previous and next
450 * pmc values for a given node.
451 * NOTE: We use the per-cpu variable to improve cache performance.
453 * This routine will alternate loading the virtual counters for
456 static void cell_virtual_cntr(unsigned long data)
458 int i, prev_hdw_thread, next_hdw_thread;
463 * Make sure that the interrupt_hander and the virt counter are
464 * not both playing with the counters on the same node.
467 spin_lock_irqsave(&cntr_lock, flags);
469 prev_hdw_thread = hdw_thread;
471 /* switch the cpu handling the interrupts */
472 hdw_thread = 1 ^ hdw_thread;
473 next_hdw_thread = hdw_thread;
475 pm_regs.group_control = 0;
476 pm_regs.debug_bus_control = 0;
478 for (i = 0; i < NUM_INPUT_BUS_WORDS; i++)
482 * There are some per thread events. Must do the
483 * set event, for the thread that is being started
485 for (i = 0; i < num_counters; i++)
487 pmc_cntrl[next_hdw_thread][i].evnts,
488 pmc_cntrl[next_hdw_thread][i].masks);
491 * The following is done only once per each node, but
492 * we need cpu #, not node #, to pass to the cbe_xxx functions.
494 for_each_online_cpu(cpu) {
495 if (cbe_get_hw_thread_id(cpu))
499 * stop counters, save counter values, restore counts
500 * for previous thread
503 cbe_disable_pm_interrupts(cpu);
504 for (i = 0; i < num_counters; i++) {
505 per_cpu(pmc_values, cpu + prev_hdw_thread)[i]
506 = cbe_read_ctr(cpu, i);
508 if (per_cpu(pmc_values, cpu + next_hdw_thread)[i]
510 /* If the cntr value is 0xffffffff, we must
511 * reset that to 0xfffffff0 when the current
512 * thread is restarted. This will generate a
513 * new interrupt and make sure that we never
514 * restore the counters to the max value. If
515 * the counters were restored to the max value,
516 * they do not increment and no interrupts are
517 * generated. Hence no more samples will be
518 * collected on that cpu.
520 cbe_write_ctr(cpu, i, 0xFFFFFFF0);
522 cbe_write_ctr(cpu, i,
525 next_hdw_thread)[i]);
529 * Switch to the other thread. Change the interrupt
530 * and control regs to be scheduled on the CPU
531 * corresponding to the thread to execute.
533 for (i = 0; i < num_counters; i++) {
534 if (pmc_cntrl[next_hdw_thread][i].enabled) {
536 * There are some per thread events.
537 * Must do the set event, enable_cntr
543 cbe_write_pm07_control(cpu, i, 0);
547 /* Enable interrupts on the CPU thread that is starting */
548 cbe_enable_pm_interrupts(cpu, next_hdw_thread,
549 virt_cntr_inter_mask);
553 spin_unlock_irqrestore(&cntr_lock, flags);
555 mod_timer(&timer_virt_cntr, jiffies + HZ / 10);
558 static void start_virt_cntrs(void)
560 init_timer(&timer_virt_cntr);
561 timer_virt_cntr.function = cell_virtual_cntr;
562 timer_virt_cntr.data = 0UL;
563 timer_virt_cntr.expires = jiffies + HZ / 10;
564 add_timer(&timer_virt_cntr);
567 static int cell_reg_setup_spu_cycles(struct op_counter_config *ctr,
568 struct op_system_config *sys, int num_ctrs)
570 spu_cycle_reset = ctr[0].count;
573 * Each node will need to make the rtas call to start
574 * and stop SPU profiling. Get the token once and store it.
576 spu_rtas_token = rtas_token("ibm,cbe-spu-perftools");
578 if (unlikely(spu_rtas_token == RTAS_UNKNOWN_SERVICE)) {
580 "%s: rtas token ibm,cbe-spu-perftools unknown\n",
587 /* Unfortunately, the hardware will only support event profiling
588 * on one SPU per node at a time. Therefore, we must time slice
589 * the profiling across all SPUs in the node. Note, we do this
590 * in parallel for each node. The following routine is called
591 * periodically based on kernel timer to switch which SPU is
592 * being monitored in a round robbin fashion.
594 static void spu_evnt_swap(unsigned long data)
597 int cur_phys_spu, nxt_phys_spu, cur_spu_evnt_phys_spu_indx;
604 /* enable interrupts on cntr 0 */
605 interrupt_mask = CBE_PM_CTR_OVERFLOW_INTR(0);
609 /* Make sure spu event interrupt handler and spu event swap
610 * don't access the counters simultaneously.
612 spin_lock_irqsave(&cntr_lock, flags);
614 cur_spu_evnt_phys_spu_indx = spu_evnt_phys_spu_indx;
616 if (++(spu_evnt_phys_spu_indx) == NUM_SPUS_PER_NODE)
617 spu_evnt_phys_spu_indx = 0;
619 pm_signal[0].sub_unit = spu_evnt_phys_spu_indx;
620 pm_signal[1].sub_unit = spu_evnt_phys_spu_indx;
621 pm_signal[2].sub_unit = spu_evnt_phys_spu_indx;
623 /* switch the SPU being profiled on each node */
624 for_each_online_cpu(cpu) {
625 if (cbe_get_hw_thread_id(cpu))
628 node = cbe_cpu_to_node(cpu);
629 cur_phys_spu = (node * NUM_SPUS_PER_NODE)
630 + cur_spu_evnt_phys_spu_indx;
631 nxt_phys_spu = (node * NUM_SPUS_PER_NODE)
632 + spu_evnt_phys_spu_indx;
635 * stop counters, save counter values, restore counts
636 * for previous physical SPU
639 cbe_disable_pm_interrupts(cpu);
641 spu_pm_cnt[cur_phys_spu]
642 = cbe_read_ctr(cpu, 0);
644 /* restore previous count for the next spu to sample */
645 /* NOTE, hardware issue, counter will not start if the
646 * counter value is at max (0xFFFFFFFF).
648 if (spu_pm_cnt[nxt_phys_spu] >= 0xFFFFFFFF)
649 cbe_write_ctr(cpu, 0, 0xFFFFFFF0);
651 cbe_write_ctr(cpu, 0, spu_pm_cnt[nxt_phys_spu]);
653 pm_rtas_reset_signals(cbe_cpu_to_node(cpu));
655 /* setup the debug bus measure the one event and
656 * the two events to route the next SPU's PC on
659 ret = pm_rtas_activate_signals(cbe_cpu_to_node(cpu), 3);
662 "%s: pm_rtas_activate_signals failed, SPU event swap\n",
665 /* clear the trace buffer, don't want to take PC for
667 cbe_write_pm(cpu, trace_address, 0);
669 enable_ctr(cpu, 0, pm_regs.pm07_cntrl);
671 /* Enable interrupts on the CPU thread that is starting */
672 cbe_enable_pm_interrupts(cpu, hdw_thread,
677 spin_unlock_irqrestore(&cntr_lock, flags);
679 /* swap approximately every 0.1 seconds */
680 mod_timer(&timer_spu_event_swap, jiffies + HZ / 25);
683 static void start_spu_event_swap(void)
685 init_timer(&timer_spu_event_swap);
686 timer_spu_event_swap.function = spu_evnt_swap;
687 timer_spu_event_swap.data = 0UL;
688 timer_spu_event_swap.expires = jiffies + HZ / 25;
689 add_timer(&timer_spu_event_swap);
692 static int cell_reg_setup_spu_events(struct op_counter_config *ctr,
693 struct op_system_config *sys, int num_ctrs)
697 /* routine is called once for all nodes */
699 spu_evnt_phys_spu_indx = 0;
701 * For all events except PPU CYCLEs, each node will need to make
702 * the rtas cbe-perftools call to setup and reset the debug bus.
703 * Make the token lookup call once and store it in the global
704 * variable pm_rtas_token.
706 pm_rtas_token = rtas_token("ibm,cbe-perftools");
708 if (unlikely(pm_rtas_token == RTAS_UNKNOWN_SERVICE)) {
710 "%s: rtas token ibm,cbe-perftools unknown\n",
715 /* setup the pm_control register settings,
716 * settings will be written per node by the
717 * cell_cpu_setup() function.
719 pm_regs.pm_cntrl.trace_buf_ovflw = 1;
721 /* Use the occurrence trace mode to have SPU PC saved
722 * to the trace buffer. Occurrence data in trace buffer
723 * is not used. Bit 2 must be set to store SPU addresses.
725 pm_regs.pm_cntrl.trace_mode = 2;
727 pm_regs.pm_cntrl.spu_addr_trace = 0x1; /* using debug bus
730 /* setup the debug bus event array with the SPU PC routing events.
731 * Note, pm_signal[0] will be filled in by set_pm_event() call below.
733 pm_signal[1].signal_group = SPU_PROFILE_EVENT_ADDR / 100;
734 pm_signal[1].bus_word = GET_BUS_WORD(SPU_PROFILE_EVENT_ADDR_MASK_A);
735 pm_signal[1].bit = SPU_PROFILE_EVENT_ADDR % 100;
736 pm_signal[1].sub_unit = spu_evnt_phys_spu_indx;
738 pm_signal[2].signal_group = SPU_PROFILE_EVENT_ADDR / 100;
739 pm_signal[2].bus_word = GET_BUS_WORD(SPU_PROFILE_EVENT_ADDR_MASK_B);
740 pm_signal[2].bit = SPU_PROFILE_EVENT_ADDR % 100;
741 pm_signal[2].sub_unit = spu_evnt_phys_spu_indx;
743 /* Set the user selected spu event to profile on,
744 * note, only one SPU profiling event is supported
746 num_counters = 1; /* Only support one SPU event at a time */
747 set_pm_event(0, ctr[0].event, ctr[0].unit_mask);
749 reset_value[0] = 0xFFFFFFFF - ctr[0].count;
751 /* global, used by cell_cpu_setup */
754 /* Initialize the count for each SPU to the reset value */
755 for (i=0; i < MAX_NUMNODES * NUM_SPUS_PER_NODE; i++)
756 spu_pm_cnt[i] = reset_value[0];
761 static int cell_reg_setup_ppu(struct op_counter_config *ctr,
762 struct op_system_config *sys, int num_ctrs)
764 /* routine is called once for all nodes */
767 num_counters = num_ctrs;
769 if (unlikely(num_ctrs > NR_PHYS_CTRS)) {
771 "%s: Oprofile, number of specified events " \
772 "exceeds number of physical counters\n",
777 set_count_mode(sys->enable_kernel, sys->enable_user);
779 /* Setup the thread 0 events */
780 for (i = 0; i < num_ctrs; ++i) {
782 pmc_cntrl[0][i].evnts = ctr[i].event;
783 pmc_cntrl[0][i].masks = ctr[i].unit_mask;
784 pmc_cntrl[0][i].enabled = ctr[i].enabled;
785 pmc_cntrl[0][i].vcntr = i;
787 for_each_possible_cpu(j)
788 per_cpu(pmc_values, j)[i] = 0;
792 * Setup the thread 1 events, map the thread 0 event to the
793 * equivalent thread 1 event.
795 for (i = 0; i < num_ctrs; ++i) {
796 if ((ctr[i].event >= 2100) && (ctr[i].event <= 2111))
797 pmc_cntrl[1][i].evnts = ctr[i].event + 19;
798 else if (ctr[i].event == 2203)
799 pmc_cntrl[1][i].evnts = ctr[i].event;
800 else if ((ctr[i].event >= 2200) && (ctr[i].event <= 2215))
801 pmc_cntrl[1][i].evnts = ctr[i].event + 16;
803 pmc_cntrl[1][i].evnts = ctr[i].event;
805 pmc_cntrl[1][i].masks = ctr[i].unit_mask;
806 pmc_cntrl[1][i].enabled = ctr[i].enabled;
807 pmc_cntrl[1][i].vcntr = i;
810 for (i = 0; i < NUM_INPUT_BUS_WORDS; i++)
814 * Our counters count up, and "count" refers to
815 * how much before the next interrupt, and we interrupt
816 * on overflow. So we calculate the starting value
817 * which will give us "count" until overflow.
818 * Then we set the events on the enabled counters.
820 for (i = 0; i < num_counters; ++i) {
821 /* start with virtual counter set 0 */
822 if (pmc_cntrl[0][i].enabled) {
823 /* Using 32bit counters, reset max - count */
824 reset_value[i] = 0xFFFFFFFF - ctr[i].count;
826 pmc_cntrl[0][i].evnts,
827 pmc_cntrl[0][i].masks);
829 /* global, used by cell_cpu_setup */
830 ctr_enabled |= (1 << i);
834 /* initialize the previous counts for the virtual cntrs */
835 for_each_online_cpu(cpu)
836 for (i = 0; i < num_counters; ++i) {
837 per_cpu(pmc_values, cpu)[i] = reset_value[i];
844 /* This function is called once for all cpus combined */
845 static int cell_reg_setup(struct op_counter_config *ctr,
846 struct op_system_config *sys, int num_ctrs)
851 /* initialize the spu_arr_trace value, will be reset if
852 * doing spu event profiling.
854 pm_regs.group_control = 0;
855 pm_regs.debug_bus_control = 0;
856 pm_regs.pm_cntrl.stop_at_max = 1;
857 pm_regs.pm_cntrl.trace_mode = 0;
858 pm_regs.pm_cntrl.freeze = 1;
859 pm_regs.pm_cntrl.trace_buf_ovflw = 0;
860 pm_regs.pm_cntrl.spu_addr_trace = 0;
863 * For all events except PPU CYCLEs, each node will need to make
864 * the rtas cbe-perftools call to setup and reset the debug bus.
865 * Make the token lookup call once and store it in the global
866 * variable pm_rtas_token.
868 pm_rtas_token = rtas_token("ibm,cbe-perftools");
870 if (unlikely(pm_rtas_token == RTAS_UNKNOWN_SERVICE)) {
872 "%s: rtas token ibm,cbe-perftools unknown\n",
877 if (ctr[0].event == SPU_CYCLES_EVENT_NUM) {
878 profiling_mode = SPU_PROFILING_CYCLES;
879 ret = cell_reg_setup_spu_cycles(ctr, sys, num_ctrs);
880 } else if ((ctr[0].event >= SPU_EVENT_NUM_START) &&
881 (ctr[0].event <= SPU_EVENT_NUM_STOP)) {
882 profiling_mode = SPU_PROFILING_EVENTS;
883 spu_cycle_reset = ctr[0].count;
885 /* for SPU event profiling, need to setup the
886 * pm_signal array with the events to route the
887 * SPU PC before making the FW call. Note, only
888 * one SPU event for profiling can be specified
891 cell_reg_setup_spu_events(ctr, sys, num_ctrs);
893 profiling_mode = PPU_PROFILING;
894 ret = cell_reg_setup_ppu(ctr, sys, num_ctrs);
902 /* This function is called once for each cpu */
903 static int cell_cpu_setup(struct op_counter_config *cntr)
905 u32 cpu = smp_processor_id();
910 /* Cycle based SPU profiling does not use the performance
911 * counters. The trace array is configured to collect
914 if (profiling_mode == SPU_PROFILING_CYCLES)
917 /* There is one performance monitor per processor chip (i.e. node),
918 * so we only need to perform this function once per node.
920 if (cbe_get_hw_thread_id(cpu))
923 /* Stop all counters */
925 cbe_disable_pm_interrupts(cpu);
927 cbe_write_pm(cpu, pm_start_stop, 0);
928 cbe_write_pm(cpu, group_control, pm_regs.group_control);
929 cbe_write_pm(cpu, debug_bus_control, pm_regs.debug_bus_control);
932 for (i = 0; i < num_counters; ++i) {
933 if (ctr_enabled & (1 << i)) {
934 pm_signal[num_enabled].cpu = cbe_cpu_to_node(cpu);
940 * The pm_rtas_activate_signals will return -EIO if the FW
943 if (profiling_mode == SPU_PROFILING_EVENTS) {
944 /* For SPU event profiling also need to setup the
947 ret = pm_rtas_activate_signals(cbe_cpu_to_node(cpu),
949 /* store PC from debug bus to Trace buffer as often
950 * as possible (every 10 cycles)
952 cbe_write_pm(cpu, pm_interval, NUM_INTERVAL_CYC);
955 return pm_rtas_activate_signals(cbe_cpu_to_node(cpu),
960 #define MAXLFSR 0xFFFFFF
962 /* precomputed table of 24 bit LFSR values */
963 static int initial_lfsr[] = {
964 8221349, 12579195, 5379618, 10097839, 7512963, 7519310, 3955098, 10753424,
965 15507573, 7458917, 285419, 2641121, 9780088, 3915503, 6668768, 1548716,
966 4885000, 8774424, 9650099, 2044357, 2304411, 9326253, 10332526, 4421547,
967 3440748, 10179459, 13332843, 10375561, 1313462, 8375100, 5198480, 6071392,
968 9341783, 1526887, 3985002, 1439429, 13923762, 7010104, 11969769, 4547026,
969 2040072, 4025602, 3437678, 7939992, 11444177, 4496094, 9803157, 10745556,
970 3671780, 4257846, 5662259, 13196905, 3237343, 12077182, 16222879, 7587769,
971 14706824, 2184640, 12591135, 10420257, 7406075, 3648978, 11042541, 15906893,
972 11914928, 4732944, 10695697, 12928164, 11980531, 4430912, 11939291, 2917017,
973 6119256, 4172004, 9373765, 8410071, 14788383, 5047459, 5474428, 1737756,
974 15967514, 13351758, 6691285, 8034329, 2856544, 14394753, 11310160, 12149558,
975 7487528, 7542781, 15668898, 12525138, 12790975, 3707933, 9106617, 1965401,
976 16219109, 12801644, 2443203, 4909502, 8762329, 3120803, 6360315, 9309720,
977 15164599, 10844842, 4456529, 6667610, 14924259, 884312, 6234963, 3326042,
978 15973422, 13919464, 5272099, 6414643, 3909029, 2764324, 5237926, 4774955,
979 10445906, 4955302, 5203726, 10798229, 11443419, 2303395, 333836, 9646934,
980 3464726, 4159182, 568492, 995747, 10318756, 13299332, 4836017, 8237783,
981 3878992, 2581665, 11394667, 5672745, 14412947, 3159169, 9094251, 16467278,
982 8671392, 15230076, 4843545, 7009238, 15504095, 1494895, 9627886, 14485051,
983 8304291, 252817, 12421642, 16085736, 4774072, 2456177, 4160695, 15409741,
984 4902868, 5793091, 13162925, 16039714, 782255, 11347835, 14884586, 366972,
985 16308990, 11913488, 13390465, 2958444, 10340278, 1177858, 1319431, 10426302,
986 2868597, 126119, 5784857, 5245324, 10903900, 16436004, 3389013, 1742384,
987 14674502, 10279218, 8536112, 10364279, 6877778, 14051163, 1025130, 6072469,
988 1988305, 8354440, 8216060, 16342977, 13112639, 3976679, 5913576, 8816697,
989 6879995, 14043764, 3339515, 9364420, 15808858, 12261651, 2141560, 5636398,
990 10345425, 10414756, 781725, 6155650, 4746914, 5078683, 7469001, 6799140,
991 10156444, 9667150, 10116470, 4133858, 2121972, 1124204, 1003577, 1611214,
992 14304602, 16221850, 13878465, 13577744, 3629235, 8772583, 10881308, 2410386,
993 7300044, 5378855, 9301235, 12755149, 4977682, 8083074, 10327581, 6395087,
994 9155434, 15501696, 7514362, 14520507, 15808945, 3244584, 4741962, 9658130,
995 14336147, 8654727, 7969093, 15759799, 14029445, 5038459, 9894848, 8659300,
996 13699287, 8834306, 10712885, 14753895, 10410465, 3373251, 309501, 9561475,
997 5526688, 14647426, 14209836, 5339224, 207299, 14069911, 8722990, 2290950,
998 3258216, 12505185, 6007317, 9218111, 14661019, 10537428, 11731949, 9027003,
999 6641507, 9490160, 200241, 9720425, 16277895, 10816638, 1554761, 10431375,
1000 7467528, 6790302, 3429078, 14633753, 14428997, 11463204, 3576212, 2003426,
1001 6123687, 820520, 9992513, 15784513, 5778891, 6428165, 8388607
1005 * The hardware uses an LFSR counting sequence to determine when to capture
1006 * the SPU PCs. An LFSR sequence is like a puesdo random number sequence
1007 * where each number occurs once in the sequence but the sequence is not in
1008 * numerical order. The SPU PC capture is done when the LFSR sequence reaches
1009 * the last value in the sequence. Hence the user specified value N
1010 * corresponds to the LFSR number that is N from the end of the sequence.
1012 * To avoid the time to compute the LFSR, a lookup table is used. The 24 bit
1013 * LFSR sequence is broken into four ranges. The spacing of the precomputed
1014 * values is adjusted in each range so the error between the user specifed
1015 * number (N) of events between samples and the actual number of events based
1016 * on the precomputed value will be les then about 6.2%. Note, if the user
1017 * specifies N < 2^16, the LFSR value that is 2^16 from the end will be used.
1018 * This is to prevent the loss of samples because the trace buffer is full.
1020 * User specified N Step between Index in
1021 * precomputed values precomputed
1023 * 0 to 2^16-1 ---- 0
1024 * 2^16 to 2^16+2^19-1 2^12 1 to 128
1025 * 2^16+2^19 to 2^16+2^19+2^22-1 2^15 129 to 256
1026 * 2^16+2^19+2^22 to 2^24-1 2^18 257 to 302
1029 * For example, the LFSR values in the second range are computed for 2^16,
1030 * 2^16+2^12, ... , 2^19-2^16, 2^19 and stored in the table at indicies
1031 * 1, 2,..., 127, 128.
1033 * The 24 bit LFSR value for the nth number in the sequence can be
1034 * calculated using the following code:
1037 * int calculate_lfsr(int n)
1040 * unsigned int newlfsr0;
1041 * unsigned int lfsr = 0xFFFFFF;
1042 * unsigned int howmany = n;
1044 * for (i = 2; i < howmany + 2; i++) {
1045 * newlfsr0 = (((lfsr >> (size - 1 - 0)) & 1) ^
1046 * ((lfsr >> (size - 1 - 1)) & 1) ^
1047 * (((lfsr >> (size - 1 - 6)) & 1) ^
1048 * ((lfsr >> (size - 1 - 23)) & 1)));
1051 * lfsr = lfsr | (newlfsr0 << (size - 1));
1057 #define V2_16 (0x1 << 16)
1058 #define V2_19 (0x1 << 19)
1059 #define V2_22 (0x1 << 22)
1061 static int calculate_lfsr(int n)
1064 * The ranges and steps are in powers of 2 so the calculations
1065 * can be done using shifts rather then divide.
1071 else if (((n - V2_16) >> 19) == 0)
1072 index = ((n - V2_16) >> 12) + 1;
1073 else if (((n - V2_16 - V2_19) >> 22) == 0)
1074 index = ((n - V2_16 - V2_19) >> 15 ) + 1 + 128;
1075 else if (((n - V2_16 - V2_19 - V2_22) >> 24) == 0)
1076 index = ((n - V2_16 - V2_19 - V2_22) >> 18 ) + 1 + 256;
1080 /* make sure index is valid */
1081 if ((index > ENTRIES) || (index < 0))
1084 return initial_lfsr[index];
1087 static int pm_rtas_activate_spu_profiling(u32 node)
1090 struct pm_signal pm_signal_local[NUM_SPUS_PER_NODE];
1093 * Set up the rtas call to configure the debug bus to
1094 * route the SPU PCs. Setup the pm_signal for each SPU
1096 for (i = 0; i < ARRAY_SIZE(pm_signal_local); i++) {
1097 pm_signal_local[i].cpu = node;
1098 pm_signal_local[i].signal_group = 41;
1099 /* spu i on word (i/2) */
1100 pm_signal_local[i].bus_word = 1 << i / 2;
1102 pm_signal_local[i].sub_unit = i;
1103 pm_signal_local[i].bit = 63;
1106 ret = rtas_ibm_cbe_perftools(SUBFUNC_ACTIVATE,
1107 PASSTHRU_ENABLE, pm_signal_local,
1108 (ARRAY_SIZE(pm_signal_local)
1109 * sizeof(struct pm_signal)));
1111 if (unlikely(ret)) {
1112 printk(KERN_WARNING "%s: rtas returned: %d\n",
1120 #ifdef CONFIG_CPU_FREQ
1122 oprof_cpufreq_notify(struct notifier_block *nb, unsigned long val, void *data)
1125 struct cpufreq_freqs *frq = data;
1126 if ((val == CPUFREQ_PRECHANGE && frq->old < frq->new) ||
1127 (val == CPUFREQ_POSTCHANGE && frq->old > frq->new) ||
1128 (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE))
1129 set_spu_profiling_frequency(frq->new, spu_cycle_reset);
1133 static struct notifier_block cpu_freq_notifier_block = {
1134 .notifier_call = oprof_cpufreq_notify
1139 * Note the generic OProfile stop calls do not support returning
1140 * an error on stop. Hence, will not return an error if the FW
1141 * calls fail on stop. Failure to reset the debug bus is not an issue.
1142 * Failure to disable the SPU profiling is not an issue. The FW calls
1143 * to enable the performance counters and debug bus will work even if
1144 * the hardware was not cleanly reset.
1146 static void cell_global_stop_spu_cycles(void)
1148 int subfunc, rtn_value;
1149 unsigned int lfsr_value;
1152 oprofile_running = 0;
1155 #ifdef CONFIG_CPU_FREQ
1156 cpufreq_unregister_notifier(&cpu_freq_notifier_block,
1157 CPUFREQ_TRANSITION_NOTIFIER);
1160 for_each_online_cpu(cpu) {
1161 if (cbe_get_hw_thread_id(cpu))
1165 * 2 - activate SPU tracing,
1168 lfsr_value = 0x8f100000;
1170 rtn_value = rtas_call(spu_rtas_token, 3, 1, NULL,
1171 subfunc, cbe_cpu_to_node(cpu),
1174 if (unlikely(rtn_value != 0)) {
1176 "%s: rtas call ibm,cbe-spu-perftools " \
1177 "failed, return = %d\n",
1178 __func__, rtn_value);
1181 /* Deactivate the signals */
1182 pm_rtas_reset_signals(cbe_cpu_to_node(cpu));
1185 stop_spu_profiling_cycles();
1188 static void cell_global_stop_spu_events(void)
1191 oprofile_running = 0;
1193 stop_spu_profiling_events();
1196 for_each_online_cpu(cpu) {
1197 if (cbe_get_hw_thread_id(cpu))
1200 cbe_sync_irq(cbe_cpu_to_node(cpu));
1201 /* Stop the counters */
1202 cbe_disable_pm(cpu);
1203 cbe_write_pm07_control(cpu, 0, 0);
1205 /* Deactivate the signals */
1206 pm_rtas_reset_signals(cbe_cpu_to_node(cpu));
1208 /* Deactivate interrupts */
1209 cbe_disable_pm_interrupts(cpu);
1211 del_timer_sync(&timer_spu_event_swap);
1214 static void cell_global_stop_ppu(void)
1219 * This routine will be called once for the system.
1220 * There is one performance monitor per node, so we
1221 * only need to perform this function once per node.
1223 del_timer_sync(&timer_virt_cntr);
1224 oprofile_running = 0;
1227 for_each_online_cpu(cpu) {
1228 if (cbe_get_hw_thread_id(cpu))
1231 cbe_sync_irq(cbe_cpu_to_node(cpu));
1232 /* Stop the counters */
1233 cbe_disable_pm(cpu);
1235 /* Deactivate the signals */
1236 pm_rtas_reset_signals(cbe_cpu_to_node(cpu));
1238 /* Deactivate interrupts */
1239 cbe_disable_pm_interrupts(cpu);
1243 static void cell_global_stop(void)
1245 if (profiling_mode == PPU_PROFILING)
1246 cell_global_stop_ppu();
1247 else if (profiling_mode == SPU_PROFILING_EVENTS)
1248 cell_global_stop_spu_events();
1250 cell_global_stop_spu_cycles();
1253 static int cell_global_start_spu_cycles(struct op_counter_config *ctr)
1256 unsigned int lfsr_value;
1260 unsigned int cpu_khzfreq = 0;
1262 /* The SPU profiling uses time-based profiling based on
1263 * cpu frequency, so if configured with the CPU_FREQ
1264 * option, we should detect frequency changes and react
1267 #ifdef CONFIG_CPU_FREQ
1268 ret = cpufreq_register_notifier(&cpu_freq_notifier_block,
1269 CPUFREQ_TRANSITION_NOTIFIER);
1271 /* this is not a fatal error */
1272 printk(KERN_ERR "CPU freq change registration failed: %d\n",
1276 cpu_khzfreq = cpufreq_quick_get(smp_processor_id());
1279 set_spu_profiling_frequency(cpu_khzfreq, spu_cycle_reset);
1281 for_each_online_cpu(cpu) {
1282 if (cbe_get_hw_thread_id(cpu))
1286 * Setup SPU cycle-based profiling.
1287 * Set perf_mon_control bit 0 to a zero before
1288 * enabling spu collection hardware.
1290 cbe_write_pm(cpu, pm_control, 0);
1292 if (spu_cycle_reset > MAX_SPU_COUNT)
1293 /* use largest possible value */
1294 lfsr_value = calculate_lfsr(MAX_SPU_COUNT-1);
1296 lfsr_value = calculate_lfsr(spu_cycle_reset);
1298 /* must use a non zero value. Zero disables data collection. */
1299 if (lfsr_value == 0)
1300 lfsr_value = calculate_lfsr(1);
1302 lfsr_value = lfsr_value << 8; /* shift lfsr to correct
1306 /* debug bus setup */
1307 ret = pm_rtas_activate_spu_profiling(cbe_cpu_to_node(cpu));
1309 if (unlikely(ret)) {
1315 subfunc = 2; /* 2 - activate SPU tracing, 3 - deactivate */
1317 /* start profiling */
1318 ret = rtas_call(spu_rtas_token, 3, 1, NULL, subfunc,
1319 cbe_cpu_to_node(cpu), lfsr_value);
1321 if (unlikely(ret != 0)) {
1323 "%s: rtas call ibm,cbe-spu-perftools failed, " \
1324 "return = %d\n", __func__, ret);
1330 rtas_error = start_spu_profiling_cycles(spu_cycle_reset);
1334 oprofile_running = 1;
1338 cell_global_stop_spu_cycles(); /* clean up the PMU/debug bus */
1343 static int cell_global_start_spu_events(struct op_counter_config *ctr)
1346 u32 interrupt_mask = 0;
1351 /* spu event profiling, uses the performance counters to generate
1352 * an interrupt. The hardware is setup to store the SPU program
1353 * counter into the trace array. The occurrence mode is used to
1354 * enable storing data to the trace buffer. The bits are set
1355 * to send/store the SPU address in the trace buffer. The debug
1356 * bus must be setup to route the SPU program counter onto the
1357 * debug bus. The occurrence data in the trace buffer is not used.
1360 /* This routine gets called once for the system.
1361 * There is one performance monitor per node, so we
1362 * only need to perform this function once per node.
1365 for_each_online_cpu(cpu) {
1366 if (cbe_get_hw_thread_id(cpu))
1370 * Setup SPU event-based profiling.
1371 * Set perf_mon_control bit 0 to a zero before
1372 * enabling spu collection hardware.
1374 * Only support one SPU event on one SPU per node.
1376 if (ctr_enabled & 1) {
1377 cbe_write_ctr(cpu, 0, reset_value[0]);
1378 enable_ctr(cpu, 0, pm_regs.pm07_cntrl);
1380 CBE_PM_CTR_OVERFLOW_INTR(0);
1382 /* Disable counter */
1383 cbe_write_pm07_control(cpu, 0, 0);
1386 cbe_get_and_clear_pm_interrupts(cpu);
1387 cbe_enable_pm_interrupts(cpu, hdw_thread, interrupt_mask);
1390 /* clear the trace buffer */
1391 cbe_write_pm(cpu, trace_address, 0);
1394 /* Start the timer to time slice collecting the event profile
1395 * on each of the SPUs. Note, can collect profile on one SPU
1396 * per node at a time.
1398 start_spu_event_swap();
1399 start_spu_profiling_events();
1400 oprofile_running = 1;
1406 static int cell_global_start_ppu(struct op_counter_config *ctr)
1409 u32 interrupt_mask = 0;
1411 /* This routine gets called once for the system.
1412 * There is one performance monitor per node, so we
1413 * only need to perform this function once per node.
1415 for_each_online_cpu(cpu) {
1416 if (cbe_get_hw_thread_id(cpu))
1421 for (i = 0; i < num_counters; ++i) {
1422 if (ctr_enabled & (1 << i)) {
1423 cbe_write_ctr(cpu, i, reset_value[i]);
1424 enable_ctr(cpu, i, pm_regs.pm07_cntrl);
1426 CBE_PM_CTR_OVERFLOW_INTR(i);
1428 /* Disable counter */
1429 cbe_write_pm07_control(cpu, i, 0);
1433 cbe_get_and_clear_pm_interrupts(cpu);
1434 cbe_enable_pm_interrupts(cpu, hdw_thread, interrupt_mask);
1438 virt_cntr_inter_mask = interrupt_mask;
1439 oprofile_running = 1;
1443 * NOTE: start_virt_cntrs will result in cell_virtual_cntr() being
1444 * executed which manipulates the PMU. We start the "virtual counter"
1445 * here so that we do not need to synchronize access to the PMU in
1446 * the above for-loop.
1453 static int cell_global_start(struct op_counter_config *ctr)
1455 if (profiling_mode == SPU_PROFILING_CYCLES)
1456 return cell_global_start_spu_cycles(ctr);
1457 else if (profiling_mode == SPU_PROFILING_EVENTS)
1458 return cell_global_start_spu_events(ctr);
1460 return cell_global_start_ppu(ctr);
1464 /* The SPU interrupt handler
1466 * SPU event profiling works as follows:
1467 * The pm_signal[0] holds the one SPU event to be measured. It is routed on
1468 * the debug bus using word 0 or 1. The value of pm_signal[1] and
1469 * pm_signal[2] contain the necessary events to route the SPU program
1470 * counter for the selected SPU onto the debug bus using words 2 and 3.
1471 * The pm_interval register is setup to write the SPU PC value into the
1472 * trace buffer at the maximum rate possible. The trace buffer is configured
1473 * to store the PCs, wrapping when it is full. The performance counter is
1474 * intialized to the max hardware count minus the number of events, N, between
1475 * samples. Once the N events have occured, a HW counter overflow occurs
1476 * causing the generation of a HW counter interrupt which also stops the
1477 * writing of the SPU PC values to the trace buffer. Hence the last PC
1478 * written to the trace buffer is the SPU PC that we want. Unfortunately,
1479 * we have to read from the beginning of the trace buffer to get to the
1480 * last value written. We just hope the PPU has nothing better to do then
1481 * service this interrupt. The PC for the specific SPU being profiled is
1482 * extracted from the trace buffer processed and stored. The trace buffer
1483 * is cleared, interrupts are cleared, the counter is reset to max - N.
1484 * A kernel timer is used to periodically call the routine spu_evnt_swap()
1485 * to switch to the next physical SPU in the node to profile in round robbin
1486 * order. This way data is collected for all SPUs on the node. It does mean
1487 * that we need to use a relatively small value of N to ensure enough samples
1488 * on each SPU are collected each SPU is being profiled 1/8 of the time.
1489 * It may also be necessary to use a longer sample collection period.
1491 static void cell_handle_interrupt_spu(struct pt_regs *regs,
1492 struct op_counter_config *ctr)
1497 u64 trace_buffer[2];
1498 u64 last_trace_buffer;
1501 unsigned long sample_array_lock_flags;
1503 unsigned long flags;
1505 /* Make sure spu event interrupt handler and spu event swap
1506 * don't access the counters simultaneously.
1508 cpu = smp_processor_id();
1509 spin_lock_irqsave(&cntr_lock, flags);
1512 cbe_disable_pm(cpu);
1514 interrupt_mask = cbe_get_and_clear_pm_interrupts(cpu);
1517 trace_entry = 0xfedcba;
1518 last_trace_buffer = 0xdeadbeaf;
1520 if ((oprofile_running == 1) && (interrupt_mask != 0)) {
1521 /* disable writes to trace buff */
1522 cbe_write_pm(cpu, pm_interval, 0);
1524 /* only have one perf cntr being used, cntr 0 */
1525 if ((interrupt_mask & CBE_PM_CTR_OVERFLOW_INTR(0))
1527 /* The SPU PC values will be read
1528 * from the trace buffer, reset counter
1531 cbe_write_ctr(cpu, 0, reset_value[0]);
1533 trace_addr = cbe_read_pm(cpu, trace_address);
1535 while (!(trace_addr & CBE_PM_TRACE_BUF_EMPTY)) {
1536 /* There is data in the trace buffer to process
1537 * Read the buffer until you get to the last
1538 * entry. This is the value we want.
1541 cbe_read_trace_buffer(cpu, trace_buffer);
1542 trace_addr = cbe_read_pm(cpu, trace_address);
1545 /* SPU Address 16 bit count format for 128 bit
1546 * HW trace buffer is used for the SPU PC storage
1548 * SPU Addr 0 bits 16:31
1549 * SPU Addr 1 bits 32:47
1550 * unused bits 48:127
1552 * HDR: bit4 = 1 SPU Address 0 valid
1553 * HDR: bit5 = 1 SPU Address 1 valid
1554 * - unfortunately, the valid bits don't seem to work
1556 * Note trace_buffer[0] holds bits 0:63 of the HW
1557 * trace buffer, trace_buffer[1] holds bits 64:127
1560 trace_entry = trace_buffer[0]
1561 & 0x00000000FFFF0000;
1563 /* only top 16 of the 18 bit SPU PC address
1564 * is stored in trace buffer, hence shift right
1566 sample = trace_entry >> 14;
1567 last_trace_buffer = trace_buffer[0];
1569 spu_num = spu_evnt_phys_spu_indx
1570 + (cbe_cpu_to_node(cpu) * NUM_SPUS_PER_NODE);
1572 /* make sure only one process at a time is calling
1575 spin_lock_irqsave(&oprof_spu_smpl_arry_lck,
1576 sample_array_lock_flags);
1577 spu_sync_buffer(spu_num, &sample, 1);
1578 spin_unlock_irqrestore(&oprof_spu_smpl_arry_lck,
1579 sample_array_lock_flags);
1581 smp_wmb(); /* insure spu event buffer updates are written
1582 * don't want events intermingled... */
1584 /* The counters were frozen by the interrupt.
1585 * Reenable the interrupt and restart the counters.
1587 cbe_write_pm(cpu, pm_interval, NUM_INTERVAL_CYC);
1588 cbe_enable_pm_interrupts(cpu, hdw_thread,
1589 virt_cntr_inter_mask);
1591 /* clear the trace buffer, re-enable writes to trace buff */
1592 cbe_write_pm(cpu, trace_address, 0);
1593 cbe_write_pm(cpu, pm_interval, NUM_INTERVAL_CYC);
1595 /* The writes to the various performance counters only writes
1596 * to a latch. The new values (interrupt setting bits, reset
1597 * counter value etc.) are not copied to the actual registers
1598 * until the performance monitor is enabled. In order to get
1599 * this to work as desired, the permormance monitor needs to
1600 * be disabled while writing to the latches. This is a
1603 write_pm_cntrl(cpu);
1606 spin_unlock_irqrestore(&cntr_lock, flags);
1609 static void cell_handle_interrupt_ppu(struct pt_regs *regs,
1610 struct op_counter_config *ctr)
1615 unsigned long flags = 0;
1619 cpu = smp_processor_id();
1622 * Need to make sure the interrupt handler and the virt counter
1623 * routine are not running at the same time. See the
1624 * cell_virtual_cntr() routine for additional comments.
1626 spin_lock_irqsave(&cntr_lock, flags);
1629 * Need to disable and reenable the performance counters
1630 * to get the desired behavior from the hardware. This
1631 * is hardware specific.
1634 cbe_disable_pm(cpu);
1636 interrupt_mask = cbe_get_and_clear_pm_interrupts(cpu);
1639 * If the interrupt mask has been cleared, then the virt cntr
1640 * has cleared the interrupt. When the thread that generated
1641 * the interrupt is restored, the data count will be restored to
1642 * 0xffffff0 to cause the interrupt to be regenerated.
1645 if ((oprofile_running == 1) && (interrupt_mask != 0)) {
1647 is_kernel = is_kernel_addr(pc);
1649 for (i = 0; i < num_counters; ++i) {
1650 if ((interrupt_mask & CBE_PM_CTR_OVERFLOW_INTR(i))
1651 && ctr[i].enabled) {
1652 oprofile_add_ext_sample(pc, regs, i, is_kernel);
1653 cbe_write_ctr(cpu, i, reset_value[i]);
1658 * The counters were frozen by the interrupt.
1659 * Reenable the interrupt and restart the counters.
1660 * If there was a race between the interrupt handler and
1661 * the virtual counter routine. The virutal counter
1662 * routine may have cleared the interrupts. Hence must
1663 * use the virt_cntr_inter_mask to re-enable the interrupts.
1665 cbe_enable_pm_interrupts(cpu, hdw_thread,
1666 virt_cntr_inter_mask);
1669 * The writes to the various performance counters only writes
1670 * to a latch. The new values (interrupt setting bits, reset
1671 * counter value etc.) are not copied to the actual registers
1672 * until the performance monitor is enabled. In order to get
1673 * this to work as desired, the permormance monitor needs to
1674 * be disabled while writing to the latches. This is a
1679 spin_unlock_irqrestore(&cntr_lock, flags);
1682 static void cell_handle_interrupt(struct pt_regs *regs,
1683 struct op_counter_config *ctr)
1685 if (profiling_mode == PPU_PROFILING)
1686 cell_handle_interrupt_ppu(regs, ctr);
1688 cell_handle_interrupt_spu(regs, ctr);
1692 * This function is called from the generic OProfile
1693 * driver. When profiling PPUs, we need to do the
1694 * generic sync start; otherwise, do spu_sync_start.
1696 static int cell_sync_start(void)
1698 if ((profiling_mode == SPU_PROFILING_CYCLES) ||
1699 (profiling_mode == SPU_PROFILING_EVENTS))
1700 return spu_sync_start();
1702 return DO_GENERIC_SYNC;
1705 static int cell_sync_stop(void)
1707 if ((profiling_mode == SPU_PROFILING_CYCLES) ||
1708 (profiling_mode == SPU_PROFILING_EVENTS))
1709 return spu_sync_stop();
1714 struct op_powerpc_model op_model_cell = {
1715 .reg_setup = cell_reg_setup,
1716 .cpu_setup = cell_cpu_setup,
1717 .global_start = cell_global_start,
1718 .global_stop = cell_global_stop,
1719 .sync_start = cell_sync_start,
1720 .sync_stop = cell_sync_stop,
1721 .handle_interrupt = cell_handle_interrupt,