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   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/sched.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/errno.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/irq.h>
  31 #include <linux/io.h>
  32
  33 #include <asm/system.h>
  34 #include <mach/hardware.h>
  35 #include <mach/dma.h>
  36
  37 #include <mach/tc.h>
  38
  39 #undef DEBUG
  40
  41 #ifndef CONFIG_ARCH_OMAP1
  42 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  43         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  44 };
  45
  46 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  47 #endif
  48
  49 #define OMAP_DMA_ACTIVE                 0x01
  50 #define OMAP_DMA_CCR_EN                 (1 << 7)
  51 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  52
  53 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  54
  55 static int enable_1510_mode;
  56
  57 struct omap_dma_lch {
  58         int next_lch;
  59         int dev_id;
  60         u16 saved_csr;
  61         u16 enabled_irqs;
  62         const char *dev_name;
  63         void (*callback)(int lch, u16 ch_status, void *data);
  64         void *data;
  65
  66 #ifndef CONFIG_ARCH_OMAP1
  67         /* required for Dynamic chaining */
  68         int prev_linked_ch;
  69         int next_linked_ch;
  70         int state;
  71         int chain_id;
  72
  73         int status;
  74 #endif
  75         long flags;
  76 };
  77
  78 struct dma_link_info {
  79         int *linked_dmach_q;
  80         int no_of_lchs_linked;
  81
  82         int q_count;
  83         int q_tail;
  84         int q_head;
  85
  86         int chain_state;
  87         int chain_mode;
  88
  89 };
  90
  91 static struct dma_link_info *dma_linked_lch;
  92
  93 #ifndef CONFIG_ARCH_OMAP1
  94
  95 /* Chain handling macros */
  96 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  97         do {                                                            \
  98                 dma_linked_lch[chain_id].q_head =                       \
  99                 dma_linked_lch[chain_id].q_tail =                       \
 100                 dma_linked_lch[chain_id].q_count = 0;                   \
 101         } while (0)
 102 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 103                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 104                 dma_linked_lch[chain_id].q_count)
 105 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 106         do {                                                            \
 107                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 108                 dma_linked_lch[chain_id].q_count)                       \
 109         } while (0)
 110 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 111                 (0 == dma_linked_lch[chain_id].q_count)
 112 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 113         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 114 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 115         do {                                                            \
 116                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 117                 dma_linked_lch[chain_id].q_count--;                     \
 118         } while (0)
 119
 120 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 121         do {                                                            \
 122                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 123                 dma_linked_lch[chain_id].q_count++; \
 124         } while (0)
 125 #endif
 126
 127 static int dma_lch_count;
 128 static int dma_chan_count;
 129 static int omap_dma_reserve_channels;
 130
 131 static spinlock_t dma_chan_lock;
 132 static struct omap_dma_lch *dma_chan;
 133 static void __iomem *omap_dma_base;
 134
 135 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 136         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 137         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 138         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 139         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 140         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 141 };
 142
 143 static inline void disable_lnk(int lch);
 144 static void omap_disable_channel_irq(int lch);
 145 static inline void omap_enable_channel_irq(int lch);
 146
 147 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 148                                                 __func__);
 149
 150 #define dma_read(reg)                                                   \
 151 ({                                                                      \
 152         u32 __val;                                                      \
 153         if (cpu_class_is_omap1())                                       \
 154                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 155         else                                                            \
 156                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 157         __val;                                                          \
 158 })
 159
 160 #define dma_write(val, reg)                                             \
 161 ({                                                                      \
 162         if (cpu_class_is_omap1())                                       \
 163                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 164         else                                                            \
 165                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 166 })
 167
 168 #ifdef CONFIG_ARCH_OMAP15XX
 169 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 170 int omap_dma_in_1510_mode(void)
 171 {
 172         return enable_1510_mode;
 173 }
 174 #else
 175 #define omap_dma_in_1510_mode()         0
 176 #endif
 177
 178 #ifdef CONFIG_ARCH_OMAP1
 179 static inline int get_gdma_dev(int req)
 180 {
 181         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 182         int shift = ((req - 1) % 5) * 6;
 183
 184         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 185 }
 186
 187 static inline void set_gdma_dev(int req, int dev)
 188 {
 189         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 190         int shift = ((req - 1) % 5) * 6;
 191         u32 l;
 192
 193         l = omap_readl(reg);
 194         l &= ~(0x3f << shift);
 195         l |= (dev - 1) << shift;
 196         omap_writel(l, reg);
 197 }
 198 #else
 199 #define set_gdma_dev(req, dev)  do {} while (0)
 200 #endif
 201
 202 /* Omap1 only */
 203 static void clear_lch_regs(int lch)
 204 {
 205         int i;
 206         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 207
 208         for (i = 0; i < 0x2c; i += 2)
 209                 __raw_writew(0, lch_base + i);
 210 }
 211
 212 void omap_set_dma_priority(int lch, int dst_port, int priority)
 213 {
 214         unsigned long reg;
 215         u32 l;
 216
 217         if (cpu_class_is_omap1()) {
 218                 switch (dst_port) {
 219                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 220                         reg = OMAP_TC_OCPT1_PRIOR;
 221                         break;
 222                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 223                         reg = OMAP_TC_OCPT2_PRIOR;
 224                         break;
 225                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 226                         reg = OMAP_TC_EMIFF_PRIOR;
 227                         break;
 228                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 229                         reg = OMAP_TC_EMIFS_PRIOR;
 230                         break;
 231                 default:
 232                         BUG();
 233                         return;
 234                 }
 235                 l = omap_readl(reg);
 236                 l &= ~(0xf << 8);
 237                 l |= (priority & 0xf) << 8;
 238                 omap_writel(l, reg);
 239         }
 240
 241         if (cpu_class_is_omap2()) {
 242                 u32 ccr;
 243
 244                 ccr = dma_read(CCR(lch));
 245                 if (priority)
 246                         ccr |= (1 << 6);
 247                 else
 248                         ccr &= ~(1 << 6);
 249                 dma_write(ccr, CCR(lch));
 250         }
 251 }
 252 EXPORT_SYMBOL(omap_set_dma_priority);
 253
 254 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 255                                   int frame_count, int sync_mode,
 256                                   int dma_trigger, int src_or_dst_synch)
 257 {
 258         u32 l;
 259
 260         l = dma_read(CSDP(lch));
 261         l &= ~0x03;
 262         l |= data_type;
 263         dma_write(l, CSDP(lch));
 264
 265         if (cpu_class_is_omap1()) {
 266                 u16 ccr;
 267
 268                 ccr = dma_read(CCR(lch));
 269                 ccr &= ~(1 << 5);
 270                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 271                         ccr |= 1 << 5;
 272                 dma_write(ccr, CCR(lch));
 273
 274                 ccr = dma_read(CCR2(lch));
 275                 ccr &= ~(1 << 2);
 276                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 277                         ccr |= 1 << 2;
 278                 dma_write(ccr, CCR2(lch));
 279         }
 280
 281         if (cpu_class_is_omap2() && dma_trigger) {
 282                 u32 val;
 283
 284                 val = dma_read(CCR(lch));
 285
 286                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 287                 val &= ~((3 << 19) | 0x1f);
 288                 val |= (dma_trigger & ~0x1f) << 14;
 289                 val |= dma_trigger & 0x1f;
 290
 291                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 292                         val |= 1 << 5;
 293                 else
 294                         val &= ~(1 << 5);
 295
 296                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 297                         val |= 1 << 18;
 298                 else
 299                         val &= ~(1 << 18);
 300
 301                 if (src_or_dst_synch)
 302                         val |= 1 << 24;         /* source synch */
 303                 else
 304                         val &= ~(1 << 24);      /* dest synch */
 305
 306                 dma_write(val, CCR(lch));
 307         }
 308
 309         dma_write(elem_count, CEN(lch));
 310         dma_write(frame_count, CFN(lch));
 311 }
 312 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 313
 314 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 315 {
 316         BUG_ON(omap_dma_in_1510_mode());
 317
 318         if (cpu_class_is_omap1()) {
 319                 u16 w;
 320
 321                 w = dma_read(CCR2(lch));
 322                 w &= ~0x03;
 323
 324                 switch (mode) {
 325                 case OMAP_DMA_CONSTANT_FILL:
 326                         w |= 0x01;
 327                         break;
 328                 case OMAP_DMA_TRANSPARENT_COPY:
 329                         w |= 0x02;
 330                         break;
 331                 case OMAP_DMA_COLOR_DIS:
 332                         break;
 333                 default:
 334                         BUG();
 335                 }
 336                 dma_write(w, CCR2(lch));
 337
 338                 w = dma_read(LCH_CTRL(lch));
 339                 w &= ~0x0f;
 340                 /* Default is channel type 2D */
 341                 if (mode) {
 342                         dma_write((u16)color, COLOR_L(lch));
 343                         dma_write((u16)(color >> 16), COLOR_U(lch));
 344                         w |= 1;         /* Channel type G */
 345                 }
 346                 dma_write(w, LCH_CTRL(lch));
 347         }
 348
 349         if (cpu_class_is_omap2()) {
 350                 u32 val;
 351
 352                 val = dma_read(CCR(lch));
 353                 val &= ~((1 << 17) | (1 << 16));
 354
 355                 switch (mode) {
 356                 case OMAP_DMA_CONSTANT_FILL:
 357                         val |= 1 << 16;
 358                         break;
 359                 case OMAP_DMA_TRANSPARENT_COPY:
 360                         val |= 1 << 17;
 361                         break;
 362                 case OMAP_DMA_COLOR_DIS:
 363                         break;
 364                 default:
 365                         BUG();
 366                 }
 367                 dma_write(val, CCR(lch));
 368
 369                 color &= 0xffffff;
 370                 dma_write(color, COLOR(lch));
 371         }
 372 }
 373 EXPORT_SYMBOL(omap_set_dma_color_mode);
 374
 375 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 376 {
 377         if (cpu_class_is_omap2()) {
 378                 u32 csdp;
 379
 380                 csdp = dma_read(CSDP(lch));
 381                 csdp &= ~(0x3 << 16);
 382                 csdp |= (mode << 16);
 383                 dma_write(csdp, CSDP(lch));
 384         }
 385 }
 386 EXPORT_SYMBOL(omap_set_dma_write_mode);
 387
 388 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 389 {
 390         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 391                 u32 l;
 392
 393                 l = dma_read(LCH_CTRL(lch));
 394                 l &= ~0x7;
 395                 l |= mode;
 396                 dma_write(l, LCH_CTRL(lch));
 397         }
 398 }
 399 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 400
 401 /* Note that src_port is only for omap1 */
 402 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 403                              unsigned long src_start,
 404                              int src_ei, int src_fi)
 405 {
 406         u32 l;
 407
 408         if (cpu_class_is_omap1()) {
 409                 u16 w;
 410
 411                 w = dma_read(CSDP(lch));
 412                 w &= ~(0x1f << 2);
 413                 w |= src_port << 2;
 414                 dma_write(w, CSDP(lch));
 415         }
 416
 417         l = dma_read(CCR(lch));
 418         l &= ~(0x03 << 12);
 419         l |= src_amode << 12;
 420         dma_write(l, CCR(lch));
 421
 422         if (cpu_class_is_omap1()) {
 423                 dma_write(src_start >> 16, CSSA_U(lch));
 424                 dma_write((u16)src_start, CSSA_L(lch));
 425         }
 426
 427         if (cpu_class_is_omap2())
 428                 dma_write(src_start, CSSA(lch));
 429
 430         dma_write(src_ei, CSEI(lch));
 431         dma_write(src_fi, CSFI(lch));
 432 }
 433 EXPORT_SYMBOL(omap_set_dma_src_params);
 434
 435 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 436 {
 437         omap_set_dma_transfer_params(lch, params->data_type,
 438                                      params->elem_count, params->frame_count,
 439                                      params->sync_mode, params->trigger,
 440                                      params->src_or_dst_synch);
 441         omap_set_dma_src_params(lch, params->src_port,
 442                                 params->src_amode, params->src_start,
 443                                 params->src_ei, params->src_fi);
 444
 445         omap_set_dma_dest_params(lch, params->dst_port,
 446                                  params->dst_amode, params->dst_start,
 447                                  params->dst_ei, params->dst_fi);
 448         if (params->read_prio || params->write_prio)
 449                 omap_dma_set_prio_lch(lch, params->read_prio,
 450                                       params->write_prio);
 451 }
 452 EXPORT_SYMBOL(omap_set_dma_params);
 453
 454 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 455 {
 456         if (cpu_class_is_omap2())
 457                 return;
 458
 459         dma_write(eidx, CSEI(lch));
 460         dma_write(fidx, CSFI(lch));
 461 }
 462 EXPORT_SYMBOL(omap_set_dma_src_index);
 463
 464 void omap_set_dma_src_data_pack(int lch, int enable)
 465 {
 466         u32 l;
 467
 468         l = dma_read(CSDP(lch));
 469         l &= ~(1 << 6);
 470         if (enable)
 471                 l |= (1 << 6);
 472         dma_write(l, CSDP(lch));
 473 }
 474 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 475
 476 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 477 {
 478         unsigned int burst = 0;
 479         u32 l;
 480
 481         l = dma_read(CSDP(lch));
 482         l &= ~(0x03 << 7);
 483
 484         switch (burst_mode) {
 485         case OMAP_DMA_DATA_BURST_DIS:
 486                 break;
 487         case OMAP_DMA_DATA_BURST_4:
 488                 if (cpu_class_is_omap2())
 489                         burst = 0x1;
 490                 else
 491                         burst = 0x2;
 492                 break;
 493         case OMAP_DMA_DATA_BURST_8:
 494                 if (cpu_class_is_omap2()) {
 495                         burst = 0x2;
 496                         break;
 497                 }
 498                 /* not supported by current hardware on OMAP1
 499                  * w |= (0x03 << 7);
 500                  * fall through
 501                  */
 502         case OMAP_DMA_DATA_BURST_16:
 503                 if (cpu_class_is_omap2()) {
 504                         burst = 0x3;
 505                         break;
 506                 }
 507                 /* OMAP1 don't support burst 16
 508                  * fall through
 509                  */
 510         default:
 511                 BUG();
 512         }
 513
 514         l |= (burst << 7);
 515         dma_write(l, CSDP(lch));
 516 }
 517 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 518
 519 /* Note that dest_port is only for OMAP1 */
 520 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 521                               unsigned long dest_start,
 522                               int dst_ei, int dst_fi)
 523 {
 524         u32 l;
 525
 526         if (cpu_class_is_omap1()) {
 527                 l = dma_read(CSDP(lch));
 528                 l &= ~(0x1f << 9);
 529                 l |= dest_port << 9;
 530                 dma_write(l, CSDP(lch));
 531         }
 532
 533         l = dma_read(CCR(lch));
 534         l &= ~(0x03 << 14);
 535         l |= dest_amode << 14;
 536         dma_write(l, CCR(lch));
 537
 538         if (cpu_class_is_omap1()) {
 539                 dma_write(dest_start >> 16, CDSA_U(lch));
 540                 dma_write(dest_start, CDSA_L(lch));
 541         }
 542
 543         if (cpu_class_is_omap2())
 544                 dma_write(dest_start, CDSA(lch));
 545
 546         dma_write(dst_ei, CDEI(lch));
 547         dma_write(dst_fi, CDFI(lch));
 548 }
 549 EXPORT_SYMBOL(omap_set_dma_dest_params);
 550
 551 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 552 {
 553         if (cpu_class_is_omap2())
 554                 return;
 555
 556         dma_write(eidx, CDEI(lch));
 557         dma_write(fidx, CDFI(lch));
 558 }
 559 EXPORT_SYMBOL(omap_set_dma_dest_index);
 560
 561 void omap_set_dma_dest_data_pack(int lch, int enable)
 562 {
 563         u32 l;
 564
 565         l = dma_read(CSDP(lch));
 566         l &= ~(1 << 13);
 567         if (enable)
 568                 l |= 1 << 13;
 569         dma_write(l, CSDP(lch));
 570 }
 571 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 572
 573 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 574 {
 575         unsigned int burst = 0;
 576         u32 l;
 577
 578         l = dma_read(CSDP(lch));
 579         l &= ~(0x03 << 14);
 580
 581         switch (burst_mode) {
 582         case OMAP_DMA_DATA_BURST_DIS:
 583                 break;
 584         case OMAP_DMA_DATA_BURST_4:
 585                 if (cpu_class_is_omap2())
 586                         burst = 0x1;
 587                 else
 588                         burst = 0x2;
 589                 break;
 590         case OMAP_DMA_DATA_BURST_8:
 591                 if (cpu_class_is_omap2())
 592                         burst = 0x2;
 593                 else
 594                         burst = 0x3;
 595                 break;
 596         case OMAP_DMA_DATA_BURST_16:
 597                 if (cpu_class_is_omap2()) {
 598                         burst = 0x3;
 599                         break;
 600                 }
 601                 /* OMAP1 don't support burst 16
 602                  * fall through
 603                  */
 604         default:
 605                 printk(KERN_ERR "Invalid DMA burst mode\n");
 606                 BUG();
 607                 return;
 608         }
 609         l |= (burst << 14);
 610         dma_write(l, CSDP(lch));
 611 }
 612 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 613
 614 static inline void omap_enable_channel_irq(int lch)
 615 {
 616         u32 status;
 617
 618         /* Clear CSR */
 619         if (cpu_class_is_omap1())
 620                 status = dma_read(CSR(lch));
 621         else if (cpu_class_is_omap2())
 622                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 623
 624         /* Enable some nice interrupts. */
 625         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 626 }
 627
 628 static void omap_disable_channel_irq(int lch)
 629 {
 630         if (cpu_class_is_omap2())
 631                 dma_write(0, CICR(lch));
 632 }
 633
 634 void omap_enable_dma_irq(int lch, u16 bits)
 635 {
 636         dma_chan[lch].enabled_irqs |= bits;
 637 }
 638 EXPORT_SYMBOL(omap_enable_dma_irq);
 639
 640 void omap_disable_dma_irq(int lch, u16 bits)
 641 {
 642         dma_chan[lch].enabled_irqs &= ~bits;
 643 }
 644 EXPORT_SYMBOL(omap_disable_dma_irq);
 645
 646 static inline void enable_lnk(int lch)
 647 {
 648         u32 l;
 649
 650         l = dma_read(CLNK_CTRL(lch));
 651
 652         if (cpu_class_is_omap1())
 653                 l &= ~(1 << 14);
 654
 655         /* Set the ENABLE_LNK bits */
 656         if (dma_chan[lch].next_lch != -1)
 657                 l = dma_chan[lch].next_lch | (1 << 15);
 658
 659 #ifndef CONFIG_ARCH_OMAP1
 660         if (cpu_class_is_omap2())
 661                 if (dma_chan[lch].next_linked_ch != -1)
 662                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 663 #endif
 664
 665         dma_write(l, CLNK_CTRL(lch));
 666 }
 667
 668 static inline void disable_lnk(int lch)
 669 {
 670         u32 l;
 671
 672         l = dma_read(CLNK_CTRL(lch));
 673
 674         /* Disable interrupts */
 675         if (cpu_class_is_omap1()) {
 676                 dma_write(0, CICR(lch));
 677                 /* Set the STOP_LNK bit */
 678                 l |= 1 << 14;
 679         }
 680
 681         if (cpu_class_is_omap2()) {
 682                 omap_disable_channel_irq(lch);
 683                 /* Clear the ENABLE_LNK bit */
 684                 l &= ~(1 << 15);
 685         }
 686
 687         dma_write(l, CLNK_CTRL(lch));
 688         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 689 }
 690
 691 static inline void omap2_enable_irq_lch(int lch)
 692 {
 693         u32 val;
 694
 695         if (!cpu_class_is_omap2())
 696                 return;
 697
 698         val = dma_read(IRQENABLE_L0);
 699         val |= 1 << lch;
 700         dma_write(val, IRQENABLE_L0);
 701 }
 702
 703 int omap_request_dma(int dev_id, const char *dev_name,
 704                      void (*callback)(int lch, u16 ch_status, void *data),
 705                      void *data, int *dma_ch_out)
 706 {
 707         int ch, free_ch = -1;
 708         unsigned long flags;
 709         struct omap_dma_lch *chan;
 710
 711         spin_lock_irqsave(&dma_chan_lock, flags);
 712         for (ch = 0; ch < dma_chan_count; ch++) {
 713                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 714                         free_ch = ch;
 715                         if (dev_id == 0)
 716                                 break;
 717                 }
 718         }
 719         if (free_ch == -1) {
 720                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 721                 return -EBUSY;
 722         }
 723         chan = dma_chan + free_ch;
 724         chan->dev_id = dev_id;
 725
 726         if (cpu_class_is_omap1())
 727                 clear_lch_regs(free_ch);
 728
 729         if (cpu_class_is_omap2())
 730                 omap_clear_dma(free_ch);
 731
 732         spin_unlock_irqrestore(&dma_chan_lock, flags);
 733
 734         chan->dev_name = dev_name;
 735         chan->callback = callback;
 736         chan->data = data;
 737         chan->flags = 0;
 738
 739 #ifndef CONFIG_ARCH_OMAP1
 740         if (cpu_class_is_omap2()) {
 741                 chan->chain_id = -1;
 742                 chan->next_linked_ch = -1;
 743         }
 744 #endif
 745
 746         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 747
 748         if (cpu_class_is_omap1())
 749                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 750         else if (cpu_class_is_omap2())
 751                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 752                         OMAP2_DMA_TRANS_ERR_IRQ;
 753
 754         if (cpu_is_omap16xx()) {
 755                 /* If the sync device is set, configure it dynamically. */
 756                 if (dev_id != 0) {
 757                         set_gdma_dev(free_ch + 1, dev_id);
 758                         dev_id = free_ch + 1;
 759                 }
 760                 /*
 761                  * Disable the 1510 compatibility mode and set the sync device
 762                  * id.
 763                  */
 764                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 765         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 766                 dma_write(dev_id, CCR(free_ch));
 767         }
 768
 769         if (cpu_class_is_omap2()) {
 770                 omap2_enable_irq_lch(free_ch);
 771                 omap_enable_channel_irq(free_ch);
 772                 /* Clear the CSR register and IRQ status register */
 773                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 774                 dma_write(1 << free_ch, IRQSTATUS_L0);
 775         }
 776
 777         *dma_ch_out = free_ch;
 778
 779         return 0;
 780 }
 781 EXPORT_SYMBOL(omap_request_dma);
 782
 783 void omap_free_dma(int lch)
 784 {
 785         unsigned long flags;
 786
 787         if (dma_chan[lch].dev_id == -1) {
 788                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 789                        lch);
 790                 return;
 791         }
 792
 793         if (cpu_class_is_omap1()) {
 794                 /* Disable all DMA interrupts for the channel. */
 795                 dma_write(0, CICR(lch));
 796                 /* Make sure the DMA transfer is stopped. */
 797                 dma_write(0, CCR(lch));
 798         }
 799
 800         if (cpu_class_is_omap2()) {
 801                 u32 val;
 802                 /* Disable interrupts */
 803                 val = dma_read(IRQENABLE_L0);
 804                 val &= ~(1 << lch);
 805                 dma_write(val, IRQENABLE_L0);
 806
 807                 /* Clear the CSR register and IRQ status register */
 808                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 809                 dma_write(1 << lch, IRQSTATUS_L0);
 810
 811                 /* Disable all DMA interrupts for the channel. */
 812                 dma_write(0, CICR(lch));
 813
 814                 /* Make sure the DMA transfer is stopped. */
 815                 dma_write(0, CCR(lch));
 816                 omap_clear_dma(lch);
 817         }
 818
 819         spin_lock_irqsave(&dma_chan_lock, flags);
 820         dma_chan[lch].dev_id = -1;
 821         dma_chan[lch].next_lch = -1;
 822         dma_chan[lch].callback = NULL;
 823         spin_unlock_irqrestore(&dma_chan_lock, flags);
 824 }
 825 EXPORT_SYMBOL(omap_free_dma);
 826
 827 /**
 828  * @brief omap_dma_set_global_params : Set global priority settings for dma
 829  *
 830  * @param arb_rate
 831  * @param max_fifo_depth
 832  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 833  *                                                 DMA_THREAD_RESERVE_ONET
 834  *                                                 DMA_THREAD_RESERVE_TWOT
 835  *                                                 DMA_THREAD_RESERVE_THREET
 836  */
 837 void
 838 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 839 {
 840         u32 reg;
 841
 842         if (!cpu_class_is_omap2()) {
 843                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 844                 return;
 845         }
 846
 847         if (max_fifo_depth == 0)
 848                 max_fifo_depth = 1;
 849         if (arb_rate == 0)
 850                 arb_rate = 1;
 851
 852         reg = 0xff & max_fifo_depth;
 853         reg |= (0x3 & tparams) << 12;
 854         reg |= (arb_rate & 0xff) << 16;
 855
 856         dma_write(reg, GCR);
 857 }
 858 EXPORT_SYMBOL(omap_dma_set_global_params);
 859
 860 /**
 861  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 862  *
 863  * @param lch
 864  * @param read_prio - Read priority
 865  * @param write_prio - Write priority
 866  * Both of the above can be set with one of the following values :
 867  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 868  */
 869 int
 870 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 871                       unsigned char write_prio)
 872 {
 873         u32 l;
 874
 875         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 876                 printk(KERN_ERR "Invalid channel id\n");
 877                 return -EINVAL;
 878         }
 879         l = dma_read(CCR(lch));
 880         l &= ~((1 << 6) | (1 << 26));
 881         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
 882                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 883         else
 884                 l |= ((read_prio & 0x1) << 6);
 885
 886         dma_write(l, CCR(lch));
 887
 888         return 0;
 889 }
 890 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 891
 892 /*
 893  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 894  * through omap_start_dma(). Any buffers in flight are discarded.
 895  */
 896 void omap_clear_dma(int lch)
 897 {
 898         unsigned long flags;
 899
 900         local_irq_save(flags);
 901
 902         if (cpu_class_is_omap1()) {
 903                 u32 l;
 904
 905                 l = dma_read(CCR(lch));
 906                 l &= ~OMAP_DMA_CCR_EN;
 907                 dma_write(l, CCR(lch));
 908
 909                 /* Clear pending interrupts */
 910                 l = dma_read(CSR(lch));
 911         }
 912
 913         if (cpu_class_is_omap2()) {
 914                 int i;
 915                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 916                 for (i = 0; i < 0x44; i += 4)
 917                         __raw_writel(0, lch_base + i);
 918         }
 919
 920         local_irq_restore(flags);
 921 }
 922 EXPORT_SYMBOL(omap_clear_dma);
 923
 924 void omap_start_dma(int lch)
 925 {
 926         u32 l;
 927
 928         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 929                 int next_lch, cur_lch;
 930                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 931
 932                 dma_chan_link_map[lch] = 1;
 933                 /* Set the link register of the first channel */
 934                 enable_lnk(lch);
 935
 936                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 937                 cur_lch = dma_chan[lch].next_lch;
 938                 do {
 939                         next_lch = dma_chan[cur_lch].next_lch;
 940
 941                         /* The loop case: we've been here already */
 942                         if (dma_chan_link_map[cur_lch])
 943                                 break;
 944                         /* Mark the current channel */
 945                         dma_chan_link_map[cur_lch] = 1;
 946
 947                         enable_lnk(cur_lch);
 948                         omap_enable_channel_irq(cur_lch);
 949
 950                         cur_lch = next_lch;
 951                 } while (next_lch != -1);
 952         } else if (cpu_is_omap242x() ||
 953                 (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
 954
 955                 /* Errata: Need to write lch even if not using chaining */
 956                 dma_write(lch, CLNK_CTRL(lch));
 957         }
 958
 959         omap_enable_channel_irq(lch);
 960
 961         l = dma_read(CCR(lch));
 962
 963         /*
 964          * Errata: On ES2.0 BUFFERING disable must be set.
 965          * This will always fail on ES1.0
 966          */
 967         if (cpu_is_omap24xx())
 968                 l |= OMAP_DMA_CCR_EN;
 969
 970         l |= OMAP_DMA_CCR_EN;
 971         dma_write(l, CCR(lch));
 972
 973         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 974 }
 975 EXPORT_SYMBOL(omap_start_dma);
 976
 977 void omap_stop_dma(int lch)
 978 {
 979         u32 l;
 980
 981         /* Disable all interrupts on the channel */
 982         if (cpu_class_is_omap1())
 983                 dma_write(0, CICR(lch));
 984
 985         l = dma_read(CCR(lch));
 986         l &= ~OMAP_DMA_CCR_EN;
 987         dma_write(l, CCR(lch));
 988
 989         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 990                 int next_lch, cur_lch = lch;
 991                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 992
 993                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 994                 do {
 995                         /* The loop case: we've been here already */
 996                         if (dma_chan_link_map[cur_lch])
 997                                 break;
 998                         /* Mark the current channel */
 999                         dma_chan_link_map[cur_lch] = 1;
1000
1001                         disable_lnk(cur_lch);
1002
1003                         next_lch = dma_chan[cur_lch].next_lch;
1004                         cur_lch = next_lch;
1005                 } while (next_lch != -1);
1006         }
1007
1008         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1009 }
1010 EXPORT_SYMBOL(omap_stop_dma);
1011
1012 /*
1013  * Allows changing the DMA callback function or data. This may be needed if
1014  * the driver shares a single DMA channel for multiple dma triggers.
1015  */
1016 int omap_set_dma_callback(int lch,
1017                           void (*callback)(int lch, u16 ch_status, void *data),
1018                           void *data)
1019 {
1020         unsigned long flags;
1021
1022         if (lch < 0)
1023                 return -ENODEV;
1024
1025         spin_lock_irqsave(&dma_chan_lock, flags);
1026         if (dma_chan[lch].dev_id == -1) {
1027                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1028                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1029                 return -EINVAL;
1030         }
1031         dma_chan[lch].callback = callback;
1032         dma_chan[lch].data = data;
1033         spin_unlock_irqrestore(&dma_chan_lock, flags);
1034
1035         return 0;
1036 }
1037 EXPORT_SYMBOL(omap_set_dma_callback);
1038
1039 /*
1040  * Returns current physical source address for the given DMA channel.
1041  * If the channel is running the caller must disable interrupts prior calling
1042  * this function and process the returned value before re-enabling interrupt to
1043  * prevent races with the interrupt handler. Note that in continuous mode there
1044  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1045  * in incorrect return value.
1046  */
1047 dma_addr_t omap_get_dma_src_pos(int lch)
1048 {
1049         dma_addr_t offset = 0;
1050
1051         if (cpu_is_omap15xx())
1052                 offset = dma_read(CPC(lch));
1053         else
1054                 offset = dma_read(CSAC(lch));
1055
1056         /*
1057          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1058          * read before the DMA controller finished disabling the channel.
1059          */
1060         if (!cpu_is_omap15xx() && offset == 0)
1061                 offset = dma_read(CSAC(lch));
1062
1063         if (cpu_class_is_omap1())
1064                 offset |= (dma_read(CSSA_U(lch)) << 16);
1065
1066         return offset;
1067 }
1068 EXPORT_SYMBOL(omap_get_dma_src_pos);
1069
1070 /*
1071  * Returns current physical destination address for the given DMA channel.
1072  * If the channel is running the caller must disable interrupts prior calling
1073  * this function and process the returned value before re-enabling interrupt to
1074  * prevent races with the interrupt handler. Note that in continuous mode there
1075  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1076  * in incorrect return value.
1077  */
1078 dma_addr_t omap_get_dma_dst_pos(int lch)
1079 {
1080         dma_addr_t offset = 0;
1081
1082         if (cpu_is_omap15xx())
1083                 offset = dma_read(CPC(lch));
1084         else
1085                 offset = dma_read(CDAC(lch));
1086
1087         /*
1088          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1089          * read before the DMA controller finished disabling the channel.
1090          */
1091         if (!cpu_is_omap15xx() && offset == 0)
1092                 offset = dma_read(CDAC(lch));
1093
1094         if (cpu_class_is_omap1())
1095                 offset |= (dma_read(CDSA_U(lch)) << 16);
1096
1097         return offset;
1098 }
1099 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1100
1101 int omap_get_dma_active_status(int lch)
1102 {
1103         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1104 }
1105 EXPORT_SYMBOL(omap_get_dma_active_status);
1106
1107 int omap_dma_running(void)
1108 {
1109         int lch;
1110
1111         /* Check if LCD DMA is running */
1112         if (cpu_is_omap16xx())
1113                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1114                         return 1;
1115
1116         for (lch = 0; lch < dma_chan_count; lch++)
1117                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1118                         return 1;
1119
1120         return 0;
1121 }
1122
1123 /*
1124  * lch_queue DMA will start right after lch_head one is finished.
1125  * For this DMA link to start, you still need to start (see omap_start_dma)
1126  * the first one. That will fire up the entire queue.
1127  */
1128 void omap_dma_link_lch(int lch_head, int lch_queue)
1129 {
1130         if (omap_dma_in_1510_mode()) {
1131                 if (lch_head == lch_queue) {
1132                         dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1133                                                                 CCR(lch_head));
1134                         return;
1135                 }
1136                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1137                 BUG();
1138                 return;
1139         }
1140
1141         if ((dma_chan[lch_head].dev_id == -1) ||
1142             (dma_chan[lch_queue].dev_id == -1)) {
1143                 printk(KERN_ERR "omap_dma: trying to link "
1144                        "non requested channels\n");
1145                 dump_stack();
1146         }
1147
1148         dma_chan[lch_head].next_lch = lch_queue;
1149 }
1150 EXPORT_SYMBOL(omap_dma_link_lch);
1151
1152 /*
1153  * Once the DMA queue is stopped, we can destroy it.
1154  */
1155 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1156 {
1157         if (omap_dma_in_1510_mode()) {
1158                 if (lch_head == lch_queue) {
1159                         dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1160                                                                 CCR(lch_head));
1161                         return;
1162                 }
1163                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1164                 BUG();
1165                 return;
1166         }
1167
1168         if (dma_chan[lch_head].next_lch != lch_queue ||
1169             dma_chan[lch_head].next_lch == -1) {
1170                 printk(KERN_ERR "omap_dma: trying to unlink "
1171                        "non linked channels\n");
1172                 dump_stack();
1173         }
1174
1175         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1176             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1177                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1178                        "before unlinking\n");
1179                 dump_stack();
1180         }
1181
1182         dma_chan[lch_head].next_lch = -1;
1183 }
1184 EXPORT_SYMBOL(omap_dma_unlink_lch);
1185
1186 /*----------------------------------------------------------------------------*/
1187
1188 #ifndef CONFIG_ARCH_OMAP1
1189 /* Create chain of DMA channesls */
1190 static void create_dma_lch_chain(int lch_head, int lch_queue)
1191 {
1192         u32 l;
1193
1194         /* Check if this is the first link in chain */
1195         if (dma_chan[lch_head].next_linked_ch == -1) {
1196                 dma_chan[lch_head].next_linked_ch = lch_queue;
1197                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1198                 dma_chan[lch_queue].next_linked_ch = lch_head;
1199                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1200         }
1201
1202         /* a link exists, link the new channel in circular chain */
1203         else {
1204                 dma_chan[lch_queue].next_linked_ch =
1205                                         dma_chan[lch_head].next_linked_ch;
1206                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1207                 dma_chan[lch_head].next_linked_ch = lch_queue;
1208                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1209                                         lch_queue;
1210         }
1211
1212         l = dma_read(CLNK_CTRL(lch_head));
1213         l &= ~(0x1f);
1214         l |= lch_queue;
1215         dma_write(l, CLNK_CTRL(lch_head));
1216
1217         l = dma_read(CLNK_CTRL(lch_queue));
1218         l &= ~(0x1f);
1219         l |= (dma_chan[lch_queue].next_linked_ch);
1220         dma_write(l, CLNK_CTRL(lch_queue));
1221 }
1222
1223 /**
1224  * @brief omap_request_dma_chain : Request a chain of DMA channels
1225  *
1226  * @param dev_id - Device id using the dma channel
1227  * @param dev_name - Device name
1228  * @param callback - Call back function
1229  * @chain_id -
1230  * @no_of_chans - Number of channels requested
1231  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1232  *                                            OMAP_DMA_DYNAMIC_CHAIN
1233  * @params - Channel parameters
1234  *
1235  * @return - Success : 0
1236  *           Failure: -EINVAL/-ENOMEM
1237  */
1238 int omap_request_dma_chain(int dev_id, const char *dev_name,
1239                            void (*callback) (int lch, u16 ch_status,
1240                                              void *data),
1241                            int *chain_id, int no_of_chans, int chain_mode,
1242                            struct omap_dma_channel_params params)
1243 {
1244         int *channels;
1245         int i, err;
1246
1247         /* Is the chain mode valid ? */
1248         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1249                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1250                 printk(KERN_ERR "Invalid chain mode requested\n");
1251                 return -EINVAL;
1252         }
1253
1254         if (unlikely((no_of_chans < 1
1255                         || no_of_chans > dma_lch_count))) {
1256                 printk(KERN_ERR "Invalid Number of channels requested\n");
1257                 return -EINVAL;
1258         }
1259
1260         /* Allocate a queue to maintain the status of the channels
1261          * in the chain */
1262         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1263         if (channels == NULL) {
1264                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1265                 return -ENOMEM;
1266         }
1267
1268         /* request and reserve DMA channels for the chain */
1269         for (i = 0; i < no_of_chans; i++) {
1270                 err = omap_request_dma(dev_id, dev_name,
1271                                         callback, NULL, &channels[i]);
1272                 if (err < 0) {
1273                         int j;
1274                         for (j = 0; j < i; j++)
1275                                 omap_free_dma(channels[j]);
1276                         kfree(channels);
1277                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1278                         return err;
1279                 }
1280                 dma_chan[channels[i]].prev_linked_ch = -1;
1281                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1282
1283                 /*
1284                  * Allowing client drivers to set common parameters now,
1285                  * so that later only relevant (src_start, dest_start
1286                  * and element count) can be set
1287                  */
1288                 omap_set_dma_params(channels[i], &params);
1289         }
1290
1291         *chain_id = channels[0];
1292         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1293         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1294         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1295         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1296
1297         for (i = 0; i < no_of_chans; i++)
1298                 dma_chan[channels[i]].chain_id = *chain_id;
1299
1300         /* Reset the Queue pointers */
1301         OMAP_DMA_CHAIN_QINIT(*chain_id);
1302
1303         /* Set up the chain */
1304         if (no_of_chans == 1)
1305                 create_dma_lch_chain(channels[0], channels[0]);
1306         else {
1307                 for (i = 0; i < (no_of_chans - 1); i++)
1308                         create_dma_lch_chain(channels[i], channels[i + 1]);
1309         }
1310
1311         return 0;
1312 }
1313 EXPORT_SYMBOL(omap_request_dma_chain);
1314
1315 /**
1316  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1317  * params after setting it. Dont do this while dma is running!!
1318  *
1319  * @param chain_id - Chained logical channel id.
1320  * @param params
1321  *
1322  * @return - Success : 0
1323  *           Failure : -EINVAL
1324  */
1325 int omap_modify_dma_chain_params(int chain_id,
1326                                 struct omap_dma_channel_params params)
1327 {
1328         int *channels;
1329         u32 i;
1330
1331         /* Check for input params */
1332         if (unlikely((chain_id < 0
1333                         || chain_id >= dma_lch_count))) {
1334                 printk(KERN_ERR "Invalid chain id\n");
1335                 return -EINVAL;
1336         }
1337
1338         /* Check if the chain exists */
1339         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1340                 printk(KERN_ERR "Chain doesn't exists\n");
1341                 return -EINVAL;
1342         }
1343         channels = dma_linked_lch[chain_id].linked_dmach_q;
1344
1345         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1346                 /*
1347                  * Allowing client drivers to set common parameters now,
1348                  * so that later only relevant (src_start, dest_start
1349                  * and element count) can be set
1350                  */
1351                 omap_set_dma_params(channels[i], &params);
1352         }
1353
1354         return 0;
1355 }
1356 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1357
1358 /**
1359  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1360  *
1361  * @param chain_id
1362  *
1363  * @return - Success : 0
1364  *           Failure : -EINVAL
1365  */
1366 int omap_free_dma_chain(int chain_id)
1367 {
1368         int *channels;
1369         u32 i;
1370
1371         /* Check for input params */
1372         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1373                 printk(KERN_ERR "Invalid chain id\n");
1374                 return -EINVAL;
1375         }
1376
1377         /* Check if the chain exists */
1378         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1379                 printk(KERN_ERR "Chain doesn't exists\n");
1380                 return -EINVAL;
1381         }
1382
1383         channels = dma_linked_lch[chain_id].linked_dmach_q;
1384         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1385                 dma_chan[channels[i]].next_linked_ch = -1;
1386                 dma_chan[channels[i]].prev_linked_ch = -1;
1387                 dma_chan[channels[i]].chain_id = -1;
1388                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1389                 omap_free_dma(channels[i]);
1390         }
1391
1392         kfree(channels);
1393
1394         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1395         dma_linked_lch[chain_id].chain_mode = -1;
1396         dma_linked_lch[chain_id].chain_state = -1;
1397
1398         return (0);
1399 }
1400 EXPORT_SYMBOL(omap_free_dma_chain);
1401
1402 /**
1403  * @brief omap_dma_chain_status - Check if the chain is in
1404  * active / inactive state.
1405  * @param chain_id
1406  *
1407  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1408  *           Failure : -EINVAL
1409  */
1410 int omap_dma_chain_status(int chain_id)
1411 {
1412         /* Check for input params */
1413         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1414                 printk(KERN_ERR "Invalid chain id\n");
1415                 return -EINVAL;
1416         }
1417
1418         /* Check if the chain exists */
1419         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1420                 printk(KERN_ERR "Chain doesn't exists\n");
1421                 return -EINVAL;
1422         }
1423         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1424                         dma_linked_lch[chain_id].q_count);
1425
1426         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1427                 return OMAP_DMA_CHAIN_INACTIVE;
1428
1429         return OMAP_DMA_CHAIN_ACTIVE;
1430 }
1431 EXPORT_SYMBOL(omap_dma_chain_status);
1432
1433 /**
1434  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1435  * set the params and start the transfer.
1436  *
1437  * @param chain_id
1438  * @param src_start - buffer start address
1439  * @param dest_start - Dest address
1440  * @param elem_count
1441  * @param frame_count
1442  * @param callbk_data - channel callback parameter data.
1443  *
1444  * @return  - Success : 0
1445  *            Failure: -EINVAL/-EBUSY
1446  */
1447 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1448                         int elem_count, int frame_count, void *callbk_data)
1449 {
1450         int *channels;
1451         u32 l, lch;
1452         int start_dma = 0;
1453
1454         /*
1455          * if buffer size is less than 1 then there is
1456          * no use of starting the chain
1457          */
1458         if (elem_count < 1) {
1459                 printk(KERN_ERR "Invalid buffer size\n");
1460                 return -EINVAL;
1461         }
1462
1463         /* Check for input params */
1464         if (unlikely((chain_id < 0
1465                         || chain_id >= dma_lch_count))) {
1466                 printk(KERN_ERR "Invalid chain id\n");
1467                 return -EINVAL;
1468         }
1469
1470         /* Check if the chain exists */
1471         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1472                 printk(KERN_ERR "Chain doesn't exist\n");
1473                 return -EINVAL;
1474         }
1475
1476         /* Check if all the channels in chain are in use */
1477         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1478                 return -EBUSY;
1479
1480         /* Frame count may be negative in case of indexed transfers */
1481         channels = dma_linked_lch[chain_id].linked_dmach_q;
1482
1483         /* Get a free channel */
1484         lch = channels[dma_linked_lch[chain_id].q_tail];
1485
1486         /* Store the callback data */
1487         dma_chan[lch].data = callbk_data;
1488
1489         /* Increment the q_tail */
1490         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1491
1492         /* Set the params to the free channel */
1493         if (src_start != 0)
1494                 dma_write(src_start, CSSA(lch));
1495         if (dest_start != 0)
1496                 dma_write(dest_start, CDSA(lch));
1497
1498         /* Write the buffer size */
1499         dma_write(elem_count, CEN(lch));
1500         dma_write(frame_count, CFN(lch));
1501
1502         /*
1503          * If the chain is dynamically linked,
1504          * then we may have to start the chain if its not active
1505          */
1506         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1507
1508                 /*
1509                  * In Dynamic chain, if the chain is not started,
1510                  * queue the channel
1511                  */
1512                 if (dma_linked_lch[chain_id].chain_state ==
1513                                                 DMA_CHAIN_NOTSTARTED) {
1514                         /* Enable the link in previous channel */
1515                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1516                                                                 DMA_CH_QUEUED)
1517                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1518                         dma_chan[lch].state = DMA_CH_QUEUED;
1519                 }
1520
1521                 /*
1522                  * Chain is already started, make sure its active,
1523                  * if not then start the chain
1524                  */
1525                 else {
1526                         start_dma = 1;
1527
1528                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1529                                                         DMA_CH_STARTED) {
1530                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1531                                 dma_chan[lch].state = DMA_CH_QUEUED;
1532                                 start_dma = 0;
1533                                 if (0 == ((1 << 7) & dma_read(
1534                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1535                                         disable_lnk(dma_chan[lch].
1536                                                     prev_linked_ch);
1537                                         pr_debug("\n prev ch is stopped\n");
1538                                         start_dma = 1;
1539                                 }
1540                         }
1541
1542                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1543                                                         == DMA_CH_QUEUED) {
1544                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1545                                 dma_chan[lch].state = DMA_CH_QUEUED;
1546                                 start_dma = 0;
1547                         }
1548                         omap_enable_channel_irq(lch);
1549
1550                         l = dma_read(CCR(lch));
1551
1552                         if ((0 == (l & (1 << 24))))
1553                                 l &= ~(1 << 25);
1554                         else
1555                                 l |= (1 << 25);
1556                         if (start_dma == 1) {
1557                                 if (0 == (l & (1 << 7))) {
1558                                         l |= (1 << 7);
1559                                         dma_chan[lch].state = DMA_CH_STARTED;
1560                                         pr_debug("starting %d\n", lch);
1561                                         dma_write(l, CCR(lch));
1562                                 } else
1563                                         start_dma = 0;
1564                         } else {
1565                                 if (0 == (l & (1 << 7)))
1566                                         dma_write(l, CCR(lch));
1567                         }
1568                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1569                 }
1570         }
1571
1572         return 0;
1573 }
1574 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1575
1576 /**
1577  * @brief omap_start_dma_chain_transfers - Start the chain
1578  *
1579  * @param chain_id
1580  *
1581  * @return - Success : 0
1582  *           Failure : -EINVAL/-EBUSY
1583  */
1584 int omap_start_dma_chain_transfers(int chain_id)
1585 {
1586         int *channels;
1587         u32 l, i;
1588
1589         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1590                 printk(KERN_ERR "Invalid chain id\n");
1591                 return -EINVAL;
1592         }
1593
1594         channels = dma_linked_lch[chain_id].linked_dmach_q;
1595
1596         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1597                 printk(KERN_ERR "Chain is already started\n");
1598                 return -EBUSY;
1599         }
1600
1601         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1602                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1603                                                                         i++) {
1604                         enable_lnk(channels[i]);
1605                         omap_enable_channel_irq(channels[i]);
1606                 }
1607         } else {
1608                 omap_enable_channel_irq(channels[0]);
1609         }
1610
1611         l = dma_read(CCR(channels[0]));
1612         l |= (1 << 7);
1613         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1614         dma_chan[channels[0]].state = DMA_CH_STARTED;
1615
1616         if ((0 == (l & (1 << 24))))
1617                 l &= ~(1 << 25);
1618         else
1619                 l |= (1 << 25);
1620         dma_write(l, CCR(channels[0]));
1621
1622         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1623
1624         return 0;
1625 }
1626 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1627
1628 /**
1629  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1630  *
1631  * @param chain_id
1632  *
1633  * @return - Success : 0
1634  *           Failure : EINVAL
1635  */
1636 int omap_stop_dma_chain_transfers(int chain_id)
1637 {
1638         int *channels;
1639         u32 l, i;
1640         u32 sys_cf;
1641
1642         /* Check for input params */
1643         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1644                 printk(KERN_ERR "Invalid chain id\n");
1645                 return -EINVAL;
1646         }
1647
1648         /* Check if the chain exists */
1649         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1650                 printk(KERN_ERR "Chain doesn't exists\n");
1651                 return -EINVAL;
1652         }
1653         channels = dma_linked_lch[chain_id].linked_dmach_q;
1654
1655         /*
1656          * DMA Errata:
1657          * Special programming model needed to disable DMA before end of block
1658          */
1659         sys_cf = dma_read(OCP_SYSCONFIG);
1660         l = sys_cf;
1661         /* Middle mode reg set no Standby */
1662         l &= ~((1 << 12)|(1 << 13));
1663         dma_write(l, OCP_SYSCONFIG);
1664
1665         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1666
1667                 /* Stop the Channel transmission */
1668                 l = dma_read(CCR(channels[i]));
1669                 l &= ~(1 << 7);
1670                 dma_write(l, CCR(channels[i]));
1671
1672                 /* Disable the link in all the channels */
1673                 disable_lnk(channels[i]);
1674                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1675
1676         }
1677         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1678
1679         /* Reset the Queue pointers */
1680         OMAP_DMA_CHAIN_QINIT(chain_id);
1681
1682         /* Errata - put in the old value */
1683         dma_write(sys_cf, OCP_SYSCONFIG);
1684
1685         return 0;
1686 }
1687 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1688
1689 /* Get the index of the ongoing DMA in chain */
1690 /**
1691  * @brief omap_get_dma_chain_index - Get the element and frame index
1692  * of the ongoing DMA in chain
1693  *
1694  * @param chain_id
1695  * @param ei - Element index
1696  * @param fi - Frame index
1697  *
1698  * @return - Success : 0
1699  *           Failure : -EINVAL
1700  */
1701 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1702 {
1703         int lch;
1704         int *channels;
1705
1706         /* Check for input params */
1707         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1708                 printk(KERN_ERR "Invalid chain id\n");
1709                 return -EINVAL;
1710         }
1711
1712         /* Check if the chain exists */
1713         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1714                 printk(KERN_ERR "Chain doesn't exists\n");
1715                 return -EINVAL;
1716         }
1717         if ((!ei) || (!fi))
1718                 return -EINVAL;
1719
1720         channels = dma_linked_lch[chain_id].linked_dmach_q;
1721
1722         /* Get the current channel */
1723         lch = channels[dma_linked_lch[chain_id].q_head];
1724
1725         *ei = dma_read(CCEN(lch));
1726         *fi = dma_read(CCFN(lch));
1727
1728         return 0;
1729 }
1730 EXPORT_SYMBOL(omap_get_dma_chain_index);
1731
1732 /**
1733  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1734  * ongoing DMA in chain
1735  *
1736  * @param chain_id
1737  *
1738  * @return - Success : Destination position
1739  *           Failure : -EINVAL
1740  */
1741 int omap_get_dma_chain_dst_pos(int chain_id)
1742 {
1743         int lch;
1744         int *channels;
1745
1746         /* Check for input params */
1747         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1748                 printk(KERN_ERR "Invalid chain id\n");
1749                 return -EINVAL;
1750         }
1751
1752         /* Check if the chain exists */
1753         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1754                 printk(KERN_ERR "Chain doesn't exists\n");
1755                 return -EINVAL;
1756         }
1757
1758         channels = dma_linked_lch[chain_id].linked_dmach_q;
1759
1760         /* Get the current channel */
1761         lch = channels[dma_linked_lch[chain_id].q_head];
1762
1763         return dma_read(CDAC(lch));
1764 }
1765 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1766
1767 /**
1768  * @brief omap_get_dma_chain_src_pos - Get the source position
1769  * of the ongoing DMA in chain
1770  * @param chain_id
1771  *
1772  * @return - Success : Destination position
1773  *           Failure : -EINVAL
1774  */
1775 int omap_get_dma_chain_src_pos(int chain_id)
1776 {
1777         int lch;
1778         int *channels;
1779
1780         /* Check for input params */
1781         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1782                 printk(KERN_ERR "Invalid chain id\n");
1783                 return -EINVAL;
1784         }
1785
1786         /* Check if the chain exists */
1787         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1788                 printk(KERN_ERR "Chain doesn't exists\n");
1789                 return -EINVAL;
1790         }
1791
1792         channels = dma_linked_lch[chain_id].linked_dmach_q;
1793
1794         /* Get the current channel */
1795         lch = channels[dma_linked_lch[chain_id].q_head];
1796
1797         return dma_read(CSAC(lch));
1798 }
1799 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1800 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1801
1802 /*----------------------------------------------------------------------------*/
1803
1804 #ifdef CONFIG_ARCH_OMAP1
1805
1806 static int omap1_dma_handle_ch(int ch)
1807 {
1808         u32 csr;
1809
1810         if (enable_1510_mode && ch >= 6) {
1811                 csr = dma_chan[ch].saved_csr;
1812                 dma_chan[ch].saved_csr = 0;
1813         } else
1814                 csr = dma_read(CSR(ch));
1815         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1816                 dma_chan[ch + 6].saved_csr = csr >> 7;
1817                 csr &= 0x7f;
1818         }
1819         if ((csr & 0x3f) == 0)
1820                 return 0;
1821         if (unlikely(dma_chan[ch].dev_id == -1)) {
1822                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1823                        "%d (CSR %04x)\n", ch, csr);
1824                 return 0;
1825         }
1826         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1827                 printk(KERN_WARNING "DMA timeout with device %d\n",
1828                        dma_chan[ch].dev_id);
1829         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1830                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1831                        "with device %d\n", dma_chan[ch].dev_id);
1832         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1833                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1834         if (likely(dma_chan[ch].callback != NULL))
1835                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1836
1837         return 1;
1838 }
1839
1840 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1841 {
1842         int ch = ((int) dev_id) - 1;
1843         int handled = 0;
1844
1845         for (;;) {
1846                 int handled_now = 0;
1847
1848                 handled_now += omap1_dma_handle_ch(ch);
1849                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1850                         handled_now += omap1_dma_handle_ch(ch + 6);
1851                 if (!handled_now)
1852                         break;
1853                 handled += handled_now;
1854         }
1855
1856         return handled ? IRQ_HANDLED : IRQ_NONE;
1857 }
1858
1859 #else
1860 #define omap1_dma_irq_handler   NULL
1861 #endif
1862
1863 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1864                         defined(CONFIG_ARCH_OMAP4)
1865
1866 static int omap2_dma_handle_ch(int ch)
1867 {
1868         u32 status = dma_read(CSR(ch));
1869
1870         if (!status) {
1871                 if (printk_ratelimit())
1872                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1873                                 ch);
1874                 dma_write(1 << ch, IRQSTATUS_L0);
1875                 return 0;
1876         }
1877         if (unlikely(dma_chan[ch].dev_id == -1)) {
1878                 if (printk_ratelimit())
1879                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1880                                         "channel %d\n", status, ch);
1881                 return 0;
1882         }
1883         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1884                 printk(KERN_INFO
1885                        "DMA synchronization event drop occurred with device "
1886                        "%d\n", dma_chan[ch].dev_id);
1887         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1888                 printk(KERN_INFO "DMA transaction error with device %d\n",
1889                        dma_chan[ch].dev_id);
1890                 if (cpu_class_is_omap2()) {
1891                         /* Errata: sDMA Channel is not disabled
1892                          * after a transaction error. So we explicitely
1893                          * disable the channel
1894                          */
1895                         u32 ccr;
1896
1897                         ccr = dma_read(CCR(ch));
1898                         ccr &= ~OMAP_DMA_CCR_EN;
1899                         dma_write(ccr, CCR(ch));
1900                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1901                 }
1902         }
1903         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1904                 printk(KERN_INFO "DMA secure error with device %d\n",
1905                        dma_chan[ch].dev_id);
1906         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1907                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1908                        dma_chan[ch].dev_id);
1909
1910         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1911         dma_write(1 << ch, IRQSTATUS_L0);
1912
1913         /* If the ch is not chained then chain_id will be -1 */
1914         if (dma_chan[ch].chain_id != -1) {
1915                 int chain_id = dma_chan[ch].chain_id;
1916                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1917                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1918                         dma_chan[dma_chan[ch].next_linked_ch].state =
1919                                                         DMA_CH_STARTED;
1920                 if (dma_linked_lch[chain_id].chain_mode ==
1921                                                 OMAP_DMA_DYNAMIC_CHAIN)
1922                         disable_lnk(ch);
1923
1924                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1925                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1926
1927                 status = dma_read(CSR(ch));
1928         }
1929
1930         dma_write(status, CSR(ch));
1931
1932         if (likely(dma_chan[ch].callback != NULL))
1933                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1934
1935         return 0;
1936 }
1937
1938 /* STATUS register count is from 1-32 while our is 0-31 */
1939 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1940 {
1941         u32 val, enable_reg;
1942         int i;
1943
1944         val = dma_read(IRQSTATUS_L0);
1945         if (val == 0) {
1946                 if (printk_ratelimit())
1947                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1948                 return IRQ_HANDLED;
1949         }
1950         enable_reg = dma_read(IRQENABLE_L0);
1951         val &= enable_reg; /* Dispatch only relevant interrupts */
1952         for (i = 0; i < dma_lch_count && val != 0; i++) {
1953                 if (val & 1)
1954                         omap2_dma_handle_ch(i);
1955                 val >>= 1;
1956         }
1957
1958         return IRQ_HANDLED;
1959 }
1960
1961 static struct irqaction omap24xx_dma_irq = {
1962         .name = "DMA",
1963         .handler = omap2_dma_irq_handler,
1964         .flags = IRQF_DISABLED
1965 };
1966
1967 #else
1968 static struct irqaction omap24xx_dma_irq;
1969 #endif
1970
1971 /*----------------------------------------------------------------------------*/
1972
1973 static struct lcd_dma_info {
1974         spinlock_t lock;
1975         int reserved;
1976         void (*callback)(u16 status, void *data);
1977         void *cb_data;
1978
1979         int active;
1980         unsigned long addr, size;
1981         int rotate, data_type, xres, yres;
1982         int vxres;
1983         int mirror;
1984         int xscale, yscale;
1985         int ext_ctrl;
1986         int src_port;
1987         int single_transfer;
1988 } lcd_dma;
1989
1990 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1991                          int data_type)
1992 {
1993         lcd_dma.addr = addr;
1994         lcd_dma.data_type = data_type;
1995         lcd_dma.xres = fb_xres;
1996         lcd_dma.yres = fb_yres;
1997 }
1998 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1999
2000 void omap_set_lcd_dma_src_port(int port)
2001 {
2002         lcd_dma.src_port = port;
2003 }
2004
2005 void omap_set_lcd_dma_ext_controller(int external)
2006 {
2007         lcd_dma.ext_ctrl = external;
2008 }
2009 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2010
2011 void omap_set_lcd_dma_single_transfer(int single)
2012 {
2013         lcd_dma.single_transfer = single;
2014 }
2015 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2016
2017 void omap_set_lcd_dma_b1_rotation(int rotate)
2018 {
2019         if (omap_dma_in_1510_mode()) {
2020                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2021                 BUG();
2022                 return;
2023         }
2024         lcd_dma.rotate = rotate;
2025 }
2026 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2027
2028 void omap_set_lcd_dma_b1_mirror(int mirror)
2029 {
2030         if (omap_dma_in_1510_mode()) {
2031                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2032                 BUG();
2033         }
2034         lcd_dma.mirror = mirror;
2035 }
2036 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2037
2038 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2039 {
2040         if (omap_dma_in_1510_mode()) {
2041                 printk(KERN_ERR "DMA virtual resulotion is not supported "
2042                                 "in 1510 mode\n");
2043                 BUG();
2044         }
2045         lcd_dma.vxres = vxres;
2046 }
2047 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2048
2049 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2050 {
2051         if (omap_dma_in_1510_mode()) {
2052                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2053                 BUG();
2054         }
2055         lcd_dma.xscale = xscale;
2056         lcd_dma.yscale = yscale;
2057 }
2058 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2059
2060 static void set_b1_regs(void)
2061 {
2062         unsigned long top, bottom;
2063         int es;
2064         u16 w;
2065         unsigned long en, fn;
2066         long ei, fi;
2067         unsigned long vxres;
2068         unsigned int xscale, yscale;
2069
2070         switch (lcd_dma.data_type) {
2071         case OMAP_DMA_DATA_TYPE_S8:
2072                 es = 1;
2073                 break;
2074         case OMAP_DMA_DATA_TYPE_S16:
2075                 es = 2;
2076                 break;
2077         case OMAP_DMA_DATA_TYPE_S32:
2078                 es = 4;
2079                 break;
2080         default:
2081                 BUG();
2082                 return;
2083         }
2084
2085         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2086         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2087         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2088         BUG_ON(vxres < lcd_dma.xres);
2089
2090 #define PIXADDR(x, y) (lcd_dma.addr +                                   \
2091                 ((y) * vxres * yscale + (x) * xscale) * es)
2092 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2093
2094         switch (lcd_dma.rotate) {
2095         case 0:
2096                 if (!lcd_dma.mirror) {
2097                         top = PIXADDR(0, 0);
2098                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2099                         /* 1510 DMA requires the bottom address to be 2 more
2100                          * than the actual last memory access location. */
2101                         if (omap_dma_in_1510_mode() &&
2102                                 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2103                                         bottom += 2;
2104                         ei = PIXSTEP(0, 0, 1, 0);
2105                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2106                 } else {
2107                         top = PIXADDR(lcd_dma.xres - 1, 0);
2108                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2109                         ei = PIXSTEP(1, 0, 0, 0);
2110                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2111                 }
2112                 en = lcd_dma.xres;
2113                 fn = lcd_dma.yres;
2114                 break;
2115         case 90:
2116                 if (!lcd_dma.mirror) {
2117                         top = PIXADDR(0, lcd_dma.yres - 1);
2118                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2119                         ei = PIXSTEP(0, 1, 0, 0);
2120                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2121                 } else {
2122                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2123                         bottom = PIXADDR(0, 0);
2124                         ei = PIXSTEP(0, 1, 0, 0);
2125                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2126                 }
2127                 en = lcd_dma.yres;
2128                 fn = lcd_dma.xres;
2129                 break;
2130         case 180:
2131                 if (!lcd_dma.mirror) {
2132                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2133                         bottom = PIXADDR(0, 0);
2134                         ei = PIXSTEP(1, 0, 0, 0);
2135                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2136                 } else {
2137                         top = PIXADDR(0, lcd_dma.yres - 1);
2138                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2139                         ei = PIXSTEP(0, 0, 1, 0);
2140                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2141                 }
2142                 en = lcd_dma.xres;
2143                 fn = lcd_dma.yres;
2144                 break;
2145         case 270:
2146                 if (!lcd_dma.mirror) {
2147                         top = PIXADDR(lcd_dma.xres - 1, 0);
2148                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2149                         ei = PIXSTEP(0, 0, 0, 1);
2150                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2151                 } else {
2152                         top = PIXADDR(0, 0);
2153                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2154                         ei = PIXSTEP(0, 0, 0, 1);
2155                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2156                 }
2157                 en = lcd_dma.yres;
2158                 fn = lcd_dma.xres;
2159                 break;
2160         default:
2161                 BUG();
2162                 return; /* Suppress warning about uninitialized vars */
2163         }
2164
2165         if (omap_dma_in_1510_mode()) {
2166                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2167                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2168                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2169                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2170
2171                 return;
2172         }
2173
2174         /* 1610 regs */
2175         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2176         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2177         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2178         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2179
2180         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2181         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2182
2183         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2184         w &= ~0x03;
2185         w |= lcd_dma.data_type;
2186         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2187
2188         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2189         /* Always set the source port as SDRAM for now*/
2190         w &= ~(0x03 << 6);
2191         if (lcd_dma.callback != NULL)
2192                 w |= 1 << 1;            /* Block interrupt enable */
2193         else
2194                 w &= ~(1 << 1);
2195         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2196
2197         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2198               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2199                 return;
2200
2201         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2202         /* Set the double-indexed addressing mode */
2203         w |= (0x03 << 12);
2204         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2205
2206         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2207         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2208         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2209 }
2210
2211 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2212 {
2213         u16 w;
2214
2215         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2216         if (unlikely(!(w & (1 << 3)))) {
2217                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2218                 return IRQ_NONE;
2219         }
2220         /* Ack the IRQ */
2221         w |= (1 << 3);
2222         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2223         lcd_dma.active = 0;
2224         if (lcd_dma.callback != NULL)
2225                 lcd_dma.callback(w, lcd_dma.cb_data);
2226
2227         return IRQ_HANDLED;
2228 }
2229
2230 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2231                          void *data)
2232 {
2233         spin_lock_irq(&lcd_dma.lock);
2234         if (lcd_dma.reserved) {
2235                 spin_unlock_irq(&lcd_dma.lock);
2236                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2237                 BUG();
2238                 return -EBUSY;
2239         }
2240         lcd_dma.reserved = 1;
2241         spin_unlock_irq(&lcd_dma.lock);
2242         lcd_dma.callback = callback;
2243         lcd_dma.cb_data = data;
2244         lcd_dma.active = 0;
2245         lcd_dma.single_transfer = 0;
2246         lcd_dma.rotate = 0;
2247         lcd_dma.vxres = 0;
2248         lcd_dma.mirror = 0;
2249         lcd_dma.xscale = 0;
2250         lcd_dma.yscale = 0;
2251         lcd_dma.ext_ctrl = 0;
2252         lcd_dma.src_port = 0;
2253
2254         return 0;
2255 }
2256 EXPORT_SYMBOL(omap_request_lcd_dma);
2257
2258 void omap_free_lcd_dma(void)
2259 {
2260         spin_lock(&lcd_dma.lock);
2261         if (!lcd_dma.reserved) {
2262                 spin_unlock(&lcd_dma.lock);
2263                 printk(KERN_ERR "LCD DMA is not reserved\n");
2264                 BUG();
2265                 return;
2266         }
2267         if (!enable_1510_mode)
2268                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2269                             OMAP1610_DMA_LCD_CCR);
2270         lcd_dma.reserved = 0;
2271         spin_unlock(&lcd_dma.lock);
2272 }
2273 EXPORT_SYMBOL(omap_free_lcd_dma);
2274
2275 void omap_enable_lcd_dma(void)
2276 {
2277         u16 w;
2278
2279         /*
2280          * Set the Enable bit only if an external controller is
2281          * connected. Otherwise the OMAP internal controller will
2282          * start the transfer when it gets enabled.
2283          */
2284         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2285                 return;
2286
2287         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2288         w |= 1 << 8;
2289         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2290
2291         lcd_dma.active = 1;
2292
2293         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2294         w |= 1 << 7;
2295         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2296 }
2297 EXPORT_SYMBOL(omap_enable_lcd_dma);
2298
2299 void omap_setup_lcd_dma(void)
2300 {
2301         BUG_ON(lcd_dma.active);
2302         if (!enable_1510_mode) {
2303                 /* Set some reasonable defaults */
2304                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2305                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2306                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2307         }
2308         set_b1_regs();
2309         if (!enable_1510_mode) {
2310                 u16 w;
2311
2312                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2313                 /*
2314                  * If DMA was already active set the end_prog bit to have
2315                  * the programmed register set loaded into the active
2316                  * register set.
2317                  */
2318                 w |= 1 << 11;           /* End_prog */
2319                 if (!lcd_dma.single_transfer)
2320                         w |= (3 << 8);  /* Auto_init, repeat */
2321                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2322         }
2323 }
2324 EXPORT_SYMBOL(omap_setup_lcd_dma);
2325
2326 void omap_stop_lcd_dma(void)
2327 {
2328         u16 w;
2329
2330         lcd_dma.active = 0;
2331         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2332                 return;
2333
2334         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2335         w &= ~(1 << 7);
2336         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2337
2338         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2339         w &= ~(1 << 8);
2340         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2341 }
2342 EXPORT_SYMBOL(omap_stop_lcd_dma);
2343
2344 /*----------------------------------------------------------------------------*/
2345
2346 static int __init omap_init_dma(void)
2347 {
2348         int ch, r;
2349
2350         if (cpu_class_is_omap1()) {
2351                 omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
2352                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2353         } else if (cpu_is_omap24xx()) {
2354                 omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
2355                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2356         } else if (cpu_is_omap34xx()) {
2357                 omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
2358                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2359         } else if (cpu_is_omap44xx()) {
2360                 omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
2361                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2362         } else {
2363                 pr_err("DMA init failed for unsupported omap\n");
2364                 return -ENODEV;
2365         }
2366
2367         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2368                         && (omap_dma_reserve_channels <= dma_lch_count))
2369                 dma_lch_count = omap_dma_reserve_channels;
2370
2371         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2372                                 GFP_KERNEL);
2373         if (!dma_chan)
2374                 return -ENOMEM;
2375
2376         if (cpu_class_is_omap2()) {
2377                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2378                                                 dma_lch_count, GFP_KERNEL);
2379                 if (!dma_linked_lch) {
2380                         kfree(dma_chan);
2381                         return -ENOMEM;
2382                 }
2383         }
2384
2385         if (cpu_is_omap15xx()) {
2386                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2387                 dma_chan_count = 9;
2388                 enable_1510_mode = 1;
2389         } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2390                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2391                        dma_read(HW_ID));
2392                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2393                        (dma_read(CAPS_0_U) << 16) |
2394                        dma_read(CAPS_0_L),
2395                        (dma_read(CAPS_1_U) << 16) |
2396                        dma_read(CAPS_1_L),
2397                        dma_read(CAPS_2), dma_read(CAPS_3),
2398                        dma_read(CAPS_4));
2399                 if (!enable_1510_mode) {
2400                         u16 w;
2401
2402                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2403                         w = dma_read(GSCR);
2404                         w |= 1 << 3;
2405                         dma_write(w, GSCR);
2406                         dma_chan_count = 16;
2407                 } else
2408                         dma_chan_count = 9;
2409                 if (cpu_is_omap16xx()) {
2410                         u16 w;
2411
2412                         /* this would prevent OMAP sleep */
2413                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2414                         w &= ~(1 << 8);
2415                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2416                 }
2417         } else if (cpu_class_is_omap2()) {
2418                 u8 revision = dma_read(REVISION) & 0xff;
2419                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2420                        revision >> 4, revision & 0xf);
2421                 dma_chan_count = dma_lch_count;
2422         } else {
2423                 dma_chan_count = 0;
2424                 return 0;
2425         }
2426
2427         spin_lock_init(&lcd_dma.lock);
2428         spin_lock_init(&dma_chan_lock);
2429
2430         for (ch = 0; ch < dma_chan_count; ch++) {
2431                 omap_clear_dma(ch);
2432                 dma_chan[ch].dev_id = -1;
2433                 dma_chan[ch].next_lch = -1;
2434
2435                 if (ch >= 6 && enable_1510_mode)
2436                         continue;
2437
2438                 if (cpu_class_is_omap1()) {
2439                         /*
2440                          * request_irq() doesn't like dev_id (ie. ch) being
2441                          * zero, so we have to kludge around this.
2442                          */
2443                         r = request_irq(omap1_dma_irq[ch],
2444                                         omap1_dma_irq_handler, 0, "DMA",
2445                                         (void *) (ch + 1));
2446                         if (r != 0) {
2447                                 int i;
2448
2449                                 printk(KERN_ERR "unable to request IRQ %d "
2450                                        "for DMA (error %d)\n",
2451                                        omap1_dma_irq[ch], r);
2452                                 for (i = 0; i < ch; i++)
2453                                         free_irq(omap1_dma_irq[i],
2454                                                  (void *) (i + 1));
2455                                 return r;
2456                         }
2457                 }
2458         }
2459
2460         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2461                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2462                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2463
2464         if (cpu_class_is_omap2()) {
2465                 int irq;
2466                 if (cpu_is_omap44xx())
2467                         irq = INT_44XX_SDMA_IRQ0;
2468                 else
2469                         irq = INT_24XX_SDMA_IRQ0;
2470                 setup_irq(irq, &omap24xx_dma_irq);
2471         }
2472
2473         /* Enable smartidle idlemodes and autoidle */
2474         if (cpu_is_omap34xx()) {
2475                 u32 v = dma_read(OCP_SYSCONFIG);
2476                 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2477                                 DMA_SYSCONFIG_SIDLEMODE_MASK |
2478                                 DMA_SYSCONFIG_AUTOIDLE);
2479                 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2480                         DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2481                         DMA_SYSCONFIG_AUTOIDLE);
2482                 dma_write(v , OCP_SYSCONFIG);
2483         }
2484
2485
2486         /* FIXME: Update LCD DMA to work on 24xx */
2487         if (cpu_class_is_omap1()) {
2488                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2489                                 "LCD DMA", NULL);
2490                 if (r != 0) {
2491                         int i;
2492
2493                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2494                                "(error %d)\n", r);
2495                         for (i = 0; i < dma_chan_count; i++)
2496                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2497                         return r;
2498                 }
2499         }
2500
2501         return 0;
2502 }
2503
2504 arch_initcall(omap_init_dma);
2505
2506 /*
2507  * Reserve the omap SDMA channels using cmdline bootarg
2508  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2509  */
2510 static int __init omap_dma_cmdline_reserve_ch(char *str)
2511 {
2512         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2513                 omap_dma_reserve_channels = 0;
2514         return 1;
2515 }
2516
2517 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2518
2519