pdc2027x: Switch properly to ioread/iowrite

Some iomap functions were still using readl/writel and friends which
happens to work on most platforms but is not correct.

Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
index f87c800..3d3f155 100644 (file)
--- a/drivers/ata/pata_pdc2027x.c
+++ b/drivers/ata/pata_pdc2027x.c
@@ -273,7 +273,7 @@ static int pdc2027x_cable_detect(struct ata_port *ap)
        u32 cgcr;
 
        /* check cable detect results */
-       cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL));
+       cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
        if (cgcr & (1 << 26))
                goto cbl40;
 
@@ -291,7 +291,7 @@ cbl40:
  */
 static inline int pdc2027x_port_enabled(struct ata_port *ap)
 {
-       return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
+       return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
 }
 
 /**
@@ -383,16 +383,16 @@ static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
        /* Set the PIO timing registers using value table for 133MHz */
        PDPRINTK("Set pio regs... \n");
 
-       ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
+       ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
        ctcr0 &= 0xffff0000;
        ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
                (pdc2027x_pio_timing_tbl[pio].value1 << 8);
-       writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
+       iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
 
-       ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
+       ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
        ctcr1 &= 0x00ffffff;
        ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
-       writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
+       iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
 
        PDPRINTK("Set pio regs done\n");
 
@@ -426,18 +426,18 @@ static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
                         * If tHOLD is '1', the hardware will add half clock for data hold time.
                         * This code segment seems to be no effect. tHOLD will be overwritten below.
                         */
-                       ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
-                       writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
+                       ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
+                       iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
                }
 
                PDPRINTK("Set udma regs... \n");
 
-               ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
+               ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
                ctcr1 &= 0xff000000;
                ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
                        (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
                        (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
-               writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
+               iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
 
                PDPRINTK("Set udma regs done\n");
 
@@ -449,13 +449,13 @@ static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
                unsigned int mdma_mode = dma_mode & 0x07;
 
                PDPRINTK("Set mdma regs... \n");
-               ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
+               ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
 
                ctcr0 &= 0x0000ffff;
                ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
                        (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
 
-               writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
+               iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
                PDPRINTK("Set mdma regs done\n");
 
                PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
@@ -492,9 +492,9 @@ static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed
                         * Enable prefetch if the device support PIO only.
                         */
                        if (dev->xfer_shift == ATA_SHIFT_PIO) {
-                               u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1));
+                               u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
                                ctcr1 |= (1 << 25);
-                               writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
+                               iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
 
                                PDPRINTK("Turn on prefetch\n");
                        } else {
@@ -559,12 +559,12 @@ static long pdc_read_counter(struct ata_host *host)
        u32 bccrl, bccrh, bccrlv, bccrhv;
 
 retry:
-       bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
-       bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
+       bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
+       bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
 
        /* Read the counter values again for verification */
-       bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
-       bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
+       bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
+       bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
 
        counter = (bccrh << 15) | bccrl;
 
@@ -613,7 +613,7 @@ static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int b
        /* Show the current clock value of PLL control register
         * (maybe already configured by the firmware)
         */
-       pll_ctl = readw(mmio_base + PDC_PLL_CTL);
+       pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
 
        PDPRINTK("pll_ctl[%X]\n", pll_ctl);
 #endif
@@ -653,8 +653,8 @@ static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int b
 
        PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
 
-       writew(pll_ctl, mmio_base + PDC_PLL_CTL);
-       readw(mmio_base + PDC_PLL_CTL); /* flush */
+       iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
+       ioread16(mmio_base + PDC_PLL_CTL); /* flush */
 
        /* Wait the PLL circuit to be stable */
        mdelay(30);
@@ -664,7 +664,7 @@ static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int b
         *  Show the current clock value of PLL control register
         * (maybe configured by the firmware)
         */
-       pll_ctl = readw(mmio_base + PDC_PLL_CTL);
+       pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
 
        PDPRINTK("pll_ctl[%X]\n", pll_ctl);
 #endif
@@ -687,10 +687,10 @@ static long pdc_detect_pll_input_clock(struct ata_host *host)
        long pll_clock, usec_elapsed;
 
        /* Start the test mode */
-       scr = readl(mmio_base + PDC_SYS_CTL);
+       scr = ioread32(mmio_base + PDC_SYS_CTL);
        PDPRINTK("scr[%X]\n", scr);
-       writel(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
-       readl(mmio_base + PDC_SYS_CTL); /* flush */
+       iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
+       ioread32(mmio_base + PDC_SYS_CTL); /* flush */
 
        /* Read current counter value */
        start_count = pdc_read_counter(host);
@@ -704,10 +704,10 @@ static long pdc_detect_pll_input_clock(struct ata_host *host)
        do_gettimeofday(&end_time);
 
        /* Stop the test mode */
-       scr = readl(mmio_base + PDC_SYS_CTL);
+       scr = ioread32(mmio_base + PDC_SYS_CTL);
        PDPRINTK("scr[%X]\n", scr);
-       writel(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
-       readl(mmio_base + PDC_SYS_CTL); /* flush */
+       iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
+       ioread32(mmio_base + PDC_SYS_CTL); /* flush */
 
        /* calculate the input clock in Hz */
        usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +