MIPS R2 instruction hazard handling.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index b901473..08d7229 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -529,6 +529,7 @@ static void r4k_flush_icache_range(unsigned long __user start,
        args.end = end;
 
        on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
+       instruction_hazard();
 }
 
 /*

diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 181f08d..f63d824 100644 (file)
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -228,6 +228,22 @@ __asm__(
 
 #endif
 
+#if defined(CONFIG_CPU_MIPS32_R2) || defined (CONFIG_CPU_MIPS64_R2)
+#define instruction_hazard()                                           \
+do {                                                                   \
+__label__ __next;                                                      \
+       __asm__ __volatile__(                                           \
+       "       jr.hb   %0                                      \n"     \
+       :                                                               \
+       : "r" (&&__next));                                              \
+__next:                                                                        \
+       ;                                                               \
+} while (0)
+
+#else
+#define instruction_hazard() do { } while (0)
+#endif
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_HAZARDS_H */