sh: Fix up SH7786 PCI resource definitions.

This adds in some of the missing memory resources for channels 1/2 and
gets the code building again for the recent changes.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index feac1fe..95d095f 100644 (file)
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -1,7 +1,7 @@
 /*
  * Low-Level PCI Express Support for the SH7786
  *
- *  Copyright (C) 2009  Paul Mundt
+ *  Copyright (C) 2009 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -30,60 +30,84 @@ static struct sh7786_pcie_hwops {
        int (*port_init_hw)(struct sh7786_pcie_port *port);
 } *sh7786_pcie_hwops;
 
-static struct resource sh7786_pci_32bit_mem_resources[] = {
+static struct resource sh7786_pci0_resources[] = {
        {
-               .name   = "pci0_mem",
-               .start  = SH4A_PCIMEM_BASEA,
-               .end    = SH4A_PCIMEM_BASEA + SZ_64M - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "PCIe0 IO",
+               .start  = 0xfd000000,
+               .end    = 0xfd000000 + SZ_8M - 1,
+               .flags  = IORESOURCE_IO,
        }, {
-               .name   = "pci1_mem",
-               .start  = SH4A_PCIMEM_BASEA1,
-               .end    = SH4A_PCIMEM_BASEA1 + SZ_64M - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "PCIe0 MEM 0",
+               .start  = 0xc0000000,
+               .end    = 0xc0000000 + SZ_512M - 1,
+               .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
        }, {
-               .name   = "pci2_mem",
-               .start  = SH4A_PCIMEM_BASEA2,
-               .end    = SH4A_PCIMEM_BASEA2 + SZ_64M - 1,
+               .name   = "PCIe0 MEM 1",
+               .start  = 0x10000000,
+               .end    = 0x10000000 + SZ_64M - 1,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .name   = "PCIe0 MEM 2",
+               .start  = 0xfe100000,
+               .end    = 0xfe100000 + SZ_1M - 1,
        },
 };
 
-static struct resource sh7786_pci_29bit_mem_resource = {
-       .start  = SH4A_PCIMEM_BASE,
-       .end    = SH4A_PCIMEM_BASE + SZ_64M - 1,
-       .flags  = IORESOURCE_MEM,
+static struct resource sh7786_pci1_resources[] = {
+       {
+               .name   = "PCIe1 IO",
+               .start  = 0xfd800000,
+               .end    = 0xfd800000 + SZ_8M - 1,
+               .flags  = IORESOURCE_IO,
+       }, {
+               .name   = "PCIe1 MEM 0",
+               .start  = 0xa0000000,
+               .end    = 0xa0000000 + SZ_512M - 1,
+               .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+       }, {
+               .name   = "PCIe1 MEM 1",
+               .start  = 0x30000000,
+               .end    = 0x30000000 + SZ_256M - 1,
+               .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+       }, {
+               .name   = "PCIe1 MEM 2",
+               .start  = 0xfe300000,
+               .end    = 0xfe300000 + SZ_1M - 1,
+       },
 };
 
-static struct resource sh7786_pci_io_resources[] = {
+static struct resource sh7786_pci2_resources[] = {
        {
-               .name   = "pci0_io",
-               .start  = SH4A_PCIIO_BASE,
-               .end    = SH4A_PCIIO_BASE + SZ_8M - 1,
-               .flags  = IORESOURCE_IO,
+               .name   = "PCIe2 IO",
+               .start  = 0xfc800000,
+               .end    = 0xfc800000 + SZ_4M - 1,
        }, {
-               .name   = "pci1_io",
-               .start  = SH4A_PCIIO_BASE1,
-               .end    = SH4A_PCIIO_BASE1 + SZ_8M - 1,
-               .flags  = IORESOURCE_IO,
+               .name   = "PCIe2 MEM 0",
+               .start  = 0x80000000,
+               .end    = 0x80000000 + SZ_512M - 1,
+               .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
        }, {
-               .name   = "pci2_io",
-               .start  = SH4A_PCIIO_BASE2,
-               .end    = SH4A_PCIIO_BASE2 + SZ_4M - 1,
-               .flags  = IORESOURCE_IO,
+               .name   = "PCIe2 MEM 1",
+               .start  = 0x20000000,
+               .end    = 0x20000000 + SZ_256M - 1,
+               .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+       }, {
+               .name   = "PCIe2 MEM 2",
+               .start  = 0xfcd00000,
+               .end    = 0xfcd00000 + SZ_1M - 1,
        },
 };
 
 extern struct pci_ops sh7786_pci_ops;
 
-#define DEFINE_CONTROLLER(start, idx)                          \
-{                                                              \
-       .pci_ops        = &sh7786_pci_ops,                      \
-       .reg_base       = start,                                \
-       /* mem_resource filled in at probe time */              \
-       .mem_offset     = 0,                                    \
-       .io_resource    = &sh7786_pci_io_resources[idx],        \
-       .io_offset      = 0,                                    \
+#define DEFINE_CONTROLLER(start, idx)                                  \
+{                                                                      \
+       .pci_ops        = &sh7786_pci_ops,                              \
+       .resources      = sh7786_pci##idx##_resources,                  \
+       .nr_resources   = ARRAY_SIZE(sh7786_pci##idx##_resources),      \
+       .reg_base       = start,                                        \
+       .mem_offset     = 0,                                            \
+       .io_offset      = 0,                                            \
 }
 
 static struct pci_channel sh7786_pci_channels[] = {
@@ -330,17 +354,7 @@ static int __init sh7786_pcie_init(void)
 
                port->index             = i;
                port->hose              = sh7786_pci_channels + i;
-               port->hose->io_map_base = port->hose->io_resource->start;
-
-               /*
-                * Check if we are booting in 29 or 32-bit mode
-                *
-                * 32-bit mode provides each controller with its own
-                * memory window, while 29-bit mode uses a shared one.
-                */
-               port->hose->mem_resource = test_mode_pin(MODE_PIN10) ?
-                       &sh7786_pci_32bit_mem_resources[i] :
-                       &sh7786_pci_29bit_mem_resource;
+               port->hose->io_map_base = port->hose->resources[0].start;
 
                ret |= sh7786_pcie_hwops->port_init_hw(port);
        }

diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h
index c655290..6666ea2 100644 (file)
--- a/arch/sh/drivers/pci/pcie-sh7786.h
+++ b/arch/sh/drivers/pci/pcie-sh7786.h
@@ -30,47 +30,9 @@
  * for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
  */
 
-/* PCI0-0: PCI I/O space */
-#define SH4A_PCIIO_BASE                0xFD000000      /* PCI I/O for controller 0 */
-#define SH4A_PCIIO_BASE1       0xFD800000      /* PCI I/O for controller 1 (Rev1.14)*/
-#define SH4A_PCIIO_BASE2       0xFC800000      /* PCI I/O for controller 2 (Rev1.171)*/
-
-#define SH4A_PCIIO_SIZE64      0x00010000      /* PLX allows only 64K */
-#define SH4A_PCIIO_SIZE                0x00800000      /* 8M */
-#define SH4A_PCIIO_SIZE2       0x00400000      /* 4M (Rev1.171)*/
-
-/* PCI0-1: PCI memory space 29-bit address */
-#define SH4A_PCIMEM_BASE       0x10000000
-#define SH4A_PCIMEM_SIZE       0x04000000      /* 64M */
-
-/* PCI0-2: PCI memory space 32-bit address */
-#define SH4A_PCIMEM_BASEA      0xC0000000      /*  for controller 0 */
-#define SH4A_PCIMEM_BASEA1     0xA0000000      /*  for controller 1 (Rev1.14)*/
-#define SH4A_PCIMEM_BASEA2     0x80000000      /*  for controller 2 (Rev1.171)*/
-#define SH4A_PCIMEM_SIZEA      0x20000000      /* 512M */
-
 /* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
 #define SH4A_PCIBMSTR_TRANSLATION      0x20000000
 
-#define SH4A_PCI_DEVICE_ID             0x0002
-#define SH4A_PCI_VENDOR_ID             0x1912
-
-// PCI compatible 000-03f
-#define PCI_CMD                0x004
-#define PCI_RID                0x008
-#define PCI_IBAR       0x010
-#define PCI_MBAR0      0x014
-#define PCI_MBAR1      0x018
-
-/* PCI power management/MSI/capablity 040-0ff */
-/* PCIE extended 100-fff */
-
-/* SH7786 device identification */     // Rev1.171
-#define SH4A_PVR               (0xFF000030)
-#define SH4A_PVR_SHX3          (0x10400000)
-#define SH4A_PRR               (0xFF000044)
-#define SH4A_PRR_SH7786                (0x00000400)    // Rev1.171
-
 /*     SPVCR0          */
 #define        SH4A_PCIEVCR0           (0x000000)      /* R - 0x0000 0000 32 */
 #define                BITS_TOP_MB     (24)