[PATCH] x86_64: avoid wasting IRQs patch update

The patch adds boundary check for the MAX_GSI_NUM.  Same as the update for
i386, the patch addresses a problem with ACPI SCI IRQ.  The patch corrects
the code such that SCI IRQ is skipped and duplicate entry is avoided.  The
VIA chipset uses 4-bit IRQ register for internal interrupt routing, and
therefore cannot handle IRQ numbers assigned to its devices.  The patch
corrects this problem by allowing PCI IRQs below 16.

Signed-off-by: Natalie Protasevich <Natalie.Protasevich@unisys.com>
Acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/arch/x86_64/kernel/mpparse.c b/arch/x86_64/kernel/mpparse.c
index 08abf9f..79c362d 100644 (file)
--- a/arch/x86_64/kernel/mpparse.c
+++ b/arch/x86_64/kernel/mpparse.c
@@ -970,8 +970,21 @@ int mp_register_gsi(u32 gsi, int edge_level, int active_high_low)
                 * due to unused I/O APIC pins.
                 */
                int irq = gsi;
-               gsi = pci_irq++;
-               gsi_to_irq[irq] = gsi;
+               if (gsi < MAX_GSI_NUM) {
+                       if (gsi > 15)
+                               gsi = pci_irq++;
+#ifdef CONFIG_ACPI_BUS
+                       /*
+                        * Don't assign IRQ used by ACPI SCI
+                        */
+                       if (gsi == acpi_fadt.sci_int)
+                               gsi = pci_irq++;
+#endif
+                       gsi_to_irq[irq] = gsi;
+               } else {
+                       printk(KERN_ERR "GSI %u is too high\n", gsi);
+                       return gsi;
+               }
        }
 
        io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,