[ARM] S3C64XX: Fix MMC0 clock source register mask

Fix the definition of the MMC0 register shift and mask in the
CLKSRC register.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>

diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index 78938a5..b1082c1 100644 (file)
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -205,8 +205,8 @@
 #define S3C6400_CLKSRC_MMC2_SHIFT      (22)
 #define S3C6400_CLKSRC_MMC1_MASK       (0x3 << 20)
 #define S3C6400_CLKSRC_MMC1_SHIFT      (20)
-#define S3C6400_CLKSRC_MMC0_MASK       (0xf << 1)
-#define S3C6400_CLKSRC_MMC0_SHIFT      (1)
+#define S3C6400_CLKSRC_MMC0_MASK       (0x3 << 18)
+#define S3C6400_CLKSRC_MMC0_SHIFT      (18)
 #define S3C6400_CLKSRC_SPI1_MASK       (0x3 << 16)
 #define S3C6400_CLKSRC_SPI1_SHIFT      (16)
 #define S3C6400_CLKSRC_SPI0_MASK       (0x3 << 14)