DEFINE_SPINLOCK(mostek_lock);
DEFINE_SPINLOCK(rtc_lock);
-unsigned long mstk48t02_regs = 0UL;
+void * __iomem mstk48t02_regs = 0UL;
#ifdef CONFIG_PCI
unsigned long ds1287_regs = 0UL;
#endif
EXPORT_SYMBOL(jiffies_64);
-static unsigned long mstk48t08_regs = 0UL;
-static unsigned long mstk48t59_regs = 0UL;
+static void * __iomem mstk48t08_regs;
+static void * __iomem mstk48t59_regs;
static int set_rtc_mmss(unsigned long);
/* Kick start a stopped clock (procedure from the Sun NVRAM/hostid FAQ). */
static void __init kick_start_clock(void)
{
- unsigned long regs = mstk48t02_regs;
+ void * __iomem regs = mstk48t02_regs;
u8 sec, tmp;
int i, count;
/* Return nonzero if the clock chip battery is low. */
static int __init has_low_battery(void)
{
- unsigned long regs = mstk48t02_regs;
+ void * __iomem regs = mstk48t02_regs;
u8 data1, data2;
spin_lock_irq(&mostek_lock);
static void __init set_system_time(void)
{
unsigned int year, mon, day, hour, min, sec;
- unsigned long mregs = mstk48t02_regs;
+ void * __iomem mregs = mstk48t02_regs;
#ifdef CONFIG_PCI
unsigned long dregs = ds1287_regs;
#else
!strcmp(model, "m5823")) {
ds1287_regs = edev->resource[0].start;
} else {
- mstk48t59_regs = edev->resource[0].start;
+ mstk48t59_regs = (void * __iomem)
+ edev->resource[0].start;
mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
}
break;
!strcmp(model, "m5823")) {
ds1287_regs = isadev->resource.start;
} else {
- mstk48t59_regs = isadev->resource.start;
+ mstk48t59_regs = (void * __iomem)
+ isadev->resource.start;
mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
}
break;
}
if(model[5] == '0' && model[6] == '2') {
- mstk48t02_regs = (((u64)clk_reg[0].phys_addr) |
- (((u64)clk_reg[0].which_io)<<32UL));
+ mstk48t02_regs = (void * __iomem)
+ (((u64)clk_reg[0].phys_addr) |
+ (((u64)clk_reg[0].which_io)<<32UL));
} else if(model[5] == '0' && model[6] == '8') {
- mstk48t08_regs = (((u64)clk_reg[0].phys_addr) |
- (((u64)clk_reg[0].which_io)<<32UL));
+ mstk48t08_regs = (void * __iomem)
+ (((u64)clk_reg[0].phys_addr) |
+ (((u64)clk_reg[0].which_io)<<32UL));
mstk48t02_regs = mstk48t08_regs + MOSTEK_48T08_48T02;
} else {
- mstk48t59_regs = (((u64)clk_reg[0].phys_addr) |
- (((u64)clk_reg[0].which_io)<<32UL));
+ mstk48t59_regs = (void * __iomem)
+ (((u64)clk_reg[0].phys_addr) |
+ (((u64)clk_reg[0].which_io)<<32UL));
mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
}
break;
}
- if (mstk48t02_regs != 0UL) {
+ if (mstk48t02_regs != NULL) {
/* Report a low battery voltage condition. */
if (has_low_battery())
prom_printf("NVRAM: Low battery voltage!\n");
static int set_rtc_mmss(unsigned long nowtime)
{
int real_seconds, real_minutes, chip_minutes;
- unsigned long mregs = mstk48t02_regs;
+ void * __iomem mregs = mstk48t02_regs;
#ifdef CONFIG_PCI
unsigned long dregs = ds1287_regs;
#else
static int rtc_busy = 0;
+/* This is the structure layout used by drivers/char/rtc.c, we
+ * support that driver's ioctls so that things are less messy in
+ * userspace.
+ */
+struct rtc_time_generic {
+ int tm_sec;
+ int tm_min;
+ int tm_hour;
+ int tm_mday;
+ int tm_mon;
+ int tm_year;
+ int tm_wday;
+ int tm_yday;
+ int tm_isdst;
+};
+#define RTC_AIE_ON _IO('p', 0x01) /* Alarm int. enable on */
+#define RTC_AIE_OFF _IO('p', 0x02) /* ... off */
+#define RTC_UIE_ON _IO('p', 0x03) /* Update int. enable on */
+#define RTC_UIE_OFF _IO('p', 0x04) /* ... off */
+#define RTC_PIE_ON _IO('p', 0x05) /* Periodic int. enable on */
+#define RTC_PIE_OFF _IO('p', 0x06) /* ... off */
+#define RTC_WIE_ON _IO('p', 0x0f) /* Watchdog int. enable on */
+#define RTC_WIE_OFF _IO('p', 0x10) /* ... off */
+#define RTC_RD_TIME _IOR('p', 0x09, struct rtc_time_generic) /* Read RTC time */
+#define RTC_SET_TIME _IOW('p', 0x0a, struct rtc_time_generic) /* Set RTC time */
+#define RTC_ALM_SET _IOW('p', 0x07, struct rtc_time) /* Set alarm time */
+#define RTC_ALM_READ _IOR('p', 0x08, struct rtc_time) /* Read alarm time */
+#define RTC_IRQP_READ _IOR('p', 0x0b, unsigned long) /* Read IRQ rate */
+#define RTC_IRQP_SET _IOW('p', 0x0c, unsigned long) /* Set IRQ rate */
+#define RTC_EPOCH_READ _IOR('p', 0x0d, unsigned long) /* Read epoch */
+#define RTC_EPOCH_SET _IOW('p', 0x0e, unsigned long) /* Set epoch */
+#define RTC_WKALM_SET _IOW('p', 0x0f, struct rtc_wkalrm)/* Set wakeup alarm*/
+#define RTC_WKALM_RD _IOR('p', 0x10, struct rtc_wkalrm)/* Get wakeup alarm*/
+#define RTC_PLL_GET _IOR('p', 0x11, struct rtc_pll_info) /* Get PLL correction */
+#define RTC_PLL_SET _IOW('p', 0x12, struct rtc_pll_info) /* Set PLL correction */
+
/* Retrieve the current date and time from the real time clock. */
static void get_rtc_time(struct rtc_time *t)
{
spin_unlock_irq(&mostek_lock);
}
+static int put_rtc_time_generic(void __user *argp, struct rtc_time *tm)
+{
+ struct rtc_time_generic __user *utm = argp;
+
+ if (__put_user(tm->sec, &utm->tm_sec) ||
+ __put_user(tm->min, &utm->tm_min) ||
+ __put_user(tm->hour, &utm->tm_hour) ||
+ __put_user(tm->dom, &utm->tm_mday) ||
+ __put_user(tm->month, &utm->tm_mon) ||
+ __put_user(tm->year, &utm->tm_year) ||
+ __put_user(tm->dow, &utm->tm_wday) ||
+ __put_user(0, &utm->tm_yday) ||
+ __put_user(0, &utm->tm_isdst))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int get_rtc_time_generic(struct rtc_time *tm, void __user *argp)
+{
+ struct rtc_time_generic __user *utm = argp;
+
+ if (__get_user(tm->sec, &utm->tm_sec) ||
+ __get_user(tm->min, &utm->tm_min) ||
+ __get_user(tm->hour, &utm->tm_hour) ||
+ __get_user(tm->dom, &utm->tm_mday) ||
+ __get_user(tm->month, &utm->tm_mon) ||
+ __get_user(tm->year, &utm->tm_year) ||
+ __get_user(tm->dow, &utm->tm_wday))
+ return -EFAULT;
+
+ return 0;
+}
+
static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
unsigned long arg)
{
struct rtc_time rtc_tm;
void __user *argp = (void __user *)arg;
- switch (cmd)
- {
+ switch (cmd) {
+ /* No interrupt support, return an error
+ * compatible with drivers/char/rtc.c
+ */
+ case RTC_AIE_OFF:
+ case RTC_AIE_ON:
+ case RTC_PIE_OFF:
+ case RTC_PIE_ON:
+ case RTC_UIE_OFF:
+ case RTC_UIE_ON:
+ case RTC_IRQP_READ:
+ case RTC_IRQP_SET:
+ case RTC_EPOCH_SET:
+ case RTC_EPOCH_READ:
+ return -EINVAL;
+
case RTCGET:
+ case RTC_RD_TIME:
memset(&rtc_tm, 0, sizeof(struct rtc_time));
get_rtc_time(&rtc_tm);
- if (copy_to_user(argp, &rtc_tm, sizeof(struct rtc_time)))
+ if (cmd == RTCGET) {
+ if (copy_to_user(argp, &rtc_tm,
+ sizeof(struct rtc_time)))
+ return -EFAULT;
+ } else if (put_rtc_time_generic(argp, &rtc_tm))
return -EFAULT;
return 0;
case RTCSET:
+ case RTC_SET_TIME:
if (!capable(CAP_SYS_TIME))
return -EPERM;
- if (copy_from_user(&rtc_tm, argp, sizeof(struct rtc_time)))
+ if (cmd == RTCSET) {
+ if (copy_from_user(&rtc_tm, argp,
+ sizeof(struct rtc_time)))
+ return -EFAULT;
+ } else if (get_rtc_time_generic(&rtc_tm, argp))
return -EFAULT;
set_rtc_time(&rtc_tm);
printk(KERN_ERR "rtc: unable to get misc minor for Mostek\n");
return error;
}
+ printk("rtc_sun_init: Registered Mostek RTC driver.\n");
return 0;
}
/* Internal routine, port->lock is held and local interrupts are disabled. */
static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
- unsigned int iflag, int baud)
+ unsigned int iflag, unsigned int baud,
+ unsigned int quot)
{
unsigned int ebrg;
unsigned char dafo;
up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
SAB82532_ISR0_TCD);
+ uart_update_timeout(&up->port, cflag,
+ (up->port.uartclk / (16 * quot)));
+
/* Now bang the new settings into the chip. */
sunsab_cec_wait(up);
sunsab_tec_wait(up);
{
struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
unsigned long flags;
- int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
+ unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
+ unsigned int quot = uart_get_divisor(port, baud);
spin_lock_irqsave(&up->port.lock, flags);
- sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud);
+ sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
spin_unlock_irqrestore(&up->port.lock, flags);
}
{
struct uart_sunsab_port *up = &sunsab_ports[con->index];
unsigned long flags;
- int baud;
+ unsigned int baud, quot;
printk("Console: ttyS%d (SAB82532)\n",
(sunsab_reg.minor - 64) + con->index);
SAB82532_IMR1_XPR;
writeb(up->interrupt_mask1, &up->regs->w.imr1);
- sunsab_convert_to_sab(up, con->cflag, 0, baud);
+ quot = uart_get_divisor(&up->port, baud);
+ sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
spin_unlock_irqrestore(&up->port.lock, flags);
static int __init sunsu_kbd_ms_init(struct uart_sunsu_port *up, int channel)
{
+ int quot, baud;
#ifdef CONFIG_SERIO
struct serio *serio;
#endif
up->port.type = PORT_UNKNOWN;
up->port.uartclk = (SU_BASE_BAUD * 16);
- if (up->su_type == SU_PORT_KBD)
+ if (up->su_type == SU_PORT_KBD) {
up->cflag = B1200 | CS8 | CLOCAL | CREAD;
- else
+ baud = 1200;
+ } else {
up->cflag = B4800 | CS8 | CLOCAL | CREAD;
+ baud = 4800;
+ }
+ quot = up->port.uartclk / (16 * baud);
sunsu_autoconfig(up);
if (up->port.type == PORT_UNKNOWN)
}
#endif
+ sunsu_change_speed(&up->port, up->cflag, 0, quot);
+
sunsu_startup(&up->port);
return 0;
}
*
* We now deal with physical addresses for I/O to the chip. -DaveM
*/
-static __inline__ u8 mostek_read(unsigned long addr)
+static __inline__ u8 mostek_read(void * __iomem addr)
{
u8 ret;
return ret;
}
-static __inline__ void mostek_write(unsigned long addr, u8 val)
+static __inline__ void mostek_write(void * __iomem addr, u8 val)
{
__asm__ __volatile__("stba %0, [%1] %2"
: /* no outputs */
#define MOSTEK_YEAR 0x07ffUL
extern spinlock_t mostek_lock;
-extern unsigned long mstk48t02_regs;
+extern void *__iomem mstk48t02_regs;
/* Control register values. */
#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
unsigned long pfn,
unsigned long size, pgprot_t prot);
+/* Clear virtual and physical cachability, set side-effect bit. */
+#define pgprot_noncached(prot) \
+ (__pgprot((pgprot_val(prot) & ~(_PAGE_CP | _PAGE_CV)) | \
+ _PAGE_E))
+
/*
* For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
* its high 4 bits. These macros/functions put it there or get it from there.