[SPARC64]: Replace cheetah+ code patching with variables.

Instead of code patching to handle the page size fields in
the context registers, just use variables from which we get
the proper values.

Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index 2879b10..f685035 100644 (file)
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -97,8 +97,8 @@ do_fpdis:
        faddd           %f0, %f2, %f4
        fmuld           %f0, %f2, %f6
        ldxa            [%g3] ASI_DMMU, %g5
-cplus_fptrap_insn_1:
-       sethi           %hi(0), %g2
+       sethi           %hi(sparc64_kern_sec_context), %g2
+       ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
        stxa            %g2, [%g3] ASI_DMMU
        membar          #Sync
        add             %g6, TI_FPREGS + 0xc0, %g2
@@ -126,8 +126,8 @@ cplus_fptrap_insn_1:
        fzero           %f34
        ldxa            [%g3] ASI_DMMU, %g5
        add             %g6, TI_FPREGS, %g1
-cplus_fptrap_insn_2:
-       sethi           %hi(0), %g2
+       sethi           %hi(sparc64_kern_sec_context), %g2
+       ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
        stxa            %g2, [%g3] ASI_DMMU
        membar          #Sync
        add             %g6, TI_FPREGS + 0x40, %g2
@@ -153,8 +153,8 @@ cplus_fptrap_insn_2:
 3:     mov             SECONDARY_CONTEXT, %g3
        add             %g6, TI_FPREGS, %g1
        ldxa            [%g3] ASI_DMMU, %g5
-cplus_fptrap_insn_3:
-       sethi           %hi(0), %g2
+       sethi           %hi(sparc64_kern_sec_context), %g2
+       ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
        stxa            %g2, [%g3] ASI_DMMU
        membar          #Sync
        mov             0x40, %g2
@@ -319,8 +319,8 @@ do_fptrap_after_fsr:
        stx             %g3, [%g6 + TI_GSR]
        mov             SECONDARY_CONTEXT, %g3
        ldxa            [%g3] ASI_DMMU, %g5
-cplus_fptrap_insn_4:
-       sethi           %hi(0), %g2
+       sethi           %hi(sparc64_kern_sec_context), %g2
+       ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
        stxa            %g2, [%g3] ASI_DMMU
        membar          #Sync
        add             %g6, TI_FPREGS, %g2
@@ -341,33 +341,6 @@ cplus_fptrap_insn_4:
        ba,pt           %xcc, etrap
         wr             %g0, 0, %fprs
 
-cplus_fptrap_1:
-       sethi           %hi(CTX_CHEETAH_PLUS_CTX0), %g2
-
-       .globl          cheetah_plus_patch_fpdis
-cheetah_plus_patch_fpdis:
-       /* We configure the dTLB512_0 for 4MB pages and the
-        * dTLB512_1 for 8K pages when in context zero.
-        */
-       sethi                   %hi(cplus_fptrap_1), %o0
-       lduw                    [%o0 + %lo(cplus_fptrap_1)], %o1
-
-       set                     cplus_fptrap_insn_1, %o2
-       stw                     %o1, [%o2]
-       flush                   %o2
-       set                     cplus_fptrap_insn_2, %o2
-       stw                     %o1, [%o2]
-       flush                   %o2
-       set                     cplus_fptrap_insn_3, %o2
-       stw                     %o1, [%o2]
-       flush                   %o2
-       set                     cplus_fptrap_insn_4, %o2
-       stw                     %o1, [%o2]
-       flush                   %o2
-
-       retl
-        nop
-
        /* The registers for cross calls will be:
         *
         * DATA 0: [low 32-bits]  Address of function to call, jmp to this

diff --git a/arch/sparc64/kernel/etrap.S b/arch/sparc64/kernel/etrap.S
index 50d2af1..0d8eba2 100644 (file)
--- a/arch/sparc64/kernel/etrap.S
+++ b/arch/sparc64/kernel/etrap.S
@@ -68,12 +68,8 @@ etrap_irq:
 
                wrpr    %g3, 0, %otherwin
                wrpr    %g2, 0, %wstate
-cplus_etrap_insn_1:
-               sethi   %hi(0), %g3
-               sllx    %g3, 32, %g3
-cplus_etrap_insn_2:
-               sethi   %hi(0), %g2
-               or      %g3, %g2, %g3
+               sethi   %hi(sparc64_kern_pri_context), %g2
+               ldx     [%g2 + %lo(sparc64_kern_pri_context)], %g3
                stxa    %g3, [%l4] ASI_DMMU
                flush   %l6
                wr      %g0, ASI_AIUS, %asi
@@ -215,12 +211,8 @@ scetrap:   rdpr    %pil, %g2
                mov     PRIMARY_CONTEXT, %l4
                wrpr    %g3, 0, %otherwin
                wrpr    %g2, 0, %wstate
-cplus_etrap_insn_3:
-               sethi   %hi(0), %g3
-               sllx    %g3, 32, %g3
-cplus_etrap_insn_4:
-               sethi   %hi(0), %g2
-               or      %g3, %g2, %g3
+               sethi   %hi(sparc64_kern_pri_context), %g2
+               ldx     [%g2 + %lo(sparc64_kern_pri_context)], %g3
                stxa    %g3, [%l4] ASI_DMMU
                flush   %l6
 
@@ -264,38 +256,3 @@ cplus_etrap_insn_4:
 
 #undef TASK_REGOFF
 #undef ETRAP_PSTATE1
-
-cplus_einsn_1:
-               sethi                   %uhi(CTX_CHEETAH_PLUS_NUC), %g3
-cplus_einsn_2:
-               sethi                   %hi(CTX_CHEETAH_PLUS_CTX0), %g2
-
-               .globl                  cheetah_plus_patch_etrap
-cheetah_plus_patch_etrap:
-               /* We configure the dTLB512_0 for 4MB pages and the
-                * dTLB512_1 for 8K pages when in context zero.
-                */
-               sethi                   %hi(cplus_einsn_1), %o0
-               sethi                   %hi(cplus_etrap_insn_1), %o2
-               lduw                    [%o0 + %lo(cplus_einsn_1)], %o1
-               or                      %o2, %lo(cplus_etrap_insn_1), %o2
-               stw                     %o1, [%o2]
-               flush                   %o2
-               sethi                   %hi(cplus_etrap_insn_3), %o2
-               or                      %o2, %lo(cplus_etrap_insn_3), %o2
-               stw                     %o1, [%o2]
-               flush                   %o2
-
-               sethi                   %hi(cplus_einsn_2), %o0
-               sethi                   %hi(cplus_etrap_insn_2), %o2
-               lduw                    [%o0 + %lo(cplus_einsn_2)], %o1
-               or                      %o2, %lo(cplus_etrap_insn_2), %o2
-               stw                     %o1, [%o2]
-               flush                   %o2
-               sethi                   %hi(cplus_etrap_insn_4), %o2
-               or                      %o2, %lo(cplus_etrap_insn_4), %o2
-               stw                     %o1, [%o2]
-               flush                   %o2
-
-               retl
-                nop

diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S
index 89406f9..2434049 100644 (file)
--- a/arch/sparc64/kernel/head.S
+++ b/arch/sparc64/kernel/head.S
@@ -325,23 +325,7 @@ cheetah_tlb_fixup:
 1:     sethi   %hi(tlb_type), %g1
        stw     %g2, [%g1 + %lo(tlb_type)]
 
-       BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
-       ba,pt   %xcc, 2f
-        nop
-
-1:     /* Patch context register writes to support nucleus page
-        * size correctly.
-        */
-       call    cheetah_plus_patch_etrap
-        nop
-       call    cheetah_plus_patch_rtrap
-        nop
-       call    cheetah_plus_patch_fpdis
-        nop
-       call    cheetah_plus_patch_winfixup
-        nop
-
-2:     /* Patch copy/page operations to cheetah optimized versions. */
+       /* Patch copy/page operations to cheetah optimized versions. */
        call    cheetah_patch_copyops
         nop
        call    cheetah_patch_copy_page
@@ -484,20 +468,13 @@ spitfire_vpte_base:
        call    prom_set_trap_table
         sethi  %hi(sparc64_ttable_tl0), %o0
 
-       BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f)
-       ba,pt   %xcc, 2f
-        nop
-
-1:     /* Start using proper page size encodings in ctx register.  */
-       sethi   %uhi(CTX_CHEETAH_PLUS_NUC), %g3
+       /* Start using proper page size encodings in ctx register.  */
+       sethi   %hi(sparc64_kern_pri_context), %g3
+       ldx     [%g3 + %lo(sparc64_kern_pri_context)], %g2
        mov     PRIMARY_CONTEXT, %g1
-       sllx    %g3, 32, %g3
-       sethi   %hi(CTX_CHEETAH_PLUS_CTX0), %g2
-       or      %g3, %g2, %g3
-       stxa    %g3, [%g1] ASI_DMMU
+       stxa    %g2, [%g1] ASI_DMMU
        membar  #Sync
 
-2:
        rdpr    %pstate, %o1
        or      %o1, PSTATE_IE, %o1
        wrpr    %o1, 0, %pstate

diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
index fafd227..ecfb42a 100644 (file)
--- a/arch/sparc64/kernel/rtrap.S
+++ b/arch/sparc64/kernel/rtrap.S
@@ -256,9 +256,8 @@ rt_continue:        ldx                     [%sp + PTREGS_OFF + PT_V9_G1], %g1
                brnz,pn                 %l3, kern_rtt
                 mov                    PRIMARY_CONTEXT, %l7
                ldxa                    [%l7 + %l7] ASI_DMMU, %l0
-cplus_rtrap_insn_1:
-               sethi                   %hi(0), %l1
-               sllx                    %l1, 32, %l1
+               sethi                   %hi(sparc64_kern_pri_nuc_bits), %l1
+               ldx                     [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
                or                      %l0, %l1, %l0
                stxa                    %l0, [%l7] ASI_DMMU
                flush                   %g6
@@ -345,21 +344,3 @@ kern_fpucheck:     ldub                    [%g6 + TI_FPDEPTH], %l5
                wr                      %g0, FPRS_DU, %fprs
                ba,pt                   %xcc, rt_continue
                 stb                    %l5, [%g6 + TI_FPDEPTH]
-
-cplus_rinsn_1:
-               sethi                   %uhi(CTX_CHEETAH_PLUS_NUC), %l1
-
-               .globl                  cheetah_plus_patch_rtrap
-cheetah_plus_patch_rtrap:
-               /* We configure the dTLB512_0 for 4MB pages and the
-                * dTLB512_1 for 8K pages when in context zero.
-                */
-               sethi                   %hi(cplus_rinsn_1), %o0
-               sethi                   %hi(cplus_rtrap_insn_1), %o2
-               lduw                    [%o0 + %lo(cplus_rinsn_1)], %o1
-               or                      %o2, %lo(cplus_rtrap_insn_1), %o2
-               stw                     %o1, [%o2]
-               flush                   %o2
-
-               retl
-                nop

diff --git a/arch/sparc64/kernel/setup.c b/arch/sparc64/kernel/setup.c
index 4c9c8f2..c1f3423 100644 (file)
--- a/arch/sparc64/kernel/setup.c
+++ b/arch/sparc64/kernel/setup.c
@@ -187,17 +187,13 @@ int prom_callback(long *args)
                }
 
                if ((va >= KERNBASE) && (va < (KERNBASE + (4 * 1024 * 1024)))) {
-                       unsigned long kernel_pctx = 0;
-
-                       if (tlb_type == cheetah_plus)
-                               kernel_pctx |= (CTX_CHEETAH_PLUS_NUC |
-                                               CTX_CHEETAH_PLUS_CTX0);
+                       extern unsigned long sparc64_kern_pri_context;
 
                        /* Spitfire Errata #32 workaround */
                        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
                                             "flush     %%g6"
                                             : /* No outputs */
-                                            : "r" (kernel_pctx),
+                                            : "r" (sparc64_kern_pri_context),
                                               "r" (PRIMARY_CONTEXT),
                                               "i" (ASI_DMMU));
 

diff --git a/arch/sparc64/kernel/trampoline.S b/arch/sparc64/kernel/trampoline.S
index 89f2fcf..9478551 100644 (file)
--- a/arch/sparc64/kernel/trampoline.S
+++ b/arch/sparc64/kernel/trampoline.S
@@ -336,20 +336,13 @@ do_unlock:
        call            init_irqwork_curcpu
         nop
 
-       BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f)
-       ba,pt   %xcc, 2f
-        nop
-
-1:     /* Start using proper page size encodings in ctx register.  */
-       sethi   %uhi(CTX_CHEETAH_PLUS_NUC), %g3
+       /* Start using proper page size encodings in ctx register.  */
+       sethi   %hi(sparc64_kern_pri_context), %g3
+       ldx     [%g3 + %lo(sparc64_kern_pri_context)], %g2
        mov     PRIMARY_CONTEXT, %g1
-       sllx    %g3, 32, %g3
-       sethi   %hi(CTX_CHEETAH_PLUS_CTX0), %g2
-       or      %g3, %g2, %g3
-       stxa    %g3, [%g1] ASI_DMMU
+       stxa    %g2, [%g1] ASI_DMMU
        membar  #Sync
 
-2:
        rdpr            %pstate, %o1
        or              %o1, PSTATE_IE, %o1
        wrpr            %o1, 0, %pstate

diff --git a/arch/sparc64/kernel/winfixup.S b/arch/sparc64/kernel/winfixup.S
index 99c809a..3916092 100644 (file)
--- a/arch/sparc64/kernel/winfixup.S
+++ b/arch/sparc64/kernel/winfixup.S
@@ -16,23 +16,14 @@
        .text
 
 set_pcontext:
-cplus_winfixup_insn_1:
-       sethi   %hi(0), %l1
+       sethi   %hi(sparc64_kern_pri_context), %l1
+       ldx     [%l1 + %lo(sparc64_kern_pri_context)], %l1
        mov     PRIMARY_CONTEXT, %g1
-       sllx    %l1, 32, %l1
-cplus_winfixup_insn_2:
-       sethi   %hi(0), %g2
-       or      %l1, %g2, %l1
        stxa    %l1, [%g1] ASI_DMMU
        flush   %g6
        retl
         nop
 
-cplus_wfinsn_1:
-       sethi   %uhi(CTX_CHEETAH_PLUS_NUC), %l1
-cplus_wfinsn_2:
-       sethi   %hi(CTX_CHEETAH_PLUS_CTX0), %g2
-
        .align  32
 
        /* Here are the rules, pay attention.
@@ -395,23 +386,3 @@ window_dax_from_user_common:
         add            %sp, PTREGS_OFF, %o0
        ba,pt           %xcc, rtrap
         clr            %l6
-       
-
-       .globl          cheetah_plus_patch_winfixup
-cheetah_plus_patch_winfixup:
-       sethi                   %hi(cplus_wfinsn_1), %o0
-       sethi                   %hi(cplus_winfixup_insn_1), %o2
-       lduw                    [%o0 + %lo(cplus_wfinsn_1)], %o1
-       or                      %o2, %lo(cplus_winfixup_insn_1), %o2
-       stw                     %o1, [%o2]
-       flush                   %o2
-
-       sethi                   %hi(cplus_wfinsn_2), %o0
-       sethi                   %hi(cplus_winfixup_insn_2), %o2
-       lduw                    [%o0 + %lo(cplus_wfinsn_2)], %o1
-       or                      %o2, %lo(cplus_winfixup_insn_2), %o2
-       stw                     %o1, [%o2]
-       flush                   %o2
-
-       retl
-        nop

diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index 5db5052..4e2f71e 100644 (file)
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -133,6 +133,12 @@ extern unsigned int sparc_ramdisk_size;
 
 struct page *mem_map_zero __read_mostly;
 
+unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
+
+unsigned long sparc64_kern_pri_context __read_mostly;
+unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
+unsigned long sparc64_kern_sec_context __read_mostly;
+
 int bigkernel = 0;
 
 /* XXX Tune this... */
@@ -582,13 +588,21 @@ static void __init remap_kernel(void)
        prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
        prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
        if (bigkernel) {
-               prom_dtlb_load(tlb_ent - 1,
+               tlb_ent -= 1;
+               prom_dtlb_load(tlb_ent,
                               tte_data + 0x400000, 
                               tte_vaddr + 0x400000);
-               prom_itlb_load(tlb_ent - 1,
+               prom_itlb_load(tlb_ent,
                               tte_data + 0x400000, 
                               tte_vaddr + 0x400000);
        }
+       sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
+       if (tlb_type == cheetah_plus) {
+               sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
+                                           CTX_CHEETAH_PLUS_NUC);
+               sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
+               sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
+       }
 }
 
 static void __init inherit_prom_mappings(void)
@@ -788,8 +802,8 @@ void inherit_locked_prom_mappings(int save_p)
                }
        }
        if (tlb_type == spitfire) {
-               int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
-               for (i = 0; i < high; i++) {
+               int high = sparc64_highest_unlocked_tlb_ent;
+               for (i = 0; i <= high; i++) {
                        unsigned long data;
 
                        /* Spitfire Errata #32 workaround */
@@ -877,9 +891,9 @@ void inherit_locked_prom_mappings(int save_p)
                        }
                }
        } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
-               int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
+               int high = sparc64_highest_unlocked_tlb_ent;
 
-               for (i = 0; i < high; i++) {
+               for (i = 0; i <= high; i++) {
                        unsigned long data;
 
                        data = cheetah_get_ldtlb_data(i);