Limit maximum divider to 0x3ff to divider computations. On high I2C
parent clock rates, the divider can exceed 0x3ff. This will help
prevent some very odd clock rates.
Signed-off-by: Kevin Wells <wellsk40@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
*/
tmp = ((freq / 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2;
*/
tmp = ((freq / 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2;
+ if (tmp > 0x3FF)
+ tmp = 0x3FF;
iowrite32(tmp, I2C_REG_CKH(alg_data));
iowrite32(tmp, I2C_REG_CKL(alg_data));
iowrite32(tmp, I2C_REG_CKH(alg_data));
iowrite32(tmp, I2C_REG_CKL(alg_data));