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perfcounters: IRQ and NMI support on AMD CPUs, fix
author
Peter Zijlstra
<peterz@infradead.org>
Thu, 5 Mar 2009 19:34:21 +0000
(20:34 +0100)
committer
Ingo Molnar
<mingo@elte.hu>
Thu, 5 Mar 2009 19:37:21 +0000
(20:37 +0100)
The BKGD suggests that counter width on AMD CPUs is 48 for all
existing models (it certainly is for mine).
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perf_counter.c
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diff --git
a/arch/x86/kernel/cpu/perf_counter.c
b/arch/x86/kernel/cpu/perf_counter.c
index
6ebe9ab
..
f585371
100644
(file)
--- a/
arch/x86/kernel/cpu/perf_counter.c
+++ b/
arch/x86/kernel/cpu/perf_counter.c
@@
-959,20
+959,8
@@
static struct pmc_x86_ops *pmc_amd_init(void)
nr_counters_generic = 4;
nr_counters_fixed = 0;
nr_counters_generic = 4;
nr_counters_fixed = 0;
- counter_value_mask = ~0ULL;
-
- rdmsrl(MSR_K7_PERFCTR0, old);
- wrmsrl(MSR_K7_PERFCTR0, counter_value_mask);
- /*
- * read the truncated mask
- */
- rdmsrl(MSR_K7_PERFCTR0, counter_value_mask);
- wrmsrl(MSR_K7_PERFCTR0, old);
-
- bits = 32 + fls(counter_value_mask >> 32);
- if (bits == 32)
- bits = fls((u32)counter_value_mask);
- counter_value_bits = bits;
+ counter_value_mask = 0x0000FFFFFFFFFFFFULL;
+ counter_value_bits = 48;
pr_info("AMD Performance Monitoring support detected.\n");
pr_info("AMD Performance Monitoring support detected.\n");