One overzealous .align 10 fixed, and a few .align5 added.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
*
* Called with IRQs disabled
*/
*
* Called with IRQs disabled
*/
ENTRY(cpu_feroceon_do_idle)
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
ENTRY(cpu_feroceon_do_idle)
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
* Clean and invalidate all cache entries in a particular
* address space.
*/
* Clean and invalidate all cache entries in a particular
* address space.
*/
ENTRY(feroceon_flush_user_cache_all)
/* FALLTHROUGH */
ENTRY(feroceon_flush_user_cache_all)
/* FALLTHROUGH */
* - end - end address (exclusive)
* - flags - vm_flags describing address space
*/
* - end - end address (exclusive)
* - flags - vm_flags describing address space
*/
ENTRY(feroceon_flush_user_cache_range)
mov ip, #0
sub r3, r1, r0 @ calculate total size
ENTRY(feroceon_flush_user_cache_range)
mov ip, #0
sub r3, r1, r0 @ calculate total size
* - start - virtual start address
* - end - virtual end address
*/
* - start - virtual start address
* - end - virtual end address
*/
ENTRY(feroceon_coherent_kern_range)
/* FALLTHROUGH */
ENTRY(feroceon_coherent_kern_range)
/* FALLTHROUGH */
*
* - addr - page aligned address
*/
*
* - addr - page aligned address
*/
ENTRY(feroceon_flush_kern_dcache_page)
add r1, r0, #PAGE_SZ
1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
ENTRY(feroceon_flush_kern_dcache_page)
add r1, r0, #PAGE_SZ
1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
ENTRY(feroceon_dma_inv_range)
tst r0, #CACHE_DLINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
ENTRY(feroceon_dma_inv_range)
tst r0, #CACHE_DLINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
ENTRY(feroceon_dma_clean_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
ENTRY(feroceon_dma_clean_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
* - start - virtual start address
* - end - virtual end address
*/
* - start - virtual start address
* - end - virtual end address
*/
ENTRY(feroceon_dma_flush_range)
bic r0, r0, #CACHE_DLINESIZE - 1
ENTRY(feroceon_dma_flush_range)
bic r0, r0, #CACHE_DLINESIZE - 1
-1:
- mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
+1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
.long feroceon_dma_clean_range
.long feroceon_dma_flush_range
.long feroceon_dma_clean_range
.long feroceon_dma_flush_range
ENTRY(cpu_feroceon_dcache_clean_area)
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #CACHE_DLINESIZE
ENTRY(cpu_feroceon_dcache_clean_area)
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #CACHE_DLINESIZE