The read[bwl] and write[bwl] functions are meant for accessing PCI
devices. How this is achieved on AVR32 is unknown, as there are no
systems with a PCI bridge available yet.
On-chip peripheral access, however, should not depend on how we end
up implementing PCI access, so using __raw_read[bwl]/__raw_write[bwl]
is the right thing to do for on-chip peripherals. This patch converts
the drivers for the static memory controller, interrupt controller,
PIO controller and system manager to use __raw MMIO access.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
/* Register access macros */
#define hsmc_readl(port,reg) \
/* Register access macros */
#define hsmc_readl(port,reg) \
- readl((port)->regs + HSMC_##reg)
+ __raw_readl((port)->regs + HSMC_##reg)
#define hsmc_writel(port,reg,value) \
#define hsmc_writel(port,reg,value) \
- writel((value), (port)->regs + HSMC_##reg)
+ __raw_writel((value), (port)->regs + HSMC_##reg)
#endif /* __ASM_AVR32_HSMC_H__ */
#endif /* __ASM_AVR32_HSMC_H__ */
#define INTC_MKBF(name, value) (((value) & ((1 << INTC_##name##_SIZE) - 1)) << INTC_##name##_OFFSET)
#define INTC_GETBF(name, value) (((value) >> INTC_##name##_OFFSET) & ((1 << INTC_##name##_SIZE) - 1))
#define INTC_MKBF(name, value) (((value) & ((1 << INTC_##name##_SIZE) - 1)) << INTC_##name##_OFFSET)
#define INTC_GETBF(name, value) (((value) >> INTC_##name##_OFFSET) & ((1 << INTC_##name##_SIZE) - 1))
-#define intc_readl(port,reg) readl((port)->regs + INTC_##reg)
-#define intc_writel(port,reg,value) writel((value), (port)->regs + INTC_##reg)
+#define intc_readl(port,reg) \
+ __raw_readl((port)->regs + INTC_##reg)
+#define intc_writel(port,reg,value) \
+ __raw_writel((value), (port)->regs + INTC_##reg)
#endif /* __ASM_AVR32_PERIHP_INTC_H__ */
#endif /* __ASM_AVR32_PERIHP_INTC_H__ */
#define PIO_BFINS(name,value,old) (((old) & ~(((1 << PIO_##name##_SIZE) - 1) << PIO_##name##_OFFSET)) | PIO_BF(name,value))
/* Register access macros */
#define PIO_BFINS(name,value,old) (((old) & ~(((1 << PIO_##name##_SIZE) - 1) << PIO_##name##_OFFSET)) | PIO_BF(name,value))
/* Register access macros */
-#define pio_readl(port,reg) readl((port)->regs + PIO_##reg)
-#define pio_writel(port,reg,value) writel((value), (port)->regs + PIO_##reg)
+#define pio_readl(port,reg) \
+ __raw_readl((port)->regs + PIO_##reg)
+#define pio_writel(port,reg,value) \
+ __raw_writel((value), (port)->regs + PIO_##reg)
void at32_init_pio(struct platform_device *pdev);
void at32_init_pio(struct platform_device *pdev);
#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value))
/* Register access macros */
#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value))
/* Register access macros */
-#define sm_readl(port,reg) readl((port)->regs + SM_##reg)
-#define sm_writel(port,reg,value) writel((value), (port)->regs + SM_##reg)
+#define sm_readl(port,reg) \
+ __raw_readl((port)->regs + SM_##reg)
+#define sm_writel(port,reg,value) \
+ __raw_writel((value), (port)->regs + SM_##reg)
#endif /* __ASM_AVR32_SM_H__ */
#endif /* __ASM_AVR32_SM_H__ */