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ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size
authorKirill A. Shutemov <kirill@shutemov.name>
Tue, 15 Sep 2009 09:23:53 +0000 (10:23 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Tue, 15 Sep 2009 21:06:38 +0000 (22:06 +0100)
commit910a17e57ab6cd22b300bde4ce5f633f175c7ccd
tree2a1dea95ca2d50192216500d90d9b0358af1dc1dtree | snapshot
parent59fcf48fdebe65e4774d2c7ec76b7845d281749acommit | diff
ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size

Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
It's not true at least for CPUs based on Cortex-A8.

List of CPUs with cache line size != 32 should be expanded later.

Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/include/asm/cache.h diff | blob | history
arch/arm/mm/Kconfig diff | blob | history
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