[MIPS] Malta: Fix reading the PCI clock frequency on big-endian
authorDmitri Vorobiev <dmitri.vorobiev@gmail.com>
Mon, 14 Jan 2008 21:27:46 +0000 (00:27 +0300)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 22 Jan 2008 00:35:23 +0000 (00:35 +0000)
commit0487de91427925e7c43debeb948bdf53b10ef32c
treee911ecd1291b7ac0c7fe85d1a28102a07e150f21
parentc2a04c4f0e1b09b58d7279e2facd306c40583ec1
[MIPS] Malta: Fix reading the PCI clock frequency on big-endian

The JMPRS register on Malta boards keeps a 32-bit CPU-endian
value. The readw() function assumes that the value it reads is a
little-endian 16-bit number. Therefore, using readw() to obtain
the value of the JMPRS register is a mistake. This error leads
to incorrect reading of the PCI clock frequency on big-endian
during board start-up.

Change readw() to __raw_readl().

This was tested by injecting a call to printk() and verifying
that the value of the jmpr variable was consistent with current
setting of the JP4 "PCI CLK" jumper.

Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mips-boards/malta/malta_setup.c