X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=include%2Fsound%2Femu10k1.h;h=10ee28eac018535da6f1e706b9c6189f90d46230;hb=76a67ec6fb79ff3570dcb5342142c16098299911;hp=396812eb668d063f5df73e49d61e2508cedfaffe;hpb=9f4bd5dde81b5cb94e4f52f2f05825aa0422f1ff;p=safe%2Fjmp%2Flinux-2.6 diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h index 396812e..10ee28e 100644 --- a/include/sound/emu10k1.h +++ b/include/sound/emu10k1.h @@ -2,7 +2,7 @@ #define __SOUND_EMU10K1_H /* - * Copyright (c) by Jaroslav Kysela , + * Copyright (c) by Jaroslav Kysela , * Creative Labs, Inc. * Definitions for EMU10K1 (SB Live!) chips * @@ -460,6 +460,7 @@ #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */ #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */ +#define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */ #define MAPA 0x0c /* Cache map A */ #define MAPB 0x0d /* Cache map B */ @@ -467,6 +468,8 @@ #define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */ #define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */ +/* 0x0e, 0x0f: Not used */ + #define ENVVOL 0x10 /* Volume envelope register */ #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ /* 0x8000-n == 666*n usec delay */ @@ -555,7 +558,7 @@ /* NOTE: All channels contain internal variables; do */ /* not write to these locations. */ -/* 1f something */ +/* 0x1f: not used */ #define CD0 0x20 /* Cache data 0 register */ #define CD1 0x21 /* Cache data 1 register */ @@ -625,6 +628,8 @@ #define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */ #define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */ +#define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */ + #define TCBS 0x44 /* Tank cache buffer size register */ #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */ #define TCBS_BUFFSIZE_16K 0x00000000 @@ -645,7 +650,7 @@ #define FXBA 0x47 /* FX Buffer Address */ #define FXBA_MASK 0xfffff000 /* 20 bit base address */ -/* 0x48 something - word access, defaults to 3f */ +#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */ #define MICBS 0x49 /* Microphone buffer size register */ @@ -689,6 +694,18 @@ #define ADCBS_BUFSIZE_57344 0x0000001e #define ADCBS_BUFSIZE_65536 0x0000001f +/* Current Send B, A Amounts */ +#define A_CSBA 0x4c + +/* Current Send D, C Amounts */ +#define A_CSDC 0x4d + +/* Current Send F, E Amounts */ +#define A_CSFE 0x4e + +/* Current Send H, G Amounts */ +#define A_CSHG 0x4f + #define CDCS 0x50 /* CD-ROM digital channel status register */ @@ -696,6 +713,9 @@ #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ +/* S/PDIF Input C Channel Status */ +#define A_SPSC 0x52 + #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ #define A_DBG 0x53 @@ -736,6 +756,8 @@ #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */ #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */ +/* 0x57: Not used */ + /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */ #define CLIEL 0x58 /* Channel loop interrupt enable low register */ @@ -761,6 +783,9 @@ #define AC97SLOT_CNTR 0x10 /* Center enable */ #define AC97SLOT_LFE 0x20 /* LFE enable */ +/* PCB Revision */ +#define A_PCB 0x5f + // NOTE: 0x60,61,62: 64-bit #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */ @@ -808,9 +833,18 @@ #define HLIPH 0x69 /* Channel half loop interrupt pending high register */ -// 0x6a,6b,6c used for some recording -// 0x6d unused -// 0x6e,6f - tanktable base / offset +/* S/PDIF Host Record Index (bypasses SRC) */ +#define A_SPRI 0x6a +/* S/PDIF Host Record Address */ +#define A_SPRA 0x6b +/* S/PDIF Host Record Control */ +#define A_SPRC 0x6c +/* Delayed Interrupt Counter & Enable */ +#define A_DICE 0x6d +/* Tank Table Base */ +#define A_TTB 0x6e +/* Tank Delay Offset */ +#define A_TDOF 0x6f /* This is the MPU port on the card (via the game port) */ #define A_MUDATA1 0x70 @@ -828,6 +862,7 @@ #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */ #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */ +/* Extended Hardware Control */ #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */ #define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */ #define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */ @@ -850,8 +885,20 @@ #define A_PCM_96000 0x00004000 #define A_PCM_44100 0x00008000 -/* 0x77,0x78,0x79 "something i2s-related" - default to 0x01080000 on my audigy 2 ZS --rlrevell */ -/* 0x7a, 0x7b - lookup tables */ +/* I2S0 Sample Rate Tracker Status */ +#define A_SRT3 0x77 + +/* I2S1 Sample Rate Tracker Status */ +#define A_SRT4 0x78 + +/* I2S2 Sample Rate Tracker Status */ +#define A_SRT5 0x79 +/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */ + +/* Tank Table DMA Address */ +#define A_TTDA 0x7a +/* Tank Table DMA Data */ +#define A_TTDD 0x7b #define A_FXRT2 0x7c #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */ @@ -873,7 +920,7 @@ #define A_FXRT_CHANNELC 0x003f0000 #define A_FXRT_CHANNELD 0x3f000000 - +/* 0x7f: Not used */ /* Each FX general purpose register is 32 bits in length, all bits are used */ #define FXGPREGBASE 0x100 /* FX general purpose registers base */ #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */ @@ -974,7 +1021,7 @@ #define EMU_HANA_OPTICAL_OUT_SPDIF 0x00 #define EMU_HANA_OPTICAL_OUT_ADAT 0x02 -#define EMU_HANA_MIDI 0x0c /* 000000x 1 bit Control MIDI */ +#define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */ #define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */ #define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */ @@ -1000,10 +1047,11 @@ #define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */ #define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */ -#define EMU_HANA_DOCK_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */ -#define EMU_HANA_DOCK_PAD1 0x01 /* 14dB Attenuation on ADC 1 */ -#define EMU_HANA_DOCK_PAD2 0x02 /* 14dB Attenuation on ADC 2 */ -#define EMU_HANA_DOCK_PAD3 0x04 /* 14dB Attenuation on ADC 3 */ +#define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */ +#define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */ +#define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */ +#define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */ +#define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */ #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */ #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */ @@ -1015,8 +1063,20 @@ #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */ #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */ -#define EMU_HANA_UNKNOWN12 0x12 /* 0xxxxxx 6 bit Unknown12 */ -#define EMU_HANA_UNKNOWN13 0x13 /* 0xxxxxx 6 bit Unknown13 */ +#define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */ +#define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */ + +#define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */ +#define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */ +#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */ + /* 0x14 - 0x1f Unused R/W registers */ #define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */ #if 0 /* Already defined for reg 0x09 IRQ_ENABLE */ @@ -1060,6 +1120,109 @@ /************************************************************************************************/ /* EMU1010m HANA Destinations */ /************************************************************************************************/ +/* Hana, original 1010,1212,1820 using Alice2 + * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 + * 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock + * 0x01, 0x00: Dock DAC 1 Left + * 0x01, 0x04: Dock DAC 1 Right + * 0x01, 0x08: Dock DAC 2 Left + * 0x01, 0x0c: Dock DAC 2 Right + * 0x01, 0x10: Dock DAC 3 Left + * 0x01, 0x12: PHONES Left + * 0x01, 0x14: Dock DAC 3 Right + * 0x01, 0x16: PHONES Right + * 0x01, 0x18: Dock DAC 4 Left + * 0x01, 0x1a: S/PDIF Left + * 0x01, 0x1c: Dock DAC 4 Right + * 0x01, 0x1e: S/PDIF Right + * 0x02, 0x00: Hana S/PDIF Left + * 0x02, 0x01: Hana S/PDIF Right + * 0x03, 0x00: Hanoa DAC Left + * 0x03, 0x01: Hanoa DAC Right + * 0x04, 0x00-0x07: Hana ADAT + * 0x05, 0x00: I2S0 Left to Alice2 + * 0x05, 0x01: I2S0 Right to Alice2 + * 0x06, 0x00: I2S0 Left to Alice2 + * 0x06, 0x01: I2S0 Right to Alice2 + * 0x07, 0x00: I2S0 Left to Alice2 + * 0x07, 0x01: I2S0 Right to Alice2 + * + * Hana2 never released, but used Tina + * Not needed. + * + * Hana3, rev2 1010,1212,1616 using Tina + * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina + * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock + * 0x01, 0x00: Dock DAC 1 Left + * 0x01, 0x04: Dock DAC 1 Right + * 0x01, 0x08: Dock DAC 2 Left + * 0x01, 0x0c: Dock DAC 2 Right + * 0x01, 0x10: Dock DAC 3 Left + * 0x01, 0x12: Dock S/PDIF Left + * 0x01, 0x14: Dock DAC 3 Right + * 0x01, 0x16: Dock S/PDIF Right + * 0x01, 0x18-0x1f: Dock ADAT 0-7 + * 0x02, 0x00: Hana3 S/PDIF Left + * 0x02, 0x01: Hana3 S/PDIF Right + * 0x03, 0x00: Hanoa DAC Left + * 0x03, 0x01: Hanoa DAC Right + * 0x04, 0x00-0x07: Hana3 ADAT 0-7 + * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina + * 0x06-0x07: Not used + * + * HanaLite, rev1 0404 using Alice2 + * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 + * 0x01: Not used + * 0x02, 0x00: S/PDIF Left + * 0x02, 0x01: S/PDIF Right + * 0x03, 0x00: DAC Left + * 0x03, 0x01: DAC Right + * 0x04-0x07: Not used + * + * HanaLiteLite, rev2 0404 using Alice2 + * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 + * 0x01: Not used + * 0x02, 0x00: S/PDIF Left + * 0x02, 0x01: S/PDIF Right + * 0x03, 0x00: DAC Left + * 0x03, 0x01: DAC Right + * 0x04-0x07: Not used + * + * Mana, Cardbus 1616 using Tina2 + * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2 + * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock + * 0x01, 0x00: Dock DAC 1 Left + * 0x01, 0x04: Dock DAC 1 Right + * 0x01, 0x08: Dock DAC 2 Left + * 0x01, 0x0c: Dock DAC 2 Right + * 0x01, 0x10: Dock DAC 3 Left + * 0x01, 0x12: Dock S/PDIF Left + * 0x01, 0x14: Dock DAC 3 Right + * 0x01, 0x16: Dock S/PDIF Right + * 0x01, 0x18-0x1f: Dock ADAT 0-7 + * 0x02: Not used + * 0x03, 0x00: Mana DAC Left + * 0x03, 0x01: Mana DAC Right + * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2 + * 0x05-0x07: Not used + * + * + */ +/* 32-bit destinations of signal in the Hana FPGA. Destinations are either + * physical outputs of Hana, or outputs going to Alice2 (audigy) for capture + * - 16 x EMU_DST_ALICE2_EMU32_X. + */ +/* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */ +/* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture. + * Which data is fed into a EMU_DST_ALICE2_EMU32_X channel in Hana depends on + * setup of mixer control for each destination - see emumixer.c - + * snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[] + */ #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */ #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */ #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */ @@ -1136,9 +1299,128 @@ #define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */ #define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */ +/* Additional destinations for 1616(M)/Microdock */ +/* Microdock S/PDIF OUT Left, 1st or 48kHz only */ +#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 +/* Microdock S/PDIF OUT Left, 2nd or 96kHz */ +#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 +/* Microdock S/PDIF OUT Right, 1st or 48kHz only */ +#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 +/* Microdock S/PDIF OUT Right, 2nd or 96kHz */ +#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 +/* Microdock S/PDIF ADAT 8 channel out +8 to +f */ +#define EMU_DST_MDOCK_ADAT 0x0118 + +/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ +#define EMU_DST_MANA_DAC_LEFT 0x0300 +/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ +#define EMU_DST_MANA_DAC_RIGHT 0x0301 + /************************************************************************************************/ /* EMU1010m HANA Sources */ /************************************************************************************************/ +/* Hana, original 1010,1212,1820 using Alice2 + * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00,0x00-0x1f: Silence + * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock + * 0x01, 0x00: Dock Mic A + * 0x01, 0x04: Dock Mic B + * 0x01, 0x08: Dock ADC 1 Left + * 0x01, 0x0c: Dock ADC 1 Right + * 0x01, 0x10: Dock ADC 2 Left + * 0x01, 0x14: Dock ADC 2 Right + * 0x01, 0x18: Dock ADC 3 Left + * 0x01, 0x1c: Dock ADC 3 Right + * 0x02, 0x00: Hana ADC Left + * 0x02, 0x01: Hana ADC Right + * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output + * 0x04, 0x00-0x07: Hana ADAT + * 0x05, 0x00: Hana S/PDIF Left + * 0x05, 0x01: Hana S/PDIF Right + * 0x06-0x07: Not used + * + * Hana2 never released, but used Tina + * Not needed. + * + * Hana3, rev2 1010,1212,1616 using Tina + * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00,0x00-0x1f: Silence + * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock + * 0x01, 0x00: Dock Mic A + * 0x01, 0x04: Dock Mic B + * 0x01, 0x08: Dock ADC 1 Left + * 0x01, 0x0c: Dock ADC 1 Right + * 0x01, 0x10: Dock ADC 2 Left + * 0x01, 0x12: Dock S/PDIF Left + * 0x01, 0x14: Dock ADC 2 Right + * 0x01, 0x16: Dock S/PDIF Right + * 0x01, 0x18-0x1f: Dock ADAT 0-7 + * 0x01, 0x18: Dock ADC 3 Left + * 0x01, 0x1c: Dock ADC 3 Right + * 0x02, 0x00: Hanoa ADC Left + * 0x02, 0x01: Hanoa ADC Right + * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output + * 0x04, 0x00-0x07: Hana3 ADAT + * 0x05, 0x00: Hana3 S/PDIF Left + * 0x05, 0x01: Hana3 S/PDIF Right + * 0x06-0x07: Not used + * + * HanaLite, rev1 0404 using Alice2 + * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00,0x00-0x1f: Silence + * 0x01: Not used + * 0x02, 0x00: ADC Left + * 0x02, 0x01: ADC Right + * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output + * 0x04: Not used + * 0x05, 0x00: S/PDIF Left + * 0x05, 0x01: S/PDIF Right + * 0x06-0x07: Not used + * + * HanaLiteLite, rev2 0404 using Alice2 + * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00,0x00-0x1f: Silence + * 0x01: Not used + * 0x02, 0x00: ADC Left + * 0x02, 0x01: ADC Right + * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output + * 0x04: Not used + * 0x05, 0x00: S/PDIF Left + * 0x05, 0x01: S/PDIF Right + * 0x06-0x07: Not used + * + * Mana, Cardbus 1616 using Tina2 + * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00,0x00-0x1f: Silence + * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock + * 0x01, 0x00: Dock Mic A + * 0x01, 0x04: Dock Mic B + * 0x01, 0x08: Dock ADC 1 Left + * 0x01, 0x0c: Dock ADC 1 Right + * 0x01, 0x10: Dock ADC 2 Left + * 0x01, 0x12: Dock S/PDIF Left + * 0x01, 0x14: Dock ADC 2 Right + * 0x01, 0x16: Dock S/PDIF Right + * 0x01, 0x18-0x1f: Dock ADAT 0-7 + * 0x01, 0x18: Dock ADC 3 Left + * 0x01, 0x1c: Dock ADC 3 Right + * 0x02: Not used + * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output + * 0x04-0x07: Not used + * + */ + +/* 32-bit sources of signal in the Hana FPGA. The sources are routed to + * destinations using mixer control for each destination - see emumixer.c + * Sources are either physical inputs of FPGA, + * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A + + * 16 x EMU_SRC_ALICE_EMU32B + */ #define EMU_SRC_SILENCE 0x0000 /* Silence */ #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */ #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */ @@ -1187,6 +1469,19 @@ #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */ #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */ #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */ + +/* Additional inputs for 1616(M)/Microdock */ +/* Microdock S/PDIF Left, 1st or 48kHz only */ +#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 +/* Microdock S/PDIF Left, 2nd or 96kHz */ +#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 +/* Microdock S/PDIF Right, 1st or 48kHz only */ +#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 +/* Microdock S/PDIF Right, 2nd or 96kHz */ +#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 +/* Microdock ADAT 8 channel in +8 to +f */ +#define EMU_SRC_MDOCK_ADAT 0x0118 + /* 0x600 and 0x700 no used */ /* ------------------- STRUCTURES -------------------- */ @@ -1332,8 +1627,6 @@ struct snd_emu10k1_fx8010 { struct snd_emu10k1_fx8010_irq *irq_handlers; }; -#define emu10k1_gpr_ctl(n) list_entry(n, struct snd_emu10k1_fx8010_ctl, list) - struct snd_emu10k1_midi { struct snd_emu10k1 *emu; struct snd_rawmidi *rmidi; @@ -1349,6 +1642,14 @@ struct snd_emu10k1_midi { void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status); }; +enum { + EMU_MODEL_SB, + EMU_MODEL_EMU1010, + EMU_MODEL_EMU1010B, + EMU_MODEL_EMU1616, + EMU_MODEL_EMU0404, +}; + struct snd_emu_chip_details { u32 vendor; u32 device; @@ -1365,10 +1666,11 @@ struct snd_emu_chip_details { unsigned char spdif_bug; /* Has Spdif phasing bug */ unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ unsigned char ecard; /* APS EEPROM */ - unsigned char emu1010; /* EMU 1010m card */ + unsigned char emu_model; /* EMU model type */ unsigned char spi_dac; /* SPI interface for DAC */ unsigned char i2c_adc; /* I2C interface for ADC */ unsigned char adc_1361t; /* Use Philips 1361T ADC */ + unsigned char invert_shared_spdif; /* analog/digital switch inverted */ const char *driver; const char *name; const char *id; /* for backward compatibility - can be NULL if not needed */ @@ -1377,6 +1679,12 @@ struct snd_emu_chip_details { struct snd_emu1010 { unsigned int output_source[64]; unsigned int input_source[64]; + unsigned int adc_pads; /* bit mask */ + unsigned int dac_pads; /* bit mask */ + unsigned int internal_clock; /* 44100 or 48000 */ + unsigned int optical_in; /* 0:SPDIF, 1:ADAT */ + unsigned int optical_out; /* 0:SPDIF, 1:ADAT */ + struct task_struct *firmware_thread; }; struct snd_emu10k1 { @@ -1386,6 +1694,7 @@ struct snd_emu10k1 { unsigned int tos_link: 1, /* tos link detected */ rear_ac97: 1, /* rear channels are on AC'97 */ enable_ir: 1; + unsigned int support_tlv :1; /* Contains profile of card capabilities */ const struct snd_emu_chip_details *card_capabilities; unsigned int audigy; /* is Audigy? */ @@ -1411,6 +1720,8 @@ struct snd_emu10k1 { spinlock_t memblk_lock; unsigned int spdif_bits[3]; /* s/pdif out setup */ + unsigned int i2c_capture_source; + u8 i2c_capture_volume[4][2]; struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */ int gpr_base; @@ -1432,6 +1743,8 @@ struct snd_emu10k1 { spinlock_t reg_lock; spinlock_t emu_lock; spinlock_t voice_lock; + spinlock_t spi_lock; /* serialises access to spi port */ + spinlock_t i2c_lock; /* serialises access to i2c port */ struct snd_emu10k1_voice voices[NUM_G]; struct snd_emu10k1_voice p16v_voices[4]; @@ -1516,9 +1829,10 @@ void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned i unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data); -int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, int reg, int value); -int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, int reg, int *value); -int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, int dst, int src); +int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value); +int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value); +int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value); +int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src); unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc); void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb); void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb); @@ -1663,6 +1977,8 @@ int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */ #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */ #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */ +#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */ +#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */ #define A_GPR(x) (A_FXGPREGBASE + (x)) /* cc_reg constants */ @@ -1835,11 +2151,20 @@ struct snd_emu10k1_fx8010_control_gpr { unsigned int value[32]; /* initial values */ unsigned int min; /* minimum range */ unsigned int max; /* maximum range */ - union { - snd_kcontrol_tlv_rw_t *c; - unsigned int *p; - } tlv; unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ + const unsigned int *tlv; +}; + +/* old ABI without TLV support */ +struct snd_emu10k1_fx8010_control_old_gpr { + struct snd_ctl_elem_id id; + unsigned int vcount; + unsigned int count; + unsigned short gpr[32]; + unsigned int value[32]; + unsigned int min; + unsigned int max; + unsigned int translation; }; struct snd_emu10k1_fx8010_code { @@ -1890,6 +2215,8 @@ struct snd_emu10k1_fx8010_pcm_rec { unsigned int res2; /* reserved */ }; +#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) + #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info) #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code) #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code) @@ -1898,6 +2225,7 @@ struct snd_emu10k1_fx8010_pcm_rec { #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram) #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec) #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec) +#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int) #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80) #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81) #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)