X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=include%2Fasm-ia64%2Fpci.h;h=0149097b736d70bd5e4d2f73801b5805ffe8a88a;hb=3e0879deb700f322f6c81ab34f056fc72d15ec02;hp=1cbd10b96b3ab37862fc4cc889b827d4209ed24e;hpb=c9c3e457de24cca2ca688fa397d93a241f472048;p=safe%2Fjmp%2Flinux-2.6 diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h index 1cbd10b..0149097 100644 --- a/include/asm-ia64/pci.h +++ b/include/asm-ia64/pci.h @@ -9,6 +9,7 @@ #include #include +#include /* * Can be used to override the logic in pci_scan_bus for skipping already-configured bus @@ -26,16 +27,18 @@ void pcibios_config_init(void); struct pci_dev; /* - * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct correspondence - * between device bus addresses and CPU physical addresses. Platforms with a hardware I/O - * MMU _must_ turn this off to suppress the bounce buffer handling code in the block and - * network device layers. Platforms with separate bus address spaces _must_ turn this off - * and provide a device DMA mapping implementation that takes care of the necessary + * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct + * correspondence between device bus addresses and CPU physical addresses. + * Platforms with a hardware I/O MMU _must_ turn this off to suppress the + * bounce buffer handling code in the block and network device layers. + * Platforms with separate bus address spaces _must_ turn this off and provide + * a device DMA mapping implementation that takes care of the necessary * address translation. * - * For now, the ia64 platforms which may have separate/multiple bus address spaces all - * have I/O MMUs which support the merging of physically discontiguous buffers, so we can - * use that as the sole factor to determine the setting of PCI_DMA_BUS_IS_PHYS. + * For now, the ia64 platforms which may have separate/multiple bus address + * spaces all have I/O MMUs which support the merging of physically + * discontiguous buffers, so we can use that as the sole factor to determine + * the setting of PCI_DMA_BUS_IS_PHYS. */ extern unsigned long ia64_max_iommu_merge_mask; #define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL) @@ -52,9 +55,6 @@ pcibios_penalize_isa_irq (int irq, int active) /* We don't do dynamic PCI IRQ allocation */ } -#define HAVE_ARCH_PCI_MWI 1 -extern int pcibios_prep_mwi (struct pci_dev *); - #include /* pci_unmap_{single,page} is not a nop, thus... */ @@ -71,16 +71,24 @@ extern int pcibios_prep_mwi (struct pci_dev *); #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ (((PTR)->LEN_NAME) = (VAL)) -/* The ia64 platform always supports 64-bit addressing. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) -#define pci_dac_page_to_dma(dev,pg,off,dir) ((dma_addr_t) page_to_bus(pg) + (off)) -#define pci_dac_dma_to_page(dev,dma_addr) (virt_to_page(bus_to_virt(dma_addr))) -#define pci_dac_dma_to_offset(dev,dma_addr) offset_in_page(dma_addr) -#define pci_dac_dma_sync_single_for_cpu(dev,dma_addr,len,dir) do { } while (0) -#define pci_dac_dma_sync_single_for_device(dev,dma_addr,len,dir) do { mb(); } while (0) +#ifdef CONFIG_PCI +static inline void pci_dma_burst_advice(struct pci_dev *pdev, + enum pci_dma_burst_strategy *strat, + unsigned long *strategy_parameter) +{ + unsigned long cacheline_size; + u8 byte; + + pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); + if (byte == 0) + cacheline_size = 1024; + else + cacheline_size = (int) byte * 4; -#define sg_dma_len(sg) ((sg)->dma_length) -#define sg_dma_address(sg) ((sg)->dma_address) + *strat = PCI_DMA_BURST_MULTIPLE; + *strategy_parameter = cacheline_size; +} +#endif #define HAVE_PCI_MMAP extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, @@ -88,10 +96,12 @@ extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, #define HAVE_PCI_LEGACY extern int pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma); -extern ssize_t pci_read_legacy_io(struct kobject *kobj, char *buf, loff_t off, - size_t count); -extern ssize_t pci_write_legacy_io(struct kobject *kobj, char *buf, loff_t off, - size_t count); +extern ssize_t pci_read_legacy_io(struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count); +extern ssize_t pci_write_legacy_io(struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count); extern int pci_mmap_legacy_mem(struct kobject *kobj, struct bin_attribute *attr, struct vm_area_struct *vma); @@ -109,6 +119,7 @@ struct pci_controller { void *acpi_handle; void *iommu; int segment; + int node; /* nearest node with memory or -1 for global allocation */ unsigned int windows; struct pci_window *window; @@ -126,16 +137,31 @@ static inline int pci_proc_domain(struct pci_bus *bus) return (pci_domain_nr(bus) != 0); } -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, struct pci_bus_region *region); +static inline struct resource * +pcibios_select_root(struct pci_dev *pdev, struct resource *res) +{ + struct resource *root = NULL; + + if (res->flags & IORESOURCE_IO) + root = &ioport_resource; + if (res->flags & IORESOURCE_MEM) + root = &iomem_resource; + + return root; +} + #define pcibios_scan_all_fns(a, b) 0 +#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ +static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) +{ + return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14); +} + #endif /* _ASM_IA64_PCI_H */