X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=drivers%2Fspi%2Fspi_bfin5xx.c;h=e706de1d10c840ee6d8730cd12eec15c3ee1704f;hb=aaaf939c573b783398b6af863576322256352f64;hp=d6e9812538c4f301192ea689375f0d6c40d09b45;hpb=003d922618150eaab53936f57ba8a61f2b601486;p=safe%2Fjmp%2Flinux-2.6 diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c index d6e9812..e706de1 100644 --- a/drivers/spi/spi_bfin5xx.c +++ b/drivers/spi/spi_bfin5xx.c @@ -1,37 +1,11 @@ /* - * File: drivers/spi/bfin5xx_spi.c - * Maintainer: - * Bryan Wu - * Original Author: - * Luke Yang (Analog Devices Inc.) - * - * Created: March. 10th 2006 - * Description: SPI controller driver for Blackfin BF5xx - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * Modified: - * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang) - * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang) - * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu) - * July 30, 2007 add platfrom_resource interface to support multi-port - * SPI controller (Bryan Wu) + * Blackfin On-Chip SPI Driver * * Copyright 2004-2007 Analog Devices Inc. * - * This program is free software ; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation ; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY ; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Enter bugs at http://blackfin.uclinux.org/ * - * You should have received a copy of the GNU General Public License - * along with this program ; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the GPL-2 or later. */ #include @@ -51,10 +25,11 @@ #include #include #include +#include #define DRV_NAME "bfin-spi" #define DRV_AUTHOR "Bryan Wu, Luke Yang" -#define DRV_DESC "Blackfin BF5xx on-chip SPI Contoller Driver" +#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver" #define DRV_VERSION "1.0" MODULE_AUTHOR(DRV_AUTHOR); @@ -180,6 +155,9 @@ static u16 hz_to_spi_baud(u32 speed_hz) if ((sclk % (2 * speed_hz)) > 0) spi_baud++; + if (spi_baud < MIN_SPI_BAUD_VAL) + spi_baud = MIN_SPI_BAUD_VAL; + return spi_baud; } @@ -220,13 +198,10 @@ static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip) udelay(chip->cs_chg_udelay); } -#define MAX_SPI_SSEL 7 - /* stop controller and re-config current chip*/ -static int restore_state(struct driver_data *drv_data) +static void restore_state(struct driver_data *drv_data) { struct chip_data *chip = drv_data->cur_chip; - int ret = 0; /* Clear status and disable clock */ write_STAT(drv_data, BIT_STAT_CLR); @@ -234,20 +209,11 @@ static int restore_state(struct driver_data *drv_data) dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); /* Load the registers */ - write_BAUD(drv_data, chip->baud); - chip->ctl_reg &= (~BIT_CTL_TIMOD); - chip->ctl_reg |= (chip->width << 8); write_CTRL(drv_data, chip->ctl_reg); + write_BAUD(drv_data, chip->baud); bfin_spi_enable(drv_data); cs_active(drv_data, chip); - - if (ret) - dev_dbg(&drv_data->pdev->dev, - ": request chip select number %d failed\n", - chip->chip_select_num); - - return ret; } /* used to kick off transfer in rx mode */ @@ -288,32 +254,30 @@ static void u8_writer(struct driver_data *drv_data) dev_dbg(&drv_data->pdev->dev, "cr8-s is 0x%x\n", read_STAT(drv_data)); - /* poll for SPI completion before start */ - while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) - cpu_relax(); - while (drv_data->tx < drv_data->tx_end) { write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); while (read_STAT(drv_data) & BIT_STAT_TXS) cpu_relax(); ++drv_data->tx; } + + /* poll for SPI completion before return */ + while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) + cpu_relax(); } static void u8_cs_chg_writer(struct driver_data *drv_data) { struct chip_data *chip = drv_data->cur_chip; - /* poll for SPI completion before start */ - while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) - cpu_relax(); - while (drv_data->tx < drv_data->tx_end) { cs_active(drv_data, chip); write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); while (read_STAT(drv_data) & BIT_STAT_TXS) cpu_relax(); + while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) + cpu_relax(); cs_deactive(drv_data, chip); @@ -352,43 +316,28 @@ static void u8_cs_chg_reader(struct driver_data *drv_data) { struct chip_data *chip = drv_data->cur_chip; - /* poll for SPI completion before start */ - while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) - cpu_relax(); - - /* clear TDBR buffer before read(else it will be shifted out) */ - write_TDBR(drv_data, 0xFFFF); + while (drv_data->rx < drv_data->rx_end) { + cs_active(drv_data, chip); + read_RDBR(drv_data); /* kick off */ - cs_active(drv_data, chip); - dummy_read(drv_data); + while (!(read_STAT(drv_data) & BIT_STAT_RXS)) + cpu_relax(); + while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) + cpu_relax(); - while (drv_data->rx < drv_data->rx_end - 1) { + *(u8 *) (drv_data->rx) = read_SHAW(drv_data); cs_deactive(drv_data, chip); - while (!(read_STAT(drv_data) & BIT_STAT_RXS)) - cpu_relax(); - cs_active(drv_data, chip); - *(u8 *) (drv_data->rx) = read_RDBR(drv_data); ++drv_data->rx; } - cs_deactive(drv_data, chip); - - while (!(read_STAT(drv_data) & BIT_STAT_RXS)) - cpu_relax(); - *(u8 *) (drv_data->rx) = read_SHAW(drv_data); - ++drv_data->rx; } static void u8_duplex(struct driver_data *drv_data) { - /* poll for SPI completion before start */ - while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) - cpu_relax(); - /* in duplex mode, clk is triggered by writing of TDBR */ while (drv_data->rx < drv_data->rx_end) { write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); - while (read_STAT(drv_data) & BIT_STAT_TXS) + while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) cpu_relax(); while (!(read_STAT(drv_data) & BIT_STAT_RXS)) cpu_relax(); @@ -402,15 +351,12 @@ static void u8_cs_chg_duplex(struct driver_data *drv_data) { struct chip_data *chip = drv_data->cur_chip; - /* poll for SPI completion before start */ - while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) - cpu_relax(); - while (drv_data->rx < drv_data->rx_end) { cs_active(drv_data, chip); write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); - while (read_STAT(drv_data) & BIT_STAT_TXS) + + while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) cpu_relax(); while (!(read_STAT(drv_data) & BIT_STAT_RXS)) cpu_relax(); @@ -428,32 +374,30 @@ static void u16_writer(struct driver_data *drv_data) dev_dbg(&drv_data->pdev->dev, "cr16 is 0x%x\n", read_STAT(drv_data)); - /* poll for SPI completion before start */ - while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) - cpu_relax(); - while (drv_data->tx < drv_data->tx_end) { write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); while ((read_STAT(drv_data) & BIT_STAT_TXS)) cpu_relax(); drv_data->tx += 2; } + + /* poll for SPI completion before return */ + while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) + cpu_relax(); } static void u16_cs_chg_writer(struct driver_data *drv_data) { struct chip_data *chip = drv_data->cur_chip; - /* poll for SPI completion before start */ - while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) - cpu_relax(); - while (drv_data->tx < drv_data->tx_end) { cs_active(drv_data, chip); write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); while ((read_STAT(drv_data) & BIT_STAT_TXS)) cpu_relax(); + while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) + cpu_relax(); cs_deactive(drv_data, chip); @@ -521,14 +465,10 @@ static void u16_cs_chg_reader(struct driver_data *drv_data) static void u16_duplex(struct driver_data *drv_data) { - /* poll for SPI completion before start */ - while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) - cpu_relax(); - /* in duplex mode, clk is triggered by writing of TDBR */ while (drv_data->tx < drv_data->tx_end) { write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); - while (read_STAT(drv_data) & BIT_STAT_TXS) + while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) cpu_relax(); while (!(read_STAT(drv_data) & BIT_STAT_RXS)) cpu_relax(); @@ -542,15 +482,11 @@ static void u16_cs_chg_duplex(struct driver_data *drv_data) { struct chip_data *chip = drv_data->cur_chip; - /* poll for SPI completion before start */ - while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) - cpu_relax(); - while (drv_data->tx < drv_data->tx_end) { cs_active(drv_data, chip); write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); - while (read_STAT(drv_data) & BIT_STAT_TXS) + while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) cpu_relax(); while (!(read_STAT(drv_data) & BIT_STAT_RXS)) cpu_relax(); @@ -618,11 +554,17 @@ static void giveback(struct driver_data *drv_data) static irqreturn_t dma_irq_handler(int irq, void *dev_id) { - struct driver_data *drv_data = (struct driver_data *)dev_id; + struct driver_data *drv_data = dev_id; struct chip_data *chip = drv_data->cur_chip; struct spi_message *msg = drv_data->cur_msg; + unsigned long timeout; + unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); + u16 spistat = read_STAT(drv_data); + + dev_dbg(&drv_data->pdev->dev, + "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", + dmastat, spistat); - dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n"); clear_dma_irqstat(drv_data->dma_channel); /* Wait for DMA to complete */ @@ -641,16 +583,30 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) cpu_relax(); } + dev_dbg(&drv_data->pdev->dev, + "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", + dmastat, read_STAT(drv_data)); + + timeout = jiffies + HZ; while (!(read_STAT(drv_data) & SPIF)) - cpu_relax(); + if (!time_before(jiffies, timeout)) { + dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); + break; + } else + cpu_relax(); - msg->actual_length += drv_data->len_in_bytes; + if ((dmastat & DMA_ERR) && (spistat & RBSY)) { + msg->state = ERROR_STATE; + dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); + } else { + msg->actual_length += drv_data->len_in_bytes; - if (drv_data->cs_change) - cs_deactive(drv_data, chip); + if (drv_data->cs_change) + cs_deactive(drv_data, chip); - /* Move to next transfer */ - msg->state = next_transfer(drv_data); + /* Move to next transfer */ + msg->state = next_transfer(drv_data); + } /* Schedule transfer tasklet */ tasklet_schedule(&drv_data->pump_transfers); @@ -674,17 +630,20 @@ static void pump_transfers(unsigned long data) u8 width; u16 cr, dma_width, dma_config; u32 tranf_success = 1; + u8 full_duplex = 0; /* Get current state information */ message = drv_data->cur_msg; transfer = drv_data->cur_transfer; chip = drv_data->cur_chip; + /* * if msg is error or done, report it back using complete() callback */ /* Handle for abort */ if (message->state == ERROR_STATE) { + dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); message->status = -EIO; giveback(drv_data); return; @@ -692,6 +651,7 @@ static void pump_transfers(unsigned long data) /* Handle end of message */ if (message->state == DONE_STATE) { + dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); message->status = 0; giveback(drv_data); return; @@ -699,6 +659,7 @@ static void pump_transfers(unsigned long data) /* Delay if requested at end of transfer */ if (message->state == RUNNING_STATE) { + dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); previous = list_entry(transfer->transfer_list.prev, struct spi_transfer, transfer_list); if (previous->delay_usecs) @@ -723,6 +684,7 @@ static void pump_transfers(unsigned long data) } if (transfer->rx_buf != NULL) { + full_duplex = transfer->tx_buf != NULL; drv_data->rx = transfer->rx_buf; drv_data->rx_end = drv_data->rx + transfer->len; dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", @@ -736,23 +698,62 @@ static void pump_transfers(unsigned long data) drv_data->len_in_bytes = transfer->len; drv_data->cs_change = transfer->cs_change; - width = chip->width; + /* Bits per word setup */ + switch (transfer->bits_per_word) { + case 8: + drv_data->n_bytes = 1; + width = CFG_SPI_WORDSIZE8; + drv_data->read = chip->cs_change_per_word ? + u8_cs_chg_reader : u8_reader; + drv_data->write = chip->cs_change_per_word ? + u8_cs_chg_writer : u8_writer; + drv_data->duplex = chip->cs_change_per_word ? + u8_cs_chg_duplex : u8_duplex; + break; + + case 16: + drv_data->n_bytes = 2; + width = CFG_SPI_WORDSIZE16; + drv_data->read = chip->cs_change_per_word ? + u16_cs_chg_reader : u16_reader; + drv_data->write = chip->cs_change_per_word ? + u16_cs_chg_writer : u16_writer; + drv_data->duplex = chip->cs_change_per_word ? + u16_cs_chg_duplex : u16_duplex; + break; + + default: + /* No change, the same as default setting */ + drv_data->n_bytes = chip->n_bytes; + width = chip->width; + drv_data->write = drv_data->tx ? chip->write : null_writer; + drv_data->read = drv_data->rx ? chip->read : null_reader; + drv_data->duplex = chip->duplex ? chip->duplex : null_writer; + break; + } + cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); + cr |= (width << 8); + write_CTRL(drv_data, cr); + if (width == CFG_SPI_WORDSIZE16) { drv_data->len = (transfer->len) >> 1; } else { drv_data->len = transfer->len; } - drv_data->write = drv_data->tx ? chip->write : null_writer; - drv_data->read = drv_data->rx ? chip->read : null_reader; - drv_data->duplex = chip->duplex ? chip->duplex : null_writer; - dev_dbg(&drv_data->pdev->dev, "transfer: ", - "drv_data->write is %p, chip->write is %p, null_wr is %p\n", + dev_dbg(&drv_data->pdev->dev, + "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n", drv_data->write, chip->write, null_writer); /* speed and width has been set on per message */ message->state = RUNNING_STATE; dma_config = 0; + /* Speed setup (surely valid because already checked) */ + if (transfer->speed_hz) + write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); + else + write_BAUD(drv_data, chip->baud); + write_STAT(drv_data, BIT_STAT_CLR); cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); cs_active(drv_data, chip); @@ -762,24 +763,26 @@ static void pump_transfers(unsigned long data) width, transfer->len); /* - * Try to map dma buffer and do a dma transfer if - * successful use different way to r/w according to - * drv_data->cur_chip->enable_dma + * Try to map dma buffer and do a dma transfer. If successful use, + * different way to r/w according to the enable_dma settings and if + * we are not doing a full duplex transfer (since the hardware does + * not support full duplex DMA transfers). */ - if (drv_data->cur_chip->enable_dma && drv_data->len > 6) { + if (!full_duplex && drv_data->cur_chip->enable_dma + && drv_data->len > 6) { + + unsigned long dma_start_addr, flags; disable_dma(drv_data->dma_channel); clear_dma_irqstat(drv_data->dma_channel); - bfin_spi_disable(drv_data); /* config dma channel */ dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); + set_dma_x_count(drv_data->dma_channel, drv_data->len); if (width == CFG_SPI_WORDSIZE16) { - set_dma_x_count(drv_data->dma_channel, drv_data->len); set_dma_x_modify(drv_data->dma_channel, 2); dma_width = WDSIZE_16; } else { - set_dma_x_count(drv_data->dma_channel, drv_data->len); set_dma_x_modify(drv_data->dma_channel, 1); dma_width = WDSIZE_8; } @@ -802,8 +805,7 @@ static void pump_transfers(unsigned long data) enable_dma(drv_data->dma_channel); /* start SPI transfer */ - write_CTRL(drv_data, - (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE)); + write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); /* just return here, there can only be one transfer * in this mode @@ -814,47 +816,62 @@ static void pump_transfers(unsigned long data) } /* In dma mode, rx or tx must be NULL in one transfer */ + dma_config = (RESTART | dma_width | DI_EN); if (drv_data->rx != NULL) { /* set transfer mode, and enable SPI */ - dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n"); + dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", + drv_data->rx, drv_data->len_in_bytes); + + /* invalidate caches, if needed */ + if (bfin_addr_dcachable((unsigned long) drv_data->rx)) + invalidate_dcache_range((unsigned long) drv_data->rx, + (unsigned long) (drv_data->rx + + drv_data->len_in_bytes)); /* clear tx reg soformer data is not shifted out */ write_TDBR(drv_data, 0xFFFF); - set_dma_x_count(drv_data->dma_channel, drv_data->len); - - /* start dma */ - dma_enable_irq(drv_data->dma_channel); - dma_config = (WNR | RESTART | dma_width | DI_EN); - set_dma_config(drv_data->dma_channel, dma_config); - set_dma_start_addr(drv_data->dma_channel, - (unsigned long)drv_data->rx); - enable_dma(drv_data->dma_channel); - - /* start SPI transfer */ - write_CTRL(drv_data, - (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE)); + dma_config |= WNR; + dma_start_addr = (unsigned long)drv_data->rx; + cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; } else if (drv_data->tx != NULL) { dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); - /* start dma */ - dma_enable_irq(drv_data->dma_channel); - dma_config = (RESTART | dma_width | DI_EN); - set_dma_config(drv_data->dma_channel, dma_config); - set_dma_start_addr(drv_data->dma_channel, - (unsigned long)drv_data->tx); - enable_dma(drv_data->dma_channel); + /* flush caches, if needed */ + if (bfin_addr_dcachable((unsigned long) drv_data->tx)) + flush_dcache_range((unsigned long) drv_data->tx, + (unsigned long) (drv_data->tx + + drv_data->len_in_bytes)); + + dma_start_addr = (unsigned long)drv_data->tx; + cr |= BIT_CTL_TIMOD_DMA_TX; + + } else + BUG(); + + /* oh man, here there be monsters ... and i dont mean the + * fluffy cute ones from pixar, i mean the kind that'll eat + * your data, kick your dog, and love it all. do *not* try + * and change these lines unless you (1) heavily test DMA + * with SPI flashes on a loaded system (e.g. ping floods), + * (2) know just how broken the DMA engine interaction with + * the SPI peripheral is, and (3) have someone else to blame + * when you screw it all up anyways. + */ + set_dma_start_addr(drv_data->dma_channel, dma_start_addr); + set_dma_config(drv_data->dma_channel, dma_config); + local_irq_save(flags); + enable_dma(drv_data->dma_channel); + write_CTRL(drv_data, cr); + dma_enable_irq(drv_data->dma_channel); + local_irq_restore(flags); - /* start SPI transfer */ - write_CTRL(drv_data, - (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE)); - } } else { /* IO mode write then read */ dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); - if (drv_data->tx != NULL && drv_data->rx != NULL) { + if (full_duplex) { /* full duplex mode */ BUG_ON((drv_data->tx_end - drv_data->tx) != (drv_data->rx_end - drv_data->rx)); @@ -899,7 +916,7 @@ static void pump_transfers(unsigned long data) message->state = ERROR_STATE; } else { /* Update total byte transfered */ - message->actual_length += drv_data->len; + message->actual_length += drv_data->len_in_bytes; /* Move to next transfer of this msg */ message->state = next_transfer(drv_data); @@ -940,10 +957,7 @@ static void pump_messages(struct work_struct *work) /* Setup the SSP using the per chip configuration */ drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); - if (restore_state(drv_data)) { - spin_unlock_irqrestore(&drv_data->lock, flags); - return; - }; + restore_state(drv_data); list_del_init(&drv_data->cur_msg->queue); @@ -1001,7 +1015,7 @@ static int transfer(struct spi_device *spi, struct spi_message *msg) #define MAX_SPI_SSEL 7 -static u16 ssel[3][MAX_SPI_SSEL] = { +static u16 ssel[][MAX_SPI_SSEL] = { {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, P_SPI0_SSEL4, P_SPI0_SSEL5, P_SPI0_SSEL6, P_SPI0_SSEL7}, @@ -1085,13 +1099,13 @@ static int setup(struct spi_device *spi) */ if (chip->enable_dma && !drv_data->dma_requested) { /* register dma irq handler */ - if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) { + if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) { dev_dbg(&spi->dev, "Unable to request BlackFin SPI DMA channel\n"); return -ENODEV; } if (set_dma_callback(drv_data->dma_channel, - (void *)dma_irq_handler, drv_data) < 0) { + dma_irq_handler, drv_data) < 0) { dev_dbg(&spi->dev, "Unable to set dma callback\n"); return -EPERM; } @@ -1149,7 +1163,7 @@ static int setup(struct spi_device *spi) if ((chip->chip_select_num > 0) && (chip->chip_select_num <= spi->master->num_chipselect)) peripheral_request(ssel[spi->master->bus_num] - [chip->chip_select_num-1], DRV_NAME); + [chip->chip_select_num-1], spi->modalias); cs_deactive(drv_data, chip); @@ -1186,8 +1200,8 @@ static inline int init_queue(struct driver_data *drv_data) /* init messages workqueue */ INIT_WORK(&drv_data->pump_messages, pump_messages); - drv_data->workqueue = - create_singlethread_workqueue(drv_data->master->dev.parent->bus_id); + drv_data->workqueue = create_singlethread_workqueue( + dev_name(drv_data->master->dev.parent)); if (drv_data->workqueue == NULL) return -EBUSY; @@ -1323,6 +1337,12 @@ static int __init bfin5xx_spi_probe(struct platform_device *pdev) goto out_error_queue_alloc; } + status = peripheral_request_list(drv_data->pin_req, DRV_NAME); + if (status != 0) { + dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); + goto out_error_queue_alloc; + } + /* Register with the SPI framework */ platform_set_drvdata(pdev, drv_data); status = spi_register_master(master); @@ -1331,12 +1351,6 @@ static int __init bfin5xx_spi_probe(struct platform_device *pdev) goto out_error_queue_alloc; } - status = peripheral_request_list(drv_data->pin_req, DRV_NAME); - if (status != 0) { - dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); - goto out_error; - } - dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", DRV_DESC, DRV_VERSION, drv_data->regs_base, drv_data->dma_channel); @@ -1348,7 +1362,6 @@ out_error_no_dma_ch: iounmap((void *) drv_data->regs_base); out_error_ioremap: out_error_get_res: -out_error: spi_master_put(master); return status; @@ -1426,7 +1439,7 @@ static int bfin5xx_spi_resume(struct platform_device *pdev) #define bfin5xx_spi_resume NULL #endif /* CONFIG_PM */ -MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */ +MODULE_ALIAS("platform:bfin-spi"); static struct platform_driver bfin5xx_spi_driver = { .driver = { .name = DRV_NAME,