X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=drivers%2Fscsi%2Fqla2xxx%2Fqla_fw.h;h=25364b1aaf12327daf2dac3e1ea34ce8286f147d;hb=71c222dc45ddf01b0dabb8a4d3e232e13e1452b5;hp=bebc32eb58698c6aebe1a79820460a05263da823;hpb=fa2a1ce53d4b869b74da9a770770c79f9af64914;p=safe%2Fjmp%2Flinux-2.6 diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h index bebc32e..25364b1 100644 --- a/drivers/scsi/qla2xxx/qla_fw.h +++ b/drivers/scsi/qla2xxx/qla_fw.h @@ -1,36 +1,24 @@ - -/******************************************************************************** -* QLOGIC LINUX SOFTWARE -* -* QLogic ISP2x00 device driver for Linux 2.6.x -* Copyright (C) 2003-2004 QLogic Corporation -* (www.qlogic.com) -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2, or (at your option) any -* later version. -* -* This program is distributed in the hope that it will be useful, but -* WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -* General Public License for more details. -** -******************************************************************************/ - +/* + * QLogic Fibre Channel HBA Driver + * Copyright (c) 2003-2005 QLogic Corporation + * + * See LICENSE.qla2xxx for copyright and licensing details. + */ #ifndef __QLA_FW_H #define __QLA_FW_H -#define RISC_SADDRESS 0x100000 #define MBS_CHECKSUM_ERROR 0x4010 +#define MBS_INVALID_PRODUCT_KEY 0x4020 /* * Firmware Options. */ #define FO1_ENABLE_PUREX BIT_10 #define FO1_DISABLE_LED_CTRL BIT_6 +#define FO1_ENABLE_8016 BIT_0 #define FO2_ENABLE_SEL_CLASS2 BIT_5 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14 +#define FO3_HOLD_STS_IOCB BIT_12 /* * Port Database structure definition for ISP 24xx. @@ -84,6 +72,16 @@ struct port_database_24xx { uint8_t reserved_3[24]; }; +struct vp_database_24xx { + uint16_t vp_status; + uint8_t options; + uint8_t id; + uint8_t port_name[WWN_SIZE]; + uint8_t node_name[WWN_SIZE]; + uint16_t port_id_low; + uint16_t port_id_high; +}; + struct nvram_24xx { /* NVRAM header. */ uint8_t id[4]; @@ -156,7 +154,7 @@ struct nvram_24xx { * BIT 2 = Enable Memory Map BIOS * BIT 3 = Enable Selectable Boot * BIT 4 = Disable RISC code load - * BIT 5 = + * BIT 5 = Disable Serdes * BIT 6 = * BIT 7 = * @@ -293,7 +291,7 @@ struct init_cb_24xx { uint16_t response_q_length; uint16_t request_q_length; - uint16_t link_down_timeout; /* Milliseconds. */ + uint16_t link_down_on_nos; /* Milliseconds. */ uint16_t prio_request_q_length; @@ -346,7 +344,9 @@ struct init_cb_24xx { * BIT 10 = Reserved * BIT 11 = Enable FC-SP Security * BIT 12 = FC Tape Enable - * BIT 13-31 = Reserved + * BIT 13 = Reserved + * BIT 14 = Enable Target PRLI Control + * BIT 15-31 = Reserved */ uint32_t firmware_options_2; @@ -368,7 +368,8 @@ struct init_cb_24xx { * BIT 13 = Data Rate bit 0 * BIT 14 = Data Rate bit 1 * BIT 15 = Data Rate bit 2 - * BIT 16-31 = Reserved + * BIT 16 = Enable 75 ohm Termination Select + * BIT 17-31 = Reserved */ uint32_t firmware_options_3; @@ -394,7 +395,7 @@ struct cmd_type_6 { uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */ - uint8_t lun[8]; /* FCP LUN (BE). */ + struct scsi_lun lun; /* FCP LUN (BE). */ uint16_t control_flags; /* Control flags. */ #define CF_DATA_SEG_DESCR_ENABLE BIT_2 @@ -432,7 +433,7 @@ struct cmd_type_7 { uint16_t dseg_count; /* Data segment count. */ uint16_t reserved_1; - uint8_t lun[8]; /* FCP LUN (BE). */ + struct scsi_lun lun; /* FCP LUN (BE). */ uint16_t task_mgmt_flags; /* Task management flags. */ #define TMF_CLEAR_ACA BIT_14 @@ -440,6 +441,7 @@ struct cmd_type_7 { #define TMF_LUN_RESET BIT_12 #define TMF_CLEAR_TASK_SET BIT_10 #define TMF_ABORT_TASK_SET BIT_9 +#define TMF_DSD_LIST_ENABLE BIT_2 #define TMF_READ_DATA BIT_1 #define TMF_WRITE_DATA BIT_0 @@ -477,7 +479,7 @@ struct sts_entry_24xx { uint16_t comp_status; /* Completion status. */ uint16_t ox_id; /* OX_ID used by the firmware. */ - uint32_t residual_len; /* Residual transfer length. */ + uint32_t residual_len; /* FW calc residual transfer length. */ uint16_t reserved_1; uint16_t state_flags; /* State flags. */ @@ -594,7 +596,7 @@ struct els_entry_24xx { #define EST_SOFI3 (1 << 4) #define EST_SOFI2 (3 << 4) - uint32_t rx_xchg_address[2]; /* Receive exchange address. */ + uint32_t rx_xchg_address; /* Receive exchange address. */ uint16_t rx_dsd_count; uint8_t opcode; @@ -655,6 +657,7 @@ struct logio_entry_24xx { uint16_t control_flags; /* Control flags. */ /* Modifiers. */ +#define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ @@ -773,9 +776,11 @@ struct device_reg_24xx { #define FA_NVRAM_FUNC0_ADDR 0x80 #define FA_NVRAM_FUNC1_ADDR 0x180 -#define FA_NVRAM_VPD_SIZE 0x80 +#define FA_NVRAM_VPD_SIZE 0x200 #define FA_NVRAM_VPD0_ADDR 0x00 #define FA_NVRAM_VPD1_ADDR 0x100 + +#define FA_BOOT_CODE_ADDR 0x00000 /* * RISC code begins at offset 512KB * within flash. Consisting of two @@ -784,6 +789,15 @@ struct device_reg_24xx { #define FA_RISC_CODE_ADDR 0x20000 #define FA_RISC_CODE_SEGMENTS 2 +#define FA_FW_AREA_ADDR 0x40000 +#define FA_VPD_NVRAM_ADDR 0x48000 +#define FA_FEATURE_ADDR 0x4C000 +#define FA_FLASH_DESCR_ADDR 0x50000 +#define FA_HW_EVENT_ADDR 0x54000 +#define FA_BOOT_LOG_ADDR 0x58000 +#define FA_FW_DUMP0_ADDR 0x60000 +#define FA_FW_DUMP1_ADDR 0x70000 + uint32_t flash_data; /* Flash/NVRAM BIOS data. */ uint32_t ctrl_status; /* Control/Status. */ @@ -864,10 +878,13 @@ struct device_reg_24xx { #define HCCRX_CLR_RISC_INT 0xA0000000 uint32_t gpiod; /* GPIO Data register. */ + /* LED update mask. */ #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) /* Data update mask. */ #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) + /* Data update mask. */ +#define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) /* LED control mask. */ #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) /* LED bit values. Color names as @@ -882,6 +899,8 @@ struct device_reg_24xx { uint32_t gpioe; /* GPIO Enable register. */ /* Enable update mask. */ #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) + /* Enable update mask. */ +#define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) /* Enable. */ #define GPEX_ENABLE (BIT_1|BIT_0) @@ -921,6 +940,16 @@ struct device_reg_24xx { uint16_t mailbox29; uint16_t mailbox30; uint16_t mailbox31; + + uint32_t iobase_window; + uint32_t iobase_c4; + uint32_t iobase_c8; + uint32_t unused_4_1[6]; /* Gap. */ + uint32_t iobase_q; + uint32_t unused_5[2]; /* Gap. */ + uint32_t iobase_select; + uint32_t unused_6[2]; /* Gap. */ + uint32_t iobase_sdata; }; /* MID Support ***************************************************************/ @@ -977,6 +1006,25 @@ struct mid_db_24xx { struct mid_db_entry_24xx entries[MAX_MID_VPS]; }; + /* + * Virtual Fabric ID type definition. + */ +typedef struct vf_id { + uint16_t id : 12; + uint16_t priority : 4; +} vf_id_t; + +/* + * Virtual Fabric HopCt type definition. + */ +typedef struct vf_hopct { + uint16_t reserved : 8; + uint16_t hopct : 8; +} vf_hopct_t; + +/* + * Virtual Port Control IOCB + */ #define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */ struct vp_ctrl_entry_24xx { uint8_t entry_type; /* Entry type. */ @@ -989,6 +1037,7 @@ struct vp_ctrl_entry_24xx { uint16_t vp_idx_failed; uint16_t comp_status; /* Completion status. */ +#define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */ #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */ #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */ @@ -997,24 +1046,34 @@ struct vp_ctrl_entry_24xx { #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */ #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */ #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */ +#define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */ uint16_t vp_count; uint8_t vp_idx_map[16]; - - uint8_t reserved_4[32]; + uint16_t flags; + struct vf_id id; + uint16_t reserved_4; + struct vf_hopct hopct; + uint8_t reserved_5[8]; }; +/* + * Modify Virtual Port Configuration IOCB + */ #define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */ struct vp_config_entry_24xx { uint8_t entry_type; /* Entry type. */ uint8_t entry_count; /* Entry count. */ - uint8_t sys_define; /* System defined. */ + uint8_t handle_count; uint8_t entry_status; /* Entry Status. */ uint32_t handle; /* System handle. */ - uint16_t reserved_1; + uint16_t flags; +#define CS_VF_BIND_VPORTS_TO_VF BIT_0 +#define CS_VF_SET_QOS_OF_VPORTS BIT_1 +#define CS_VF_SET_HOPS_OF_VPORTS BIT_2 uint16_t comp_status; /* Completion status. */ #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */ @@ -1024,27 +1083,29 @@ struct vp_config_entry_24xx { #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */ uint8_t command; -#define VCT_COMMAND_MOD_VPS 0x00 /* Enable VPs. */ -#define VCT_COMMAND_MOD_ENABLE_VPS 0x08 /* Disable VPs. */ +#define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */ +#define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */ uint8_t vp_count; - uint8_t vp_idx1; - uint8_t vp_idx2; + uint8_t vp_index1; + uint8_t vp_index2; uint8_t options_idx1; uint8_t hard_address_idx1; - uint16_t reserved_2; + uint16_t reserved_vp1; uint8_t port_name_idx1[WWN_SIZE]; uint8_t node_name_idx1[WWN_SIZE]; uint8_t options_idx2; uint8_t hard_address_idx2; - uint16_t reserved_3; + uint16_t reserved_vp2; uint8_t port_name_idx2[WWN_SIZE]; uint8_t node_name_idx2[WWN_SIZE]; - - uint8_t reserved_4[8]; + struct vf_id id; + uint16_t reserved_4; + struct vf_hopct hopct; + uint8_t reserved_5; }; #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */ @@ -1069,5 +1130,30 @@ struct vp_rpt_id_entry_24xx { uint8_t reserved_4[32]; }; +#define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */ +struct vf_evfp_entry_24xx { + uint8_t entry_type; /* Entry type. */ + uint8_t entry_count; /* Entry count. */ + uint8_t sys_define; /* System defined. */ + uint8_t entry_status; /* Entry Status. */ + + uint32_t handle; /* System handle. */ + uint16_t comp_status; /* Completion status. */ + uint16_t timeout; /* timeout */ + uint16_t adim_tagging_mode; + + uint16_t vfport_id; + uint32_t exch_addr; + + uint16_t nport_handle; /* N_PORT handle. */ + uint16_t control_flags; + uint32_t io_parameter_0; + uint32_t io_parameter_1; + uint32_t tx_address[2]; /* Data segment 0 address. */ + uint32_t tx_len; /* Data segment 0 length. */ + uint32_t rx_address[2]; /* Data segment 1 address. */ + uint32_t rx_len; /* Data segment 1 length. */ +}; + /* END MID Support ***********************************************************/ #endif