X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=drivers%2Fnet%2Fsmc91x.h;h=8d2772cc42f2ba5e174e501de81c966c6cd97474;hb=f8965467f366fd18f01feafb5db10512d7b4422c;hp=0c9f1e7dab2e8de01277bef61c3f7b072792ca9b;hpb=12f417ee95bf98cd3e42d2a771f7c6d360159b9d;p=safe%2Fjmp%2Flinux-2.6 diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index 0c9f1e7..8d2772c 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h @@ -28,32 +28,60 @@ . Authors . Erik Stahlman . Daris A Nevil - . Nicolas Pitre + . Nicolas Pitre . ---------------------------------------------------------------------------*/ #ifndef _SMC91X_H_ #define _SMC91X_H_ +#include /* * Define your architecture specific bus configuration parameters here. */ -#if defined(CONFIG_ARCH_LUBBOCK) +#if defined(CONFIG_ARCH_LUBBOCK) ||\ + defined(CONFIG_MACH_MAINSTONE) ||\ + defined(CONFIG_MACH_ZYLONITE) ||\ + defined(CONFIG_MACH_LITTLETON) ||\ + defined(CONFIG_MACH_ZYLONITE2) ||\ + defined(CONFIG_ARCH_VIPER) ||\ + defined(CONFIG_MACH_STARGATE2) -/* We can only do 16-bit reads and writes in the static memory space. */ -#define SMC_CAN_USE_8BIT 0 +#include + +/* Now the bus width is specified in the platform data + * pretend here to support all I/O access types + */ +#define SMC_CAN_USE_8BIT 1 #define SMC_CAN_USE_16BIT 1 -#define SMC_CAN_USE_32BIT 0 +#define SMC_CAN_USE_32BIT 1 #define SMC_NOWAIT 1 -/* The first two address lines aren't connected... */ -#define SMC_IO_SHIFT 2 +#define SMC_IO_SHIFT (lp->io_shift) +#define SMC_inb(a, r) readb((a) + (r)) #define SMC_inw(a, r) readw((a) + (r)) -#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_inl(a, r) readl((a) + (r)) +#define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_outl(v, a, r) writel(v, (a) + (r)) #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) +#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) +#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) +#define SMC_IRQ_FLAGS (-1) /* from resource */ + +/* We actually can't write halfwords properly if not word aligned */ +static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg) +{ + if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) { + unsigned int v = val << 16; + v |= readl(ioaddr + (reg & ~2)) & 0xffff; + writel(v, ioaddr + (reg & ~2)); + } else { + writew(val, ioaddr + reg); + } +} #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) @@ -109,11 +137,11 @@ #define SMC_outw(v, a, r) writew(v, (a) + (r)) #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) -#define SMC_IRQ_FLAGS (0) +#define SMC_IRQ_FLAGS (-1) #elif defined(CONFIG_SA1100_ASSABET) -#include +#include /* We can only do 8-bit reads and writes in the static memory space. */ #define SMC_CAN_USE_8BIT 1 @@ -128,8 +156,10 @@ #define SMC_outb(v, a, r) writeb(v, (a) + (r)) #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) +#define SMC_IRQ_FLAGS (-1) /* from resource */ -#elif defined(CONFIG_MACH_LOGICPD_PXA270) +#elif defined(CONFIG_MACH_LOGICPD_PXA270) || \ + defined(CONFIG_MACH_NOMADIK_8815NHK) #define SMC_CAN_USE_8BIT 0 #define SMC_CAN_USE_16BIT 1 @@ -143,9 +173,9 @@ #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) #elif defined(CONFIG_ARCH_INNOKOM) || \ - defined(CONFIG_MACH_MAINSTONE) || \ defined(CONFIG_ARCH_PXA_IDP) || \ - defined(CONFIG_ARCH_RAMSES) + defined(CONFIG_ARCH_RAMSES) || \ + defined(CONFIG_ARCH_PCM027) #define SMC_CAN_USE_8BIT 1 #define SMC_CAN_USE_16BIT 1 @@ -161,6 +191,7 @@ #define SMC_outl(v, a, r) writel(v, (a) + (r)) #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) +#define SMC_IRQ_FLAGS (-1) /* from resource */ /* We actually can't write halfwords properly if not word aligned */ static inline void @@ -175,31 +206,6 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) } } -#elif defined(CONFIG_ARCH_OMAP) - -/* We can only do 16-bit reads and writes in the static memory space. */ -#define SMC_CAN_USE_8BIT 0 -#define SMC_CAN_USE_16BIT 1 -#define SMC_CAN_USE_32BIT 0 -#define SMC_IO_SHIFT 0 -#define SMC_NOWAIT 1 - -#define SMC_inw(a, r) readw((a) + (r)) -#define SMC_outw(v, a, r) writew(v, (a) + (r)) -#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) -#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) - -#include -#include - -#define SMC_IRQ_FLAGS (( \ - machine_is_omap_h2() \ - || machine_is_omap_h3() \ - || machine_is_omap_h4() \ - || (machine_is_omap_innovator() && !cpu_is_omap1510()) \ - ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING) - - #elif defined(CONFIG_SH_SH4202_MICRODEV) #define SMC_CAN_USE_8BIT 0 @@ -219,26 +225,13 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) #define SMC_IRQ_FLAGS (0) -#elif defined(CONFIG_ISA) - -#define SMC_CAN_USE_8BIT 1 -#define SMC_CAN_USE_16BIT 1 -#define SMC_CAN_USE_32BIT 0 - -#define SMC_inb(a, r) inb((a) + (r)) -#define SMC_inw(a, r) inw((a) + (r)) -#define SMC_outb(v, a, r) outb(v, (a) + (r)) -#define SMC_outw(v, a, r) outw(v, (a) + (r)) -#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) -#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) - #elif defined(CONFIG_M32R) #define SMC_CAN_USE_8BIT 0 #define SMC_CAN_USE_16BIT 1 #define SMC_CAN_USE_32BIT 0 -#define SMC_inb(a, r) inb((u32)a) + (r)) +#define SMC_inb(a, r) inb(((u32)a) + (r)) #define SMC_inw(a, r) inw(((u32)a) + (r)) #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) @@ -250,9 +243,9 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) #define RPC_LSA_DEFAULT RPC_LED_TX_RX #define RPC_LSB_DEFAULT RPC_LED_100_10 -#elif defined(CONFIG_MACH_LPD79520) \ - || defined(CONFIG_MACH_LPD7A400) \ - || defined(CONFIG_MACH_LPD7A404) +#elif defined(CONFIG_MACH_LPD79520) || \ + defined(CONFIG_MACH_LPD7A400) || \ + defined(CONFIG_MACH_LPD7A404) /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the * way that the CPU handles chip selects and the way that the SMC chip @@ -273,7 +266,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) * IOBARRIER on entry to their ISR. */ -#include /* IOBARRIER_VIRT */ +#include /* IOBARRIER_VIRT */ #define SMC_CAN_USE_8BIT 0 #define SMC_CAN_USE_16BIT 1 @@ -312,38 +305,6 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #define RPC_LSA_DEFAULT RPC_LED_TX_RX #define RPC_LSB_DEFAULT RPC_LED_100_10 -#elif defined(CONFIG_SOC_AU1X00) - -#include - -/* We can only do 16-bit reads and writes in the static memory space. */ -#define SMC_CAN_USE_8BIT 0 -#define SMC_CAN_USE_16BIT 1 -#define SMC_CAN_USE_32BIT 0 -#define SMC_IO_SHIFT 0 -#define SMC_NOWAIT 1 - -#define SMC_inw(a, r) au_readw((unsigned long)((a) + (r))) -#define SMC_insw(a, r, p, l) \ - do { \ - unsigned long _a = (unsigned long)((a) + (r)); \ - int _l = (l); \ - u16 *_p = (u16 *)(p); \ - while (_l-- > 0) \ - *_p++ = au_readw(_a); \ - } while(0) -#define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r))) -#define SMC_outsw(a, r, p, l) \ - do { \ - unsigned long _a = (unsigned long)((a) + (r)); \ - int _l = (l); \ - const u16 *_p = (const u16 *)(p); \ - while (_l-- > 0) \ - au_writew(*_p++ , _a); \ - } while(0) - -#define SMC_IRQ_FLAGS (0) - #elif defined(CONFIG_ARCH_VERSATILE) #define SMC_CAN_USE_8BIT 1 @@ -359,76 +320,79 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #define SMC_outl(v, a, r) writel(v, (a) + (r)) #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) +#define SMC_IRQ_FLAGS (-1) /* from resource */ -#define SMC_IRQ_FLAGS (0) - -#elif defined(CONFIG_ARCH_VERSATILE) - -#define SMC_CAN_USE_8BIT 1 -#define SMC_CAN_USE_16BIT 1 -#define SMC_CAN_USE_32BIT 1 -#define SMC_NOWAIT 1 +#elif defined(CONFIG_MN10300) -#define SMC_inb(a, r) readb((a) + (r)) -#define SMC_inw(a, r) readw((a) + (r)) -#define SMC_inl(a, r) readl((a) + (r)) -#define SMC_outb(v, a, r) writeb(v, (a) + (r)) -#define SMC_outw(v, a, r) writew(v, (a) + (r)) -#define SMC_outl(v, a, r) writel(v, (a) + (r)) -#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) -#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) +/* + * MN10300/AM33 configuration + */ -#define SMC_IRQ_FLAGS (0) +#include -#elif defined(CONFIG_ARCH_VERSATILE) +#elif defined(CONFIG_ARCH_MSM) -#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_8BIT 0 #define SMC_CAN_USE_16BIT 1 -#define SMC_CAN_USE_32BIT 1 +#define SMC_CAN_USE_32BIT 0 #define SMC_NOWAIT 1 -#define SMC_inb(a, r) readb((a) + (r)) #define SMC_inw(a, r) readw((a) + (r)) -#define SMC_inl(a, r) readl((a) + (r)) -#define SMC_outb(v, a, r) writeb(v, (a) + (r)) #define SMC_outw(v, a, r) writew(v, (a) + (r)) -#define SMC_outl(v, a, r) writel(v, (a) + (r)) -#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) -#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) +#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) -#define SMC_IRQ_FLAGS (0) +#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH -#elif defined(CONFIG_ARCH_VERSATILE) +#elif defined(CONFIG_COLDFIRE) -#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_8BIT 0 #define SMC_CAN_USE_16BIT 1 -#define SMC_CAN_USE_32BIT 1 +#define SMC_CAN_USE_32BIT 0 #define SMC_NOWAIT 1 -#define SMC_inb(a, r) readb((a) + (r)) -#define SMC_inw(a, r) readw((a) + (r)) -#define SMC_inl(a, r) readl((a) + (r)) -#define SMC_outb(v, a, r) writeb(v, (a) + (r)) -#define SMC_outw(v, a, r) writew(v, (a) + (r)) -#define SMC_outl(v, a, r) writel(v, (a) + (r)) -#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) -#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) +static inline void mcf_insw(void *a, unsigned char *p, int l) +{ + u16 *wp = (u16 *) p; + while (l-- > 0) + *wp++ = readw(a); +} -#define SMC_IRQ_FLAGS (0) +static inline void mcf_outsw(void *a, unsigned char *p, int l) +{ + u16 *wp = (u16 *) p; + while (l-- > 0) + writew(*wp++, a); +} + +#define SMC_inw(a, r) _swapw(readw((a) + (r))) +#define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r)) +#define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l) +#define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l) + +#define SMC_IRQ_FLAGS (IRQF_DISABLED) #else +/* + * Default configuration + */ + #define SMC_CAN_USE_8BIT 1 #define SMC_CAN_USE_16BIT 1 #define SMC_CAN_USE_32BIT 1 #define SMC_NOWAIT 1 +#define SMC_IO_SHIFT (lp->io_shift) + #define SMC_inb(a, r) readb((a) + (r)) #define SMC_inw(a, r) readw((a) + (r)) #define SMC_inl(a, r) readl((a) + (r)) #define SMC_outb(v, a, r) writeb(v, (a) + (r)) #define SMC_outw(v, a, r) writew(v, (a) + (r)) #define SMC_outl(v, a, r) writel(v, (a) + (r)) +#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) @@ -437,7 +401,61 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #endif -#ifdef SMC_USE_PXA_DMA + +/* store this information for the driver.. */ +struct smc_local { + /* + * If I have to wait until memory is available to send a + * packet, I will store the skbuff here, until I get the + * desired memory. Then, I'll send it out and free it. + */ + struct sk_buff *pending_tx_skb; + struct tasklet_struct tx_task; + + /* version/revision of the SMC91x chip */ + int version; + + /* Contains the current active transmission mode */ + int tcr_cur_mode; + + /* Contains the current active receive mode */ + int rcr_cur_mode; + + /* Contains the current active receive/phy mode */ + int rpc_cur_mode; + int ctl_rfduplx; + int ctl_rspeed; + + u32 msg_enable; + u32 phy_type; + struct mii_if_info mii; + + /* work queue */ + struct work_struct phy_configure; + struct net_device *dev; + int work_pending; + + spinlock_t lock; + +#ifdef CONFIG_ARCH_PXA + /* DMA needs the physical address of the chip */ + u_long physaddr; + struct device *device; +#endif + void __iomem *base; + void __iomem *datacs; + + /* the low address lines on some platforms aren't connected... */ + int io_shift; + + struct smc91x_platdata cfg; +}; + +#define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT) +#define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT) +#define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT) + +#ifdef CONFIG_ARCH_PXA /* * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is * always happening in irq context so no need to worry about races. TX is @@ -445,17 +463,17 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, * as RX which can overrun memory and lose packets. */ #include -#include -#include +#include #ifdef SMC_insl #undef SMC_insl #define SMC_insl(a, r, p, l) \ - smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) + smc_pxa_dma_insl(a, lp, r, dev->dma, p, l) static inline void -smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, +smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, u_char *buf, int len) { + u_long physaddr = lp->physaddr; dma_addr_t dmabuf; /* fallback if no DMA available */ @@ -472,7 +490,7 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, } len *= 4; - dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); + dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); DCSR(dma) = DCSR_NODESC; DTADR(dma) = dmabuf; DSADR(dma) = physaddr + reg; @@ -482,18 +500,19 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, while (!(DCSR(dma) & DCSR_STOPSTATE)) cpu_relax(); DCSR(dma) = 0; - dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); + dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); } #endif #ifdef SMC_insw #undef SMC_insw #define SMC_insw(a, r, p, l) \ - smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) + smc_pxa_dma_insw(a, lp, r, dev->dma, p, l) static inline void -smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, +smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, u_char *buf, int len) { + u_long physaddr = lp->physaddr; dma_addr_t dmabuf; /* fallback if no DMA available */ @@ -510,7 +529,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, } len *= 2; - dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); + dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); DCSR(dma) = DCSR_NODESC; DTADR(dma) = dmabuf; DSADR(dma) = physaddr + reg; @@ -520,7 +539,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, while (!(DCSR(dma) & DCSR_STOPSTATE)) cpu_relax(); DCSR(dma) = 0; - dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); + dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); } #endif @@ -529,7 +548,7 @@ smc_pxa_dma_irq(int dma, void *dummy) { DCSR(dma) = 0; } -#endif /* SMC_USE_PXA_DMA */ +#endif /* CONFIG_ARCH_PXA */ /* @@ -626,7 +645,7 @@ smc_pxa_dma_irq(int dma, void *dummy) // Transmit Control Register /* BANK 0 */ -#define TCR_REG SMC_REG(0x0000, 0) +#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) #define TCR_ENABLE 0x0001 // When 1 we can transmit #define TCR_LOOP 0x0002 // Controls output pin LBK #define TCR_FORCOL 0x0004 // When 1 will force a collision @@ -645,7 +664,7 @@ smc_pxa_dma_irq(int dma, void *dummy) // EPH Status Register /* BANK 0 */ -#define EPH_STATUS_REG SMC_REG(0x0002, 0) +#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0) #define ES_TX_SUC 0x0001 // Last TX was successful #define ES_SNGL_COL 0x0002 // Single collision detected for last tx #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx @@ -664,7 +683,7 @@ smc_pxa_dma_irq(int dma, void *dummy) // Receive Control Register /* BANK 0 */ -#define RCR_REG SMC_REG(0x0004, 0) +#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0) #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted #define RCR_PRMS 0x0002 // Enable promiscuous mode #define RCR_ALMUL 0x0004 // When set accepts all multicast frames @@ -681,30 +700,22 @@ smc_pxa_dma_irq(int dma, void *dummy) // Counter Register /* BANK 0 */ -#define COUNTER_REG SMC_REG(0x0006, 0) +#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) // Memory Information Register /* BANK 0 */ -#define MIR_REG SMC_REG(0x0008, 0) +#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0) // Receive/Phy Control Register /* BANK 0 */ -#define RPC_REG SMC_REG(0x000A, 0) +#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0) #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb -#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect -#define RPC_LED_RES (0x01) // LED = Reserved -#define RPC_LED_10 (0x02) // LED = 10Mbps link detect -#define RPC_LED_FD (0x03) // LED = Full Duplex Mode -#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred -#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect -#define RPC_LED_TX (0x06) // LED = TX packet occurred -#define RPC_LED_RX (0x07) // LED = RX packet occurred #ifndef RPC_LSA_DEFAULT #define RPC_LSA_DEFAULT RPC_LED_100 @@ -713,7 +724,7 @@ smc_pxa_dma_irq(int dma, void *dummy) #define RPC_LSB_DEFAULT RPC_LED_FD #endif -#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) +#define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX) /* Bank 0 0x0C is reserved */ @@ -725,7 +736,7 @@ smc_pxa_dma_irq(int dma, void *dummy) // Configuration Reg /* BANK 1 */ -#define CONFIG_REG SMC_REG(0x0000, 1) +#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1) #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus @@ -737,24 +748,24 @@ smc_pxa_dma_irq(int dma, void *dummy) // Base Address Register /* BANK 1 */ -#define BASE_REG SMC_REG(0x0002, 1) +#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) // Individual Address Registers /* BANK 1 */ -#define ADDR0_REG SMC_REG(0x0004, 1) -#define ADDR1_REG SMC_REG(0x0006, 1) -#define ADDR2_REG SMC_REG(0x0008, 1) +#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) +#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) +#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) // General Purpose Register /* BANK 1 */ -#define GP_REG SMC_REG(0x000A, 1) +#define GP_REG(lp) SMC_REG(lp, 0x000A, 1) // Control Register /* BANK 1 */ -#define CTL_REG SMC_REG(0x000C, 1) +#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1) #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt @@ -767,7 +778,7 @@ smc_pxa_dma_irq(int dma, void *dummy) // MMU Command Register /* BANK 2 */ -#define MMU_CMD_REG SMC_REG(0x0000, 2) +#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) #define MC_BUSY 1 // When 1 the last release has not completed #define MC_NOP (0<<5) // No Op #define MC_ALLOC (1<<5) // OR with number of 256 byte packets @@ -781,30 +792,30 @@ smc_pxa_dma_irq(int dma, void *dummy) // Packet Number Register /* BANK 2 */ -#define PN_REG SMC_REG(0x0002, 2) +#define PN_REG(lp) SMC_REG(lp, 0x0002, 2) // Allocation Result Register /* BANK 2 */ -#define AR_REG SMC_REG(0x0003, 2) +#define AR_REG(lp) SMC_REG(lp, 0x0003, 2) #define AR_FAILED 0x80 // Alocation Failed // TX FIFO Ports Register /* BANK 2 */ -#define TXFIFO_REG SMC_REG(0x0004, 2) +#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty // RX FIFO Ports Register /* BANK 2 */ -#define RXFIFO_REG SMC_REG(0x0005, 2) +#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) #define RXFIFO_REMPTY 0x80 // RX FIFO Empty -#define FIFO_REG SMC_REG(0x0004, 2) +#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) // Pointer Register /* BANK 2 */ -#define PTR_REG SMC_REG(0x0006, 2) +#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2) #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access #define PTR_READ 0x2000 // When 1 the operation is a read @@ -812,17 +823,17 @@ smc_pxa_dma_irq(int dma, void *dummy) // Data Register /* BANK 2 */ -#define DATA_REG SMC_REG(0x0008, 2) +#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) // Interrupt Status/Acknowledge Register /* BANK 2 */ -#define INT_REG SMC_REG(0x000C, 2) +#define INT_REG(lp) SMC_REG(lp, 0x000C, 2) // Interrupt Mask Register /* BANK 2 */ -#define IM_REG SMC_REG(0x000D, 2) +#define IM_REG(lp) SMC_REG(lp, 0x000D, 2) #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt #define IM_ERCV_INT 0x40 // Early Receive Interrupt #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section @@ -835,15 +846,15 @@ smc_pxa_dma_irq(int dma, void *dummy) // Multicast Table Registers /* BANK 3 */ -#define MCAST_REG1 SMC_REG(0x0000, 3) -#define MCAST_REG2 SMC_REG(0x0002, 3) -#define MCAST_REG3 SMC_REG(0x0004, 3) -#define MCAST_REG4 SMC_REG(0x0006, 3) +#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) +#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) +#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) +#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) // Management Interface Register (MII) /* BANK 3 */ -#define MII_REG SMC_REG(0x0008, 3) +#define MII_REG(lp) SMC_REG(lp, 0x0008, 3) #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup #define MII_MDOE 0x0008 // MII Output Enable #define MII_MCLK 0x0004 // MII Clock, pin MDCLK @@ -854,20 +865,20 @@ smc_pxa_dma_irq(int dma, void *dummy) // Revision Register /* BANK 3 */ /* ( hi: chip id low: rev # ) */ -#define REV_REG SMC_REG(0x000A, 3) +#define REV_REG(lp) SMC_REG(lp, 0x000A, 3) // Early RCV Register /* BANK 3 */ /* this is NOT on SMC9192 */ -#define ERCV_REG SMC_REG(0x000C, 3) +#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask // External Register /* BANK 7 */ -#define EXT_REG SMC_REG(0x0000, 7) +#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7) #define CHIP_9192 3 @@ -991,9 +1002,9 @@ static const char * chip_ids[ 16 ] = { */ #if SMC_DEBUG > 0 -#define SMC_REG(reg, bank) \ +#define SMC_REG(lp, reg, bank) \ ({ \ - int __b = SMC_CURRENT_BANK(); \ + int __b = SMC_CURRENT_BANK(lp); \ if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ printk( "%s: bank reg screwed (0x%04x)\n", \ CARDNAME, __b ); \ @@ -1002,7 +1013,7 @@ static const char * chip_ids[ 16 ] = { reg<> 8) ) +#define SMC_GET_AR(lp) \ + (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \ + : (SMC_inw(ioaddr, PN_REG(lp)) >> 8)) -#define SMC_GET_TXFIFO() \ - ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \ - : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) ) +#define SMC_GET_TXFIFO(lp) \ + (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \ + : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF)) -#define SMC_GET_RXFIFO() \ - ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \ - : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) ) +#define SMC_GET_RXFIFO(lp) \ + (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \ + : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8)) -#define SMC_GET_INT() \ - ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \ - : (SMC_inw(ioaddr, INT_REG) & 0xFF) ) +#define SMC_GET_INT(lp) \ + (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \ + : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF)) -#define SMC_ACK_INT(x) \ +#define SMC_ACK_INT(lp, x) \ do { \ - if (SMC_CAN_USE_8BIT) \ - SMC_outb(x, ioaddr, INT_REG); \ + if (SMC_8BIT(lp)) \ + SMC_outb(x, ioaddr, INT_REG(lp)); \ else { \ unsigned long __flags; \ int __mask; \ local_irq_save(__flags); \ - __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ - SMC_outw( __mask | (x), ioaddr, INT_REG ); \ + __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \ + SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \ local_irq_restore(__flags); \ } \ } while (0) -#define SMC_GET_INT_MASK() \ - ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \ - : (SMC_inw( ioaddr, INT_REG ) >> 8) ) +#define SMC_GET_INT_MASK(lp) \ + (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \ + : (SMC_inw(ioaddr, INT_REG(lp)) >> 8)) -#define SMC_SET_INT_MASK(x) \ +#define SMC_SET_INT_MASK(lp, x) \ do { \ - if (SMC_CAN_USE_8BIT) \ - SMC_outb(x, ioaddr, IM_REG); \ + if (SMC_8BIT(lp)) \ + SMC_outb(x, ioaddr, IM_REG(lp)); \ else \ - SMC_outw((x) << 8, ioaddr, INT_REG); \ + SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \ } while (0) -#define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT) +#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT) -#define SMC_SELECT_BANK(x) \ +#define SMC_SELECT_BANK(lp, x) \ do { \ - if (SMC_MUST_ALIGN_WRITE) \ + if (SMC_MUST_ALIGN_WRITE(lp)) \ SMC_outl((x)<<16, ioaddr, 12<> 8; \ - __v = SMC_inw( ioaddr, ADDR1_REG ); \ + __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \ addr[2] = __v; addr[3] = __v >> 8; \ - __v = SMC_inw( ioaddr, ADDR2_REG ); \ + __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \ addr[4] = __v; addr[5] = __v >> 8; \ } while (0) #endif -#define SMC_SET_MAC_ADDR(addr) \ +#define SMC_SET_MAC_ADDR(lp, addr) \ do { \ - SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ - SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ - SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ + SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ + SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ + SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ } while (0) -#define SMC_SET_MCAST(x) \ +#define SMC_SET_MCAST(lp, x) \ do { \ const unsigned char *mt = (x); \ - SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ - SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ - SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ - SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ + SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ + SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ + SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ + SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ } while (0) -#define SMC_PUT_PKT_HDR(status, length) \ +#define SMC_PUT_PKT_HDR(lp, status, length) \ do { \ - if (SMC_CAN_USE_32BIT) \ - SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \ + if (SMC_32BIT(lp)) \ + SMC_outl((status) | (length)<<16, ioaddr, \ + DATA_REG(lp)); \ else { \ - SMC_outw(status, ioaddr, DATA_REG); \ - SMC_outw(length, ioaddr, DATA_REG); \ + SMC_outw(status, ioaddr, DATA_REG(lp)); \ + SMC_outw(length, ioaddr, DATA_REG(lp)); \ } \ } while (0) -#define SMC_GET_PKT_HDR(status, length) \ +#define SMC_GET_PKT_HDR(lp, status, length) \ do { \ - if (SMC_CAN_USE_32BIT) { \ - unsigned int __val = SMC_inl(ioaddr, DATA_REG); \ + if (SMC_32BIT(lp)) { \ + unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \ (status) = __val & 0xffff; \ (length) = __val >> 16; \ } else { \ - (status) = SMC_inw(ioaddr, DATA_REG); \ - (length) = SMC_inw(ioaddr, DATA_REG); \ + (status) = SMC_inw(ioaddr, DATA_REG(lp)); \ + (length) = SMC_inw(ioaddr, DATA_REG(lp)); \ } \ } while (0) -#define SMC_PUSH_DATA(p, l) \ +#define SMC_PUSH_DATA(lp, p, l) \ do { \ - if (SMC_CAN_USE_32BIT) { \ + if (SMC_32BIT(lp)) { \ void *__ptr = (p); \ int __len = (l); \ - void *__ioaddr = ioaddr; \ + void __iomem *__ioaddr = ioaddr; \ if (__len >= 2 && (unsigned long)__ptr & 2) { \ __len -= 2; \ - SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \ + SMC_outw(*(u16 *)__ptr, ioaddr, \ + DATA_REG(lp)); \ __ptr += 2; \ } \ if (SMC_CAN_USE_DATACS && lp->datacs) \ __ioaddr = lp->datacs; \ - SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \ + SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ if (__len & 2) { \ __ptr += (__len & ~3); \ - SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \ + SMC_outw(*((u16 *)__ptr), ioaddr, \ + DATA_REG(lp)); \ } \ - } else if (SMC_CAN_USE_16BIT) \ - SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \ - else if (SMC_CAN_USE_8BIT) \ - SMC_outsb(ioaddr, DATA_REG, p, l); \ + } else if (SMC_16BIT(lp)) \ + SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ + else if (SMC_8BIT(lp)) \ + SMC_outsb(ioaddr, DATA_REG(lp), p, l); \ } while (0) -#define SMC_PULL_DATA(p, l) \ +#define SMC_PULL_DATA(lp, p, l) \ do { \ - if (SMC_CAN_USE_32BIT) { \ + if (SMC_32BIT(lp)) { \ void *__ptr = (p); \ int __len = (l); \ - void *__ioaddr = ioaddr; \ + void __iomem *__ioaddr = ioaddr; \ if ((unsigned long)__ptr & 2) { \ /* \ * We want 32bit alignment here. \ @@ -1239,16 +1263,17 @@ static const char * chip_ids[ 16 ] = { */ \ __ptr -= 2; \ __len += 2; \ - SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ + SMC_SET_PTR(lp, \ + 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ } \ if (SMC_CAN_USE_DATACS && lp->datacs) \ __ioaddr = lp->datacs; \ __len += 2; \ - SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \ - } else if (SMC_CAN_USE_16BIT) \ - SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \ - else if (SMC_CAN_USE_8BIT) \ - SMC_insb(ioaddr, DATA_REG, p, l); \ + SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ + } else if (SMC_16BIT(lp)) \ + SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ + else if (SMC_8BIT(lp)) \ + SMC_insb(ioaddr, DATA_REG(lp), p, l); \ } while (0) #endif /* _SMC91X_H_ */