X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=drivers%2Fnet%2Fsmc91x.h;h=271c28dc9baae1057681ce326ea4bc81e50e8756;hb=a7c458906542aacdda7289bb21f527a2dc4097ca;hp=9f9f8f2d533877e6e97740fda9ed69d5e6ca064a;hpb=09e590e5d5a93f2eaa748a89c623258e6bad1648;p=safe%2Fjmp%2Flinux-2.6 diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index 9f9f8f2..271c28d 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h @@ -54,7 +54,57 @@ #define SMC_outw(v, a, r) writew(v, (a) + (r)) #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) +#define SMC_IRQ_FLAGS (-1) /* from resource */ +#elif defined(CONFIG_BLACKFIN) + +#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH +#define RPC_LSA_DEFAULT RPC_LED_100_10 +#define RPC_LSB_DEFAULT RPC_LED_TX_RX + +# if defined (CONFIG_BFIN561_EZKIT) +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 1 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 1 +#define SMC_USE_BFIN_DMA 0 + + +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_inl(a, r) readl((a) + (r)) +#define SMC_outl(v, a, r) writel(v, (a) + (r)) +#define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l) +#define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l) +# else +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 1 +#define SMC_USE_BFIN_DMA 0 + + +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l) +#define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l) +# endif +/* check if the mac in reg is valid */ +#define SMC_GET_MAC_ADDR(addr) \ + do { \ + unsigned int __v; \ + __v = SMC_inw(ioaddr, ADDR0_REG); \ + addr[0] = __v; addr[1] = __v >> 8; \ + __v = SMC_inw(ioaddr, ADDR1_REG); \ + addr[2] = __v; addr[3] = __v >> 8; \ + __v = SMC_inw(ioaddr, ADDR2_REG); \ + addr[4] = __v; addr[5] = __v >> 8; \ + if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \ + random_ether_addr(addr); \ + } \ + } while (0) #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) /* We can only do 16-bit reads and writes in the static memory space. */ @@ -109,7 +159,7 @@ #define SMC_outw(v, a, r) writew(v, (a) + (r)) #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) -#define SMC_IRQ_FLAGS (0) +#define SMC_IRQ_FLAGS (-1) #elif defined(CONFIG_SA1100_ASSABET) @@ -128,6 +178,7 @@ #define SMC_outb(v, a, r) writeb(v, (a) + (r)) #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) +#define SMC_IRQ_FLAGS (-1) /* from resource */ #elif defined(CONFIG_MACH_LOGICPD_PXA270) @@ -145,7 +196,8 @@ #elif defined(CONFIG_ARCH_INNOKOM) || \ defined(CONFIG_MACH_MAINSTONE) || \ defined(CONFIG_ARCH_PXA_IDP) || \ - defined(CONFIG_ARCH_RAMSES) + defined(CONFIG_ARCH_RAMSES) || \ + defined(CONFIG_ARCH_PCM027) #define SMC_CAN_USE_8BIT 1 #define SMC_CAN_USE_16BIT 1 @@ -161,6 +213,7 @@ #define SMC_outl(v, a, r) writel(v, (a) + (r)) #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) +#define SMC_IRQ_FLAGS (-1) /* from resource */ /* We actually can't write halfwords properly if not word aligned */ static inline void @@ -175,6 +228,22 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) } } +#elif defined(CONFIG_MACH_ZYLONITE) + +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 1 +#define SMC_USE_PXA_DMA 1 +#define SMC_inb(a, r) readb((a) + (r)) +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) +#define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_IRQ_FLAGS (-1) /* from resource */ + #elif defined(CONFIG_ARCH_OMAP) /* We can only do 16-bit reads and writes in the static memory space. */ @@ -184,26 +253,11 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) #define SMC_IO_SHIFT 0 #define SMC_NOWAIT 1 -#define SMC_inb(a, r) readb((a) + (r)) -#define SMC_outb(v, a, r) writeb(v, (a) + (r)) #define SMC_inw(a, r) readw((a) + (r)) #define SMC_outw(v, a, r) writew(v, (a) + (r)) #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) -#define SMC_inl(a, r) readl((a) + (r)) -#define SMC_outl(v, a, r) writel(v, (a) + (r)) -#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) -#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) - -#include -#include - -#define SMC_IRQ_FLAGS (( \ - machine_is_omap_h2() \ - || machine_is_omap_h3() \ - || (machine_is_omap_innovator() && !cpu_is_omap1510()) \ - ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING) - +#define SMC_IRQ_FLAGS (-1) /* from resource */ #elif defined(CONFIG_SH_SH4202_MICRODEV) @@ -237,13 +291,43 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) +#elif defined(CONFIG_SUPERH) + +#ifdef CONFIG_SOLUTION_ENGINE +#define SMC_IRQ_FLAGS (0) +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 1 + +#define SMC_inw(a, r) inw((a) + (r)) +#define SMC_outw(v, a, r) outw(v, (a) + (r)) +#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) + +#else /* BOARDS */ + +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 + +#define SMC_inb(a, r) inb((a) + (r)) +#define SMC_inw(a, r) inw((a) + (r)) +#define SMC_outb(v, a, r) outb(v, (a) + (r)) +#define SMC_outw(v, a, r) outw(v, (a) + (r)) +#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) + +#endif /* BOARDS */ + #elif defined(CONFIG_M32R) #define SMC_CAN_USE_8BIT 0 #define SMC_CAN_USE_16BIT 1 #define SMC_CAN_USE_32BIT 0 -#define SMC_inb(a, r) inb((u32)a) + (r)) +#define SMC_inb(a, r) inb(((u32)a) + (r)) #define SMC_inw(a, r) inw(((u32)a) + (r)) #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) @@ -364,8 +448,7 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #define SMC_outl(v, a, r) writel(v, (a) + (r)) #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) - -#define SMC_IRQ_FLAGS (0) +#define SMC_IRQ_FLAGS (-1) /* from resource */ #else @@ -388,6 +471,52 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #endif + +/* store this information for the driver.. */ +struct smc_local { + /* + * If I have to wait until memory is available to send a + * packet, I will store the skbuff here, until I get the + * desired memory. Then, I'll send it out and free it. + */ + struct sk_buff *pending_tx_skb; + struct tasklet_struct tx_task; + + /* version/revision of the SMC91x chip */ + int version; + + /* Contains the current active transmission mode */ + int tcr_cur_mode; + + /* Contains the current active receive mode */ + int rcr_cur_mode; + + /* Contains the current active receive/phy mode */ + int rpc_cur_mode; + int ctl_rfduplx; + int ctl_rspeed; + + u32 msg_enable; + u32 phy_type; + struct mii_if_info mii; + + /* work queue */ + struct work_struct phy_configure; + struct net_device *dev; + int work_pending; + + spinlock_t lock; + +#ifdef SMC_USE_PXA_DMA + /* DMA needs the physical address of the chip */ + u_long physaddr; + struct device *device; +#endif + void __iomem *base; + void __iomem *datacs; +}; + + #ifdef SMC_USE_PXA_DMA /* * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is @@ -402,11 +531,12 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #ifdef SMC_insl #undef SMC_insl #define SMC_insl(a, r, p, l) \ - smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) + smc_pxa_dma_insl(a, lp, r, dev->dma, p, l) static inline void -smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, +smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, u_char *buf, int len) { + u_long physaddr = lp->physaddr; dma_addr_t dmabuf; /* fallback if no DMA available */ @@ -423,7 +553,7 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, } len *= 4; - dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); + dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); DCSR(dma) = DCSR_NODESC; DTADR(dma) = dmabuf; DSADR(dma) = physaddr + reg; @@ -433,18 +563,19 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, while (!(DCSR(dma) & DCSR_STOPSTATE)) cpu_relax(); DCSR(dma) = 0; - dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); + dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); } #endif #ifdef SMC_insw #undef SMC_insw #define SMC_insw(a, r, p, l) \ - smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) + smc_pxa_dma_insw(a, lp, r, dev->dma, p, l) static inline void -smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, +smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, u_char *buf, int len) { + u_long physaddr = lp->physaddr; dma_addr_t dmabuf; /* fallback if no DMA available */ @@ -461,7 +592,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, } len *= 2; - dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); + dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); DCSR(dma) = DCSR_NODESC; DTADR(dma) = dmabuf; DSADR(dma) = physaddr + reg; @@ -471,12 +602,12 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, while (!(DCSR(dma) & DCSR_STOPSTATE)) cpu_relax(); DCSR(dma) = 0; - dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); + dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); } #endif static void -smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs) +smc_pxa_dma_irq(int dma, void *dummy) { DCSR(dma) = 0; } @@ -1149,7 +1280,7 @@ static const char * chip_ids[ 16 ] = { if (SMC_CAN_USE_32BIT) { \ void *__ptr = (p); \ int __len = (l); \ - void *__ioaddr = ioaddr; \ + void __iomem *__ioaddr = ioaddr; \ if (__len >= 2 && (unsigned long)__ptr & 2) { \ __len -= 2; \ SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \ @@ -1173,7 +1304,7 @@ static const char * chip_ids[ 16 ] = { if (SMC_CAN_USE_32BIT) { \ void *__ptr = (p); \ int __len = (l); \ - void *__ioaddr = ioaddr; \ + void __iomem *__ioaddr = ioaddr; \ if ((unsigned long)__ptr & 2) { \ /* \ * We want 32bit alignment here. \