X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnx2.h;h=0b032c3c7b611c17cee29b12a62809839a1dae2b;hb=7479a2939df4957ba794cce814379b6d10914bdc;hp=d8e034700c363420e1aef24dd27a01bf56358da8;hpb=b491edd5817f1618f4e06d67638739591a714bdb;p=safe%2Fjmp%2Flinux-2.6 diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index d8e0347..0b032c3 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h @@ -309,6 +309,7 @@ struct l2_fhdr { #endif }; +#define BNX2_RX_OFFSET (sizeof(struct l2_fhdr) + 2) /* * l2_context definition @@ -348,6 +349,12 @@ struct l2_fhdr { #define BNX2_L2CTX_BD_PRE_READ 0x00000000 #define BNX2_L2CTX_CTX_SIZE 0x00000000 #define BNX2_L2CTX_CTX_TYPE 0x00000000 +#define BNX2_L2CTX_LO_WATER_MARK_DEFAULT 32 +#define BNX2_L2CTX_LO_WATER_MARK_SCALE 4 +#define BNX2_L2CTX_LO_WATER_MARK_DIS 0 +#define BNX2_L2CTX_HI_WATER_MARK_SHIFT 4 +#define BNX2_L2CTX_HI_WATER_MARK_SCALE 16 +#define BNX2_L2CTX_WATER_MARKS_MSK 0x000000ff #define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) @@ -371,6 +378,9 @@ struct l2_fhdr { * pci_config_l definition * offset: 0000 */ +#define BNX2_PCICFG_MSI_CONTROL 0x00000058 +#define BNX2_PCICFG_MSI_CONTROL_ENABLE (1L<<16) + #define BNX2_PCICFG_MISC_CONFIG 0x00000068 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) @@ -4151,6 +4161,23 @@ struct l2_fhdr { /* + * rlup_reg definition + * offset: 0x2000 + */ +#define BNX2_RLUP_RSS_CONFIG 0x0000201c +#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI (0x3L<<0) +#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI (0L<<0) +#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI (1L<<0) +#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI (2L<<0) +#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI (3L<<0) +#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI (0x3L<<2) +#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI (0L<<2) +#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI (1L<<2) +#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI (2L<<2) +#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI (3L<<2) + + +/* * rbuf_reg definition * offset: 0x200000 */ @@ -4494,6 +4521,9 @@ struct l2_fhdr { #define BNX2_MQ_MAP_L2_3_ENA (0x1L<<31) #define BNX2_MQ_MAP_L2_3_DEFAULT 0x82004646 +#define BNX2_MQ_MAP_L2_5 0x00003d34 +#define BNX2_MQ_MAP_L2_5_ARM (0x3L<<26) + /* * tsch_reg definition * offset: 0x4c00 @@ -5510,6 +5540,18 @@ struct l2_fhdr { #define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0) #define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16) +#define BNX2_HC_SB_CONFIG_SIZE (BNX2_HC_SB_CONFIG_2 - BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_COMP_PROD_TRIP_OFF (BNX2_HC_COMP_PROD_TRIP_1 - \ + BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_COM_TICKS_OFF (BNX2_HC_COM_TICKS_1 - BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_CMD_TICKS_OFF (BNX2_HC_CMD_TICKS_1 - BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_TX_QUICK_CONS_TRIP_OFF (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \ + BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_TX_TICKS_OFF (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_RX_QUICK_CONS_TRIP_OFF (BNX2_HC_RX_QUICK_CONS_TRIP_1 - \ + BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_RX_TICKS_OFF (BNX2_HC_RX_TICKS_1 - BNX2_HC_SB_CONFIG_1) + /* * txp_reg definition @@ -5837,6 +5879,9 @@ struct l2_fhdr { #define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) #define BNX2_RXP_SCRATCH 0x000e0000 +#define BNX2_RXP_SCRATCH_RSS_TBL_SZ 0x000e0038 +#define BNX2_RXP_SCRATCH_RSS_TBL 0x000e003c +#define BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES 128 /* @@ -6346,11 +6391,12 @@ struct l2_fhdr { #define MII_BNX2_DSP_EXPAND_REG 0x0f00 #define MII_EXPAND_REG1 (MII_BNX2_DSP_EXPAND_REG | 1) #define MII_EXPAND_REG1_RUDI_C 0x20 -#define MII_EXPAND_SERDES_CTL (MII_BNX2_DSP_EXPAND_REG | 2) +#define MII_EXPAND_SERDES_CTL (MII_BNX2_DSP_EXPAND_REG | 3) #define MII_BNX2_MISC_SHADOW 0x1c #define MISC_SHDW_AN_DBG 0x6800 #define MISC_SHDW_AN_DBG_NOSYNC 0x0002 +#define MISC_SHDW_AN_DBG_RUDI_INVALID 0x0100 #define MISC_SHDW_MODE_CTL 0x7c00 #define MISC_SHDW_MODE_CTL_SIG_DET 0x0010 @@ -6393,9 +6439,14 @@ struct l2_fhdr { #define MAX_ETHERNET_PACKET_SIZE 1514 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014 -#define RX_COPY_THRESH 128 +#define BNX2_RX_COPY_THRESH 128 + +#define BNX2_MISC_ENABLE_DEFAULT 0x17ffffff -#define BNX2_MISC_ENABLE_DEFAULT 0x7ffffff +#define BNX2_START_UNICAST_ADDRESS_INDEX 4 +#define BNX2_END_UNICAST_ADDRESS_INDEX 7 +#define BNX2_MAX_UNICAST_ADDRESSES (BNX2_END_UNICAST_ADDRESS_INDEX - \ + BNX2_START_UNICAST_ADDRESS_INDEX + 1) #define DMA_READ_CHANS 5 #define DMA_WRITE_CHANS 3 @@ -6459,6 +6510,11 @@ struct l2_fhdr { #define TX_CID 16 #define TX_TSS_CID 32 #define RX_CID 0 +#define RX_RSS_CID 4 +#define RX_MAX_RSS_RINGS 7 +#define RX_MAX_RINGS (RX_MAX_RSS_RINGS + 1) +#define TX_MAX_TSS_RINGS 7 +#define TX_MAX_RINGS (TX_MAX_TSS_RINGS + 1) #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) @@ -6473,10 +6529,14 @@ struct sw_pg { DECLARE_PCI_UNMAP_ADDR(mapping) }; +struct sw_tx_bd { + struct sk_buff *skb; +}; + #define SW_RXBD_RING_SIZE (sizeof(struct sw_bd) * RX_DESC_CNT) #define SW_RXPG_RING_SIZE (sizeof(struct sw_pg) * RX_DESC_CNT) #define RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) -#define SW_TXBD_RING_SIZE (sizeof(struct sw_bd) * TX_DESC_CNT) +#define SW_TXBD_RING_SIZE (sizeof(struct sw_tx_bd) * TX_DESC_CNT) #define TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) /* Buffered flash (Atmel: AT45DB011B) specific information */ @@ -6537,38 +6597,72 @@ struct flash_spec { }; #define BNX2_MAX_MSIX_HW_VEC 9 -#define BNX2_MAX_MSIX_VEC 2 +#define BNX2_MAX_MSIX_VEC 9 #define BNX2_BASE_VEC 0 #define BNX2_TX_VEC 1 #define BNX2_TX_INT_NUM (BNX2_TX_VEC << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT) struct bnx2_irq { irq_handler_t handler; - u16 vector; + unsigned int vector; u8 requested; char name[16]; }; -struct bnx2_napi { - struct napi_struct napi ____cacheline_aligned; - struct bnx2 *bp; - struct status_block *status_blk; - struct status_block_msix *status_blk_msix; - u32 last_status_idx; - u32 int_num; +struct bnx2_tx_ring_info { + u32 tx_prod_bseq; + u16 tx_prod; + u32 tx_bidx_addr; + u32 tx_bseq_addr; + + struct tx_bd *tx_desc_ring; + struct sw_tx_bd *tx_buf_ring; u16 tx_cons; u16 hw_tx_cons; + dma_addr_t tx_desc_mapping; +}; + +struct bnx2_rx_ring_info { u32 rx_prod_bseq; u16 rx_prod; u16 rx_cons; + u32 rx_bidx_addr; + u32 rx_bseq_addr; + u32 rx_pg_bidx_addr; + u16 rx_pg_prod; u16 rx_pg_cons; + struct sw_bd *rx_buf_ring; + struct rx_bd *rx_desc_ring[MAX_RX_RINGS]; + struct sw_pg *rx_pg_ring; + struct rx_bd *rx_pg_desc_ring[MAX_RX_PG_RINGS]; + + dma_addr_t rx_desc_mapping[MAX_RX_RINGS]; + dma_addr_t rx_pg_desc_mapping[MAX_RX_PG_RINGS]; +}; + +struct bnx2_napi { + struct napi_struct napi ____cacheline_aligned; + struct bnx2 *bp; + union { + struct status_block *msi; + struct status_block_msix *msix; + } status_blk; + u16 *hw_tx_cons_ptr; + u16 *hw_rx_cons_ptr; + u32 last_status_idx; + u32 int_num; + + struct bnx2_rx_ring_info rx_ring; + struct bnx2_tx_ring_info tx_ring; }; +#define BNX2_TIMER_INTERVAL HZ + struct bnx2 { /* Fields used in the tx and intr/napi performance paths are grouped */ /* together in the beginning of the structure. */ @@ -6593,14 +6687,7 @@ struct bnx2 { #define BNX2_FLAG_USING_MSI_OR_MSIX (BNX2_FLAG_USING_MSI | \ BNX2_FLAG_USING_MSIX) #define BNX2_FLAG_JUMBO_BROKEN 0x00000800 - - /* Put tx producer and consumer fields in separate cache lines. */ - - u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES))); - u16 tx_prod; - u8 tx_vec; - u32 tx_bidx_addr; - u32 tx_bseq_addr; +#define BNX2_FLAG_CAN_KEEP_VLAN 0x00001000 struct bnx2_napi bnx2_napi[BNX2_MAX_MSIX_VEC]; @@ -6608,7 +6695,6 @@ struct bnx2 { struct vlan_group *vlgrp; #endif - u32 rx_offset; u32 rx_buf_use_size; /* useable size */ u32 rx_buf_size; /* with alignment */ u32 rx_copy_thresh; @@ -6618,26 +6704,15 @@ struct bnx2 { u32 rx_csum; - struct sw_bd *rx_buf_ring; - struct rx_bd *rx_desc_ring[MAX_RX_RINGS]; - struct sw_pg *rx_pg_ring; - struct rx_bd *rx_pg_desc_ring[MAX_RX_PG_RINGS]; - /* TX constants */ - struct tx_bd *tx_desc_ring; - struct sw_bd *tx_buf_ring; int tx_ring_size; u32 tx_wake_thresh; /* End of fields used in the performance code paths. */ - char *name; - - int timer_interval; int current_interval; struct timer_list timer; struct work_struct reset_task; - int in_reset_task; /* Used to synchronize phy accesses. */ spinlock_t phy_lock; @@ -6654,6 +6729,7 @@ struct bnx2 { #define BNX2_PHY_FLAG_DIS_EARLY_DAC 0x00000400 #define BNX2_PHY_FLAG_REMOTE_PHY_CAP 0x00000800 #define BNX2_PHY_FLAG_FORCED_DOWN 0x00001000 +#define BNX2_PHY_FLAG_NO_PARALLEL 0x00002000 u32 mii_bmcr; u32 mii_bmsr; @@ -6703,16 +6779,11 @@ struct bnx2 { u16 fw_wr_seq; u16 fw_drv_pulse_wr_seq; - dma_addr_t tx_desc_mapping; - - int rx_max_ring; int rx_ring_size; - dma_addr_t rx_desc_mapping[MAX_RX_RINGS]; int rx_max_pg_ring; int rx_pg_ring_size; - dma_addr_t rx_pg_desc_mapping[MAX_RX_PG_RINGS]; u16 tx_quick_cons_trip; u16 tx_quick_cons_trip_int; @@ -6731,7 +6802,6 @@ struct bnx2 { u32 stats_ticks; - struct status_block *status_blk; dma_addr_t status_blk_mapping; struct statistics_block *stats_blk; @@ -6793,10 +6863,13 @@ struct bnx2 { struct bnx2_irq irq_tbl[BNX2_MAX_MSIX_VEC]; int irq_nvecs; -}; -static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset); -static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val); + u8 num_tx_rings; + u8 num_rx_rings; + + u32 idle_chk_status_idx; + +}; #define REG_RD(bp, offset) \ readl(bp->regview + offset) @@ -6807,19 +6880,6 @@ static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val); #define REG_WR16(bp, offset, val) \ writew(val, bp->regview + offset) -#define REG_RD_IND(bp, offset) \ - bnx2_reg_rd_ind(bp, offset) - -#define REG_WR_IND(bp, offset, val) \ - bnx2_reg_wr_ind(bp, offset, val) - -/* Indirect context access. Unlike the MBQ_WR, these macros will not - * trigger a chip event. */ -static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val); - -#define CTX_WR(bp, cid_addr, offset, val) \ - bnx2_ctx_wr(bp, cid_addr, offset, val) - struct cpu_reg { u32 mode; u32 mode_value_halt; @@ -6909,6 +6969,7 @@ struct fw_info { #define BNX2_DRV_MSG_CODE_DIAG 0x07000000 #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 #define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 +#define BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE 0x0d000000 #define BNX2_DRV_MSG_CODE_CMD_SET_LINK 0x10000000 #define BNX2_DRV_MSG_DATA 0x00ff0000 @@ -7237,6 +7298,10 @@ struct fw_info { #define BNX2_FW_CAP_SIGNATURE_MASK 0xffff0000 #define BNX2_FW_CAP_REMOTE_PHY_CAPABLE 0x00000001 #define BNX2_FW_CAP_REMOTE_PHY_PRESENT 0x00000002 +#define BNX2_FW_CAP_MFW_CAN_KEEP_VLAN 0x00000008 +#define BNX2_FW_CAP_BC_CAN_KEEP_VLAN 0x00000010 +#define BNX2_FW_CAP_CAN_KEEP_VLAN (BNX2_FW_CAP_BC_CAN_KEEP_VLAN | \ + BNX2_FW_CAP_MFW_CAN_KEEP_VLAN) #define BNX2_RPHY_SIGNATURE 0x36c #define BNX2_RPHY_LOAD_SIGNATURE 0x5a5a5a5a