X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnx2.c;h=ad61cfd2a9bab131f3a9d4b43b5a63bf883a116e;hb=2aec609fb45e84d65bc8eabc7b650bbecb1cc179;hp=d681f3153e7c266191de7f9434af6edf3be4a712;hpb=543a827d7a5600a71855bd6afacac78536c86822;p=safe%2Fjmp%2Flinux-2.6 diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index d681f31..ad61cfd 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -56,8 +56,8 @@ #define DRV_MODULE_NAME "bnx2" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "1.7.4" -#define DRV_MODULE_RELDATE "February 18, 2008" +#define DRV_MODULE_VERSION "1.7.7" +#define DRV_MODULE_RELDATE "June 17, 2008" #define RUN_AT(x) (jiffies + (x)) @@ -68,7 +68,7 @@ static char version[] __devinitdata = "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; MODULE_AUTHOR("Michael Chan "); -MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver"); +MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709 Driver"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_MODULE_VERSION); @@ -226,7 +226,7 @@ static struct flash_spec flash_5709 = { MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); -static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi) +static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr) { u32 diff; @@ -235,7 +235,7 @@ static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi) /* The ring uses 256 indices for 255 entries, one of them * needs to be skipped. */ - diff = bp->tx_prod - bnapi->tx_cons; + diff = txr->tx_prod - txr->tx_cons; if (unlikely(diff >= TX_DESC_CNT)) { diff &= 0xffff; if (diff == TX_DESC_CNT) @@ -496,99 +496,162 @@ bnx2_netif_start(struct bnx2 *bp) } static void -bnx2_free_mem(struct bnx2 *bp) +bnx2_free_tx_mem(struct bnx2 *bp) { int i; - for (i = 0; i < bp->ctx_pages; i++) { - if (bp->ctx_blk[i]) { - pci_free_consistent(bp->pdev, BCM_PAGE_SIZE, - bp->ctx_blk[i], - bp->ctx_blk_mapping[i]); - bp->ctx_blk[i] = NULL; + for (i = 0; i < bp->num_tx_rings; i++) { + struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; + struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; + + if (txr->tx_desc_ring) { + pci_free_consistent(bp->pdev, TXBD_RING_SIZE, + txr->tx_desc_ring, + txr->tx_desc_mapping); + txr->tx_desc_ring = NULL; } + kfree(txr->tx_buf_ring); + txr->tx_buf_ring = NULL; } - if (bp->status_blk) { - pci_free_consistent(bp->pdev, bp->status_stats_size, - bp->status_blk, bp->status_blk_mapping); - bp->status_blk = NULL; - bp->stats_blk = NULL; +} + +static void +bnx2_free_rx_mem(struct bnx2 *bp) +{ + int i; + + for (i = 0; i < bp->num_rx_rings; i++) { + struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; + struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; + int j; + + for (j = 0; j < bp->rx_max_ring; j++) { + if (rxr->rx_desc_ring[j]) + pci_free_consistent(bp->pdev, RXBD_RING_SIZE, + rxr->rx_desc_ring[j], + rxr->rx_desc_mapping[j]); + rxr->rx_desc_ring[j] = NULL; + } + if (rxr->rx_buf_ring) + vfree(rxr->rx_buf_ring); + rxr->rx_buf_ring = NULL; + + for (j = 0; j < bp->rx_max_pg_ring; j++) { + if (rxr->rx_pg_desc_ring[j]) + pci_free_consistent(bp->pdev, RXBD_RING_SIZE, + rxr->rx_pg_desc_ring[i], + rxr->rx_pg_desc_mapping[i]); + rxr->rx_pg_desc_ring[i] = NULL; + } + if (rxr->rx_pg_ring) + vfree(rxr->rx_pg_ring); + rxr->rx_pg_ring = NULL; } - if (bp->tx_desc_ring) { - pci_free_consistent(bp->pdev, TXBD_RING_SIZE, - bp->tx_desc_ring, bp->tx_desc_mapping); - bp->tx_desc_ring = NULL; - } - kfree(bp->tx_buf_ring); - bp->tx_buf_ring = NULL; - for (i = 0; i < bp->rx_max_ring; i++) { - if (bp->rx_desc_ring[i]) - pci_free_consistent(bp->pdev, RXBD_RING_SIZE, - bp->rx_desc_ring[i], - bp->rx_desc_mapping[i]); - bp->rx_desc_ring[i] = NULL; - } - vfree(bp->rx_buf_ring); - bp->rx_buf_ring = NULL; - for (i = 0; i < bp->rx_max_pg_ring; i++) { - if (bp->rx_pg_desc_ring[i]) - pci_free_consistent(bp->pdev, RXBD_RING_SIZE, - bp->rx_pg_desc_ring[i], - bp->rx_pg_desc_mapping[i]); - bp->rx_pg_desc_ring[i] = NULL; - } - if (bp->rx_pg_ring) - vfree(bp->rx_pg_ring); - bp->rx_pg_ring = NULL; } static int -bnx2_alloc_mem(struct bnx2 *bp) +bnx2_alloc_tx_mem(struct bnx2 *bp) { - int i, status_blk_size; + int i; - bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); - if (bp->tx_buf_ring == NULL) - return -ENOMEM; + for (i = 0; i < bp->num_tx_rings; i++) { + struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; + struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; - bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE, - &bp->tx_desc_mapping); - if (bp->tx_desc_ring == NULL) - goto alloc_mem_err; + txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); + if (txr->tx_buf_ring == NULL) + return -ENOMEM; - bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring); - if (bp->rx_buf_ring == NULL) - goto alloc_mem_err; + txr->tx_desc_ring = + pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE, + &txr->tx_desc_mapping); + if (txr->tx_desc_ring == NULL) + return -ENOMEM; + } + return 0; +} - memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring); +static int +bnx2_alloc_rx_mem(struct bnx2 *bp) +{ + int i; - for (i = 0; i < bp->rx_max_ring; i++) { - bp->rx_desc_ring[i] = - pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE, - &bp->rx_desc_mapping[i]); - if (bp->rx_desc_ring[i] == NULL) - goto alloc_mem_err; + for (i = 0; i < bp->num_rx_rings; i++) { + struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; + struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; + int j; - } + rxr->rx_buf_ring = + vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring); + if (rxr->rx_buf_ring == NULL) + return -ENOMEM; - if (bp->rx_pg_ring_size) { - bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE * - bp->rx_max_pg_ring); - if (bp->rx_pg_ring == NULL) - goto alloc_mem_err; + memset(rxr->rx_buf_ring, 0, + SW_RXBD_RING_SIZE * bp->rx_max_ring); + + for (j = 0; j < bp->rx_max_ring; j++) { + rxr->rx_desc_ring[j] = + pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE, + &rxr->rx_desc_mapping[j]); + if (rxr->rx_desc_ring[j] == NULL) + return -ENOMEM; + + } - memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE * - bp->rx_max_pg_ring); + if (bp->rx_pg_ring_size) { + rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE * + bp->rx_max_pg_ring); + if (rxr->rx_pg_ring == NULL) + return -ENOMEM; + + memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE * + bp->rx_max_pg_ring); + } + + for (j = 0; j < bp->rx_max_pg_ring; j++) { + rxr->rx_pg_desc_ring[j] = + pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE, + &rxr->rx_pg_desc_mapping[j]); + if (rxr->rx_pg_desc_ring[j] == NULL) + return -ENOMEM; + + } } + return 0; +} + +static void +bnx2_free_mem(struct bnx2 *bp) +{ + int i; + struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; - for (i = 0; i < bp->rx_max_pg_ring; i++) { - bp->rx_pg_desc_ring[i] = - pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE, - &bp->rx_pg_desc_mapping[i]); - if (bp->rx_pg_desc_ring[i] == NULL) - goto alloc_mem_err; + bnx2_free_tx_mem(bp); + bnx2_free_rx_mem(bp); + for (i = 0; i < bp->ctx_pages; i++) { + if (bp->ctx_blk[i]) { + pci_free_consistent(bp->pdev, BCM_PAGE_SIZE, + bp->ctx_blk[i], + bp->ctx_blk_mapping[i]); + bp->ctx_blk[i] = NULL; + } } + if (bnapi->status_blk.msi) { + pci_free_consistent(bp->pdev, bp->status_stats_size, + bnapi->status_blk.msi, + bp->status_blk_mapping); + bnapi->status_blk.msi = NULL; + bp->stats_blk = NULL; + } +} + +static int +bnx2_alloc_mem(struct bnx2 *bp) +{ + int i, status_blk_size, err; + struct bnx2_napi *bnapi; + void *status_blk; /* Combine status and statistics blocks into one allocation. */ status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); @@ -598,27 +661,37 @@ bnx2_alloc_mem(struct bnx2 *bp) bp->status_stats_size = status_blk_size + sizeof(struct statistics_block); - bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size, - &bp->status_blk_mapping); - if (bp->status_blk == NULL) + status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size, + &bp->status_blk_mapping); + if (status_blk == NULL) goto alloc_mem_err; - memset(bp->status_blk, 0, bp->status_stats_size); + memset(status_blk, 0, bp->status_stats_size); - bp->bnx2_napi[0].status_blk = bp->status_blk; + bnapi = &bp->bnx2_napi[0]; + bnapi->status_blk.msi = status_blk; + bnapi->hw_tx_cons_ptr = + &bnapi->status_blk.msi->status_tx_quick_consumer_index0; + bnapi->hw_rx_cons_ptr = + &bnapi->status_blk.msi->status_rx_quick_consumer_index0; if (bp->flags & BNX2_FLAG_MSIX_CAP) { for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) { - struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; + struct status_block_msix *sblk; + + bnapi = &bp->bnx2_napi[i]; - bnapi->status_blk_msix = (void *) - ((unsigned long) bp->status_blk + - BNX2_SBLK_MSIX_ALIGN_SIZE * i); + sblk = (void *) (status_blk + + BNX2_SBLK_MSIX_ALIGN_SIZE * i); + bnapi->status_blk.msix = sblk; + bnapi->hw_tx_cons_ptr = + &sblk->status_tx_quick_consumer_index; + bnapi->hw_rx_cons_ptr = + &sblk->status_rx_quick_consumer_index; bnapi->int_num = i << 24; } } - bp->stats_blk = (void *) ((unsigned long) bp->status_blk + - status_blk_size); + bp->stats_blk = status_blk + status_blk_size; bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; @@ -634,6 +707,15 @@ bnx2_alloc_mem(struct bnx2 *bp) goto alloc_mem_err; } } + + err = bnx2_alloc_rx_mem(bp); + if (err) + goto alloc_mem_err; + + err = bnx2_alloc_tx_mem(bp); + if (err) + goto alloc_mem_err; + return 0; alloc_mem_err: @@ -993,9 +1075,9 @@ bnx2_copper_linkup(struct bnx2 *bp) } static void -bnx2_init_rx_context0(struct bnx2 *bp) +bnx2_init_rx_context(struct bnx2 *bp, u32 cid) { - u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID); + u32 val, rx_cid_addr = GET_CID_ADDR(cid); val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; @@ -1028,6 +1110,19 @@ bnx2_init_rx_context0(struct bnx2 *bp) bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); } +static void +bnx2_init_all_rx_contexts(struct bnx2 *bp) +{ + int i; + u32 cid; + + for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { + if (i == 1) + cid = RX_RSS_CID; + bnx2_init_rx_context(bp, cid); + } +} + static int bnx2_set_mac_link(struct bnx2 *bp) { @@ -1093,7 +1188,7 @@ bnx2_set_mac_link(struct bnx2 *bp) REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); if (CHIP_NUM(bp) == CHIP_NUM_5709) - bnx2_init_rx_context0(bp); + bnx2_init_all_rx_contexts(bp); return 0; } @@ -1875,7 +1970,7 @@ bnx2_setup_phy(struct bnx2 *bp, u8 port) } static int -bnx2_init_5709s_phy(struct bnx2 *bp) +bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy) { u32 val; @@ -1890,7 +1985,8 @@ bnx2_init_5709s_phy(struct bnx2 *bp) bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); - bnx2_reset_phy(bp); + if (reset_phy) + bnx2_reset_phy(bp); bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); @@ -1924,11 +2020,12 @@ bnx2_init_5709s_phy(struct bnx2 *bp) } static int -bnx2_init_5708s_phy(struct bnx2 *bp) +bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy) { u32 val; - bnx2_reset_phy(bp); + if (reset_phy) + bnx2_reset_phy(bp); bp->mii_up1 = BCM5708S_UP1; @@ -1981,9 +2078,10 @@ bnx2_init_5708s_phy(struct bnx2 *bp) } static int -bnx2_init_5706s_phy(struct bnx2 *bp) +bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy) { - bnx2_reset_phy(bp); + if (reset_phy) + bnx2_reset_phy(bp); bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; @@ -2018,11 +2116,12 @@ bnx2_init_5706s_phy(struct bnx2 *bp) } static int -bnx2_init_copper_phy(struct bnx2 *bp) +bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy) { u32 val; - bnx2_reset_phy(bp); + if (reset_phy) + bnx2_reset_phy(bp); if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { bnx2_write_phy(bp, 0x18, 0x0c00); @@ -2070,7 +2169,7 @@ bnx2_init_copper_phy(struct bnx2 *bp) static int -bnx2_init_phy(struct bnx2 *bp) +bnx2_init_phy(struct bnx2 *bp, int reset_phy) { u32 val; int rc = 0; @@ -2096,14 +2195,14 @@ bnx2_init_phy(struct bnx2 *bp) if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { if (CHIP_NUM(bp) == CHIP_NUM_5706) - rc = bnx2_init_5706s_phy(bp); + rc = bnx2_init_5706s_phy(bp, reset_phy); else if (CHIP_NUM(bp) == CHIP_NUM_5708) - rc = bnx2_init_5708s_phy(bp); + rc = bnx2_init_5708s_phy(bp, reset_phy); else if (CHIP_NUM(bp) == CHIP_NUM_5709) - rc = bnx2_init_5709s_phy(bp); + rc = bnx2_init_5709s_phy(bp, reset_phy); } else { - rc = bnx2_init_copper_phy(bp); + rc = bnx2_init_copper_phy(bp, reset_phy); } setup_phy: @@ -2222,6 +2321,11 @@ bnx2_init_5709_context(struct bnx2 *bp) for (i = 0; i < bp->ctx_pages; i++) { int j; + if (bp->ctx_blk[i]) + memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE); + else + return -ENOMEM; + REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0, (bp->ctx_blk_mapping[i] & 0xffffffff) | BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID); @@ -2356,12 +2460,12 @@ bnx2_set_mac_addr(struct bnx2 *bp) } static inline int -bnx2_alloc_rx_page(struct bnx2 *bp, u16 index) +bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) { dma_addr_t mapping; - struct sw_pg *rx_pg = &bp->rx_pg_ring[index]; + struct sw_pg *rx_pg = &rxr->rx_pg_ring[index]; struct rx_bd *rxbd = - &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)]; + &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)]; struct page *page = alloc_page(GFP_ATOMIC); if (!page) @@ -2376,9 +2480,9 @@ bnx2_alloc_rx_page(struct bnx2 *bp, u16 index) } static void -bnx2_free_rx_page(struct bnx2 *bp, u16 index) +bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) { - struct sw_pg *rx_pg = &bp->rx_pg_ring[index]; + struct sw_pg *rx_pg = &rxr->rx_pg_ring[index]; struct page *page = rx_pg->page; if (!page) @@ -2392,12 +2496,12 @@ bnx2_free_rx_page(struct bnx2 *bp, u16 index) } static inline int -bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index) +bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) { struct sk_buff *skb; - struct sw_bd *rx_buf = &bp->rx_buf_ring[index]; + struct sw_bd *rx_buf = &rxr->rx_buf_ring[index]; dma_addr_t mapping; - struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)]; + struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)]; unsigned long align; skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size); @@ -2417,7 +2521,7 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index) rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; - bnapi->rx_prod_bseq += bp->rx_buf_use_size; + rxr->rx_prod_bseq += bp->rx_buf_use_size; return 0; } @@ -2425,7 +2529,7 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index) static int bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event) { - struct status_block *sblk = bnapi->status_blk; + struct status_block *sblk = bnapi->status_blk.msi; u32 new_link_state, old_link_state; int is_set = 1; @@ -2461,11 +2565,9 @@ bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi) { u16 cons; - if (bnapi->int_num == 0) - cons = bnapi->status_blk->status_tx_quick_consumer_index0; - else - cons = bnapi->status_blk_msix->status_tx_quick_consumer_index; - + /* Tell compiler that status block fields can change. */ + barrier(); + cons = *bnapi->hw_tx_cons_ptr; if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT)) cons++; return cons; @@ -2474,11 +2576,12 @@ bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi) static int bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) { + struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; u16 hw_cons, sw_cons, sw_ring_cons; int tx_pkt = 0; hw_cons = bnx2_get_hw_tx_cons(bnapi); - sw_cons = bnapi->tx_cons; + sw_cons = txr->tx_cons; while (sw_cons != hw_cons) { struct sw_bd *tx_buf; @@ -2487,7 +2590,7 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) sw_ring_cons = TX_RING_IDX(sw_cons); - tx_buf = &bp->tx_buf_ring[sw_ring_cons]; + tx_buf = &txr->tx_buf_ring[sw_ring_cons]; skb = tx_buf->skb; /* partial BD completions possible with TSO packets */ @@ -2517,7 +2620,7 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) pci_unmap_page(bp->pdev, pci_unmap_addr( - &bp->tx_buf_ring[TX_RING_IDX(sw_cons)], + &txr->tx_buf_ring[TX_RING_IDX(sw_cons)], mapping), skb_shinfo(skb)->frags[i].size, PCI_DMA_TODEVICE); @@ -2533,8 +2636,8 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) hw_cons = bnx2_get_hw_tx_cons(bnapi); } - bnapi->hw_tx_cons = hw_cons; - bnapi->tx_cons = sw_cons; + txr->hw_tx_cons = hw_cons; + txr->tx_cons = sw_cons; /* Need to make the tx_cons update visible to bnx2_start_xmit() * before checking for netif_queue_stopped(). Without the * memory barrier, there is a small possibility that bnx2_start_xmit() @@ -2543,10 +2646,10 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) smp_mb(); if (unlikely(netif_queue_stopped(bp->dev)) && - (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) { + (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) { netif_tx_lock(bp->dev); if ((netif_queue_stopped(bp->dev)) && - (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) + (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) netif_wake_queue(bp->dev); netif_tx_unlock(bp->dev); } @@ -2554,23 +2657,23 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) } static void -bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi, +bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb, int count) { struct sw_pg *cons_rx_pg, *prod_rx_pg; struct rx_bd *cons_bd, *prod_bd; dma_addr_t mapping; int i; - u16 hw_prod = bnapi->rx_pg_prod, prod; - u16 cons = bnapi->rx_pg_cons; + u16 hw_prod = rxr->rx_pg_prod, prod; + u16 cons = rxr->rx_pg_cons; for (i = 0; i < count; i++) { prod = RX_PG_RING_IDX(hw_prod); - prod_rx_pg = &bp->rx_pg_ring[prod]; - cons_rx_pg = &bp->rx_pg_ring[cons]; - cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)]; - prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; + prod_rx_pg = &rxr->rx_pg_ring[prod]; + cons_rx_pg = &rxr->rx_pg_ring[cons]; + cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)]; + prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; if (i == 0 && skb) { struct page *page; @@ -2599,25 +2702,25 @@ bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi, cons = RX_PG_RING_IDX(NEXT_RX_BD(cons)); hw_prod = NEXT_RX_BD(hw_prod); } - bnapi->rx_pg_prod = hw_prod; - bnapi->rx_pg_cons = cons; + rxr->rx_pg_prod = hw_prod; + rxr->rx_pg_cons = cons; } static inline void -bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, - u16 cons, u16 prod) +bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, + struct sk_buff *skb, u16 cons, u16 prod) { struct sw_bd *cons_rx_buf, *prod_rx_buf; struct rx_bd *cons_bd, *prod_bd; - cons_rx_buf = &bp->rx_buf_ring[cons]; - prod_rx_buf = &bp->rx_buf_ring[prod]; + cons_rx_buf = &rxr->rx_buf_ring[cons]; + prod_rx_buf = &rxr->rx_buf_ring[prod]; pci_dma_sync_single_for_device(bp->pdev, pci_unmap_addr(cons_rx_buf, mapping), - bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); + BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE); - bnapi->rx_prod_bseq += bp->rx_buf_use_size; + rxr->rx_prod_bseq += bp->rx_buf_use_size; prod_rx_buf->skb = skb; @@ -2627,33 +2730,33 @@ bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, pci_unmap_addr_set(prod_rx_buf, mapping, pci_unmap_addr(cons_rx_buf, mapping)); - cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; - prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; + cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; + prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; } static int -bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, +bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb, unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr, u32 ring_idx) { int err; u16 prod = ring_idx & 0xffff; - err = bnx2_alloc_rx_skb(bp, bnapi, prod); + err = bnx2_alloc_rx_skb(bp, rxr, prod); if (unlikely(err)) { - bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod); + bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod); if (hdr_len) { unsigned int raw_len = len + 4; int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT; - bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages); + bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); } return err; } - skb_reserve(skb, bp->rx_offset); + skb_reserve(skb, BNX2_RX_OFFSET); pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); @@ -2663,8 +2766,8 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, } else { unsigned int i, frag_len, frag_size, pages; struct sw_pg *rx_pg; - u16 pg_cons = bnapi->rx_pg_cons; - u16 pg_prod = bnapi->rx_pg_prod; + u16 pg_cons = rxr->rx_pg_cons; + u16 pg_prod = rxr->rx_pg_prod; frag_size = len + 4 - hdr_len; pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT; @@ -2675,9 +2778,9 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, if (unlikely(frag_len <= 4)) { unsigned int tail = 4 - frag_len; - bnapi->rx_pg_cons = pg_cons; - bnapi->rx_pg_prod = pg_prod; - bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, + rxr->rx_pg_cons = pg_cons; + rxr->rx_pg_prod = pg_prod; + bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages - i); skb->len -= tail; if (i == 0) { @@ -2691,7 +2794,7 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, } return 0; } - rx_pg = &bp->rx_pg_ring[pg_cons]; + rx_pg = &rxr->rx_pg_ring[pg_cons]; pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE, PCI_DMA_FROMDEVICE); @@ -2702,11 +2805,12 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); rx_pg->page = NULL; - err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod)); + err = bnx2_alloc_rx_page(bp, rxr, + RX_PG_RING_IDX(pg_prod)); if (unlikely(err)) { - bnapi->rx_pg_cons = pg_cons; - bnapi->rx_pg_prod = pg_prod; - bnx2_reuse_rx_skb_pages(bp, bnapi, skb, + rxr->rx_pg_cons = pg_cons; + rxr->rx_pg_prod = pg_prod; + bnx2_reuse_rx_skb_pages(bp, rxr, skb, pages - i); return err; } @@ -2719,8 +2823,8 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, pg_prod = NEXT_RX_BD(pg_prod); pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons)); } - bnapi->rx_pg_prod = pg_prod; - bnapi->rx_pg_cons = pg_cons; + rxr->rx_pg_prod = pg_prod; + rxr->rx_pg_cons = pg_cons; } return 0; } @@ -2728,8 +2832,11 @@ bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb, static inline u16 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi) { - u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0; + u16 cons; + /* Tell compiler that status block fields can change. */ + barrier(); + cons = *bnapi->hw_rx_cons_ptr; if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)) cons++; return cons; @@ -2738,13 +2845,14 @@ bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi) static int bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) { + struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; struct l2_fhdr *rx_hdr; int rx_pkt = 0, pg_ring_used = 0; hw_cons = bnx2_get_hw_rx_cons(bnapi); - sw_cons = bnapi->rx_cons; - sw_prod = bnapi->rx_prod; + sw_cons = rxr->rx_cons; + sw_prod = rxr->rx_prod; /* Memory barrier necessary as speculative reads of the rx * buffer can be ahead of the index in the status block @@ -2760,7 +2868,7 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) sw_ring_cons = RX_RING_IDX(sw_cons); sw_ring_prod = RX_RING_IDX(sw_prod); - rx_buf = &bp->rx_buf_ring[sw_ring_cons]; + rx_buf = &rxr->rx_buf_ring[sw_ring_cons]; skb = rx_buf->skb; rx_buf->skb = NULL; @@ -2768,7 +2876,8 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) dma_addr = pci_unmap_addr(rx_buf, mapping); pci_dma_sync_single_for_cpu(bp->pdev, dma_addr, - bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); + BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, + PCI_DMA_FROMDEVICE); rx_hdr = (struct l2_fhdr *) skb->data; len = rx_hdr->l2_fhdr_pkt_len; @@ -2780,7 +2889,7 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { - bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons, + bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons, sw_ring_prod); goto next_rx; } @@ -2800,22 +2909,23 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) new_skb = netdev_alloc_skb(bp->dev, len + 2); if (new_skb == NULL) { - bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons, + bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons, sw_ring_prod); goto next_rx; } /* aligned copy */ - skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2, + skb_copy_from_linear_data_offset(skb, + BNX2_RX_OFFSET - 2, new_skb->data, len + 2); skb_reserve(new_skb, 2); skb_put(new_skb, len); - bnx2_reuse_rx_skb(bp, bnapi, skb, + bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons, sw_ring_prod); skb = new_skb; - } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len, + } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len, dma_addr, (sw_ring_cons << 16) | sw_ring_prod))) goto next_rx; @@ -2864,16 +2974,15 @@ next_rx: rmb(); } } - bnapi->rx_cons = sw_cons; - bnapi->rx_prod = sw_prod; + rxr->rx_cons = sw_cons; + rxr->rx_prod = sw_prod; if (pg_ring_used) - REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX, - bnapi->rx_pg_prod); + REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); - REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod); + REG_WR16(bp, rxr->rx_bidx_addr, sw_prod); - REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq); + REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); mmiowb(); @@ -2887,11 +2996,11 @@ next_rx: static irqreturn_t bnx2_msi(int irq, void *dev_instance) { - struct net_device *dev = dev_instance; - struct bnx2 *bp = netdev_priv(dev); - struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; + struct bnx2_napi *bnapi = dev_instance; + struct bnx2 *bp = bnapi->bp; + struct net_device *dev = bp->dev; - prefetch(bnapi->status_blk); + prefetch(bnapi->status_blk.msi); REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); @@ -2908,11 +3017,11 @@ bnx2_msi(int irq, void *dev_instance) static irqreturn_t bnx2_msi_1shot(int irq, void *dev_instance) { - struct net_device *dev = dev_instance; - struct bnx2 *bp = netdev_priv(dev); - struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; + struct bnx2_napi *bnapi = dev_instance; + struct bnx2 *bp = bnapi->bp; + struct net_device *dev = bp->dev; - prefetch(bnapi->status_blk); + prefetch(bnapi->status_blk.msi); /* Return here if interrupt is disabled. */ if (unlikely(atomic_read(&bp->intr_sem) != 0)) @@ -2926,10 +3035,10 @@ bnx2_msi_1shot(int irq, void *dev_instance) static irqreturn_t bnx2_interrupt(int irq, void *dev_instance) { - struct net_device *dev = dev_instance; - struct bnx2 *bp = netdev_priv(dev); - struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; - struct status_block *sblk = bnapi->status_blk; + struct bnx2_napi *bnapi = dev_instance; + struct bnx2 *bp = bnapi->bp; + struct net_device *dev = bp->dev; + struct status_block *sblk = bnapi->status_blk.msi; /* When using INTx, it is possible for the interrupt to arrive * at the CPU before the status block posted prior to the @@ -2963,21 +3072,16 @@ bnx2_interrupt(int irq, void *dev_instance) return IRQ_HANDLED; } -static irqreturn_t -bnx2_tx_msix(int irq, void *dev_instance) +static inline int +bnx2_has_fast_work(struct bnx2_napi *bnapi) { - struct net_device *dev = dev_instance; - struct bnx2 *bp = netdev_priv(dev); - struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC]; - - prefetch(bnapi->status_blk_msix); - - /* Return here if interrupt is disabled. */ - if (unlikely(atomic_read(&bp->intr_sem) != 0)) - return IRQ_HANDLED; + struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; + struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; - netif_rx_schedule(dev, &bnapi->napi); - return IRQ_HANDLED; + if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) || + (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)) + return 1; + return 0; } #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \ @@ -2986,10 +3090,9 @@ bnx2_tx_msix(int irq, void *dev_instance) static inline int bnx2_has_work(struct bnx2_napi *bnapi) { - struct status_block *sblk = bnapi->status_blk; + struct status_block *sblk = bnapi->status_blk.msi; - if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) || - (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)) + if (bnx2_has_fast_work(bnapi)) return 1; if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != @@ -2999,33 +3102,9 @@ bnx2_has_work(struct bnx2_napi *bnapi) return 0; } -static int bnx2_tx_poll(struct napi_struct *napi, int budget) +static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi) { - struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); - struct bnx2 *bp = bnapi->bp; - int work_done = 0; - struct status_block_msix *sblk = bnapi->status_blk_msix; - - do { - work_done += bnx2_tx_int(bp, bnapi, budget - work_done); - if (unlikely(work_done >= budget)) - return work_done; - - bnapi->last_status_idx = sblk->status_idx; - rmb(); - } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons); - - netif_rx_complete(bp->dev, napi); - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | - BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | - bnapi->last_status_idx); - return work_done; -} - -static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi, - int work_done, int budget) -{ - struct status_block *sblk = bnapi->status_blk; + struct status_block *sblk = bnapi->status_blk.msi; u32 status_attn_bits = sblk->status_attn_bits; u32 status_attn_bits_ack = sblk->status_attn_bits_ack; @@ -3041,24 +3120,60 @@ static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); REG_RD(bp, BNX2_HC_COMMAND); } +} + +static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi, + int work_done, int budget) +{ + struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; + struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; - if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons) + if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons) bnx2_tx_int(bp, bnapi, 0); - if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) + if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) work_done += bnx2_rx_int(bp, bnapi, budget - work_done); return work_done; } +static int bnx2_poll_msix(struct napi_struct *napi, int budget) +{ + struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); + struct bnx2 *bp = bnapi->bp; + int work_done = 0; + struct status_block_msix *sblk = bnapi->status_blk.msix; + + while (1) { + work_done = bnx2_poll_work(bp, bnapi, work_done, budget); + if (unlikely(work_done >= budget)) + break; + + bnapi->last_status_idx = sblk->status_idx; + /* status idx must be read before checking for more work. */ + rmb(); + if (likely(!bnx2_has_fast_work(bnapi))) { + + netif_rx_complete(bp->dev, napi); + REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | + BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | + bnapi->last_status_idx); + break; + } + } + return work_done; +} + static int bnx2_poll(struct napi_struct *napi, int budget) { struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); struct bnx2 *bp = bnapi->bp; int work_done = 0; - struct status_block *sblk = bnapi->status_blk; + struct status_block *sblk = bnapi->status_blk.msi; while (1) { + bnx2_poll_link(bp, bnapi); + work_done = bnx2_poll_work(bp, bnapi, work_done, budget); if (unlikely(work_done >= budget)) @@ -3175,6 +3290,12 @@ load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len, int i; u32 val; + if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) { + val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]); + val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK; + val |= XI_RV2P_PROC2_BD_PAGE_SIZE; + rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val); + } for (i = 0; i < rv2p_code_len; i += 8) { REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code)); @@ -3202,7 +3323,7 @@ load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len, } static int -load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) +load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw) { u32 offset; u32 val; @@ -3286,7 +3407,6 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) static int bnx2_init_cpus(struct bnx2 *bp) { - struct cpu_reg cpu_reg; struct fw_info *fw; int rc, rv2p_len; void *text, *rv2p; @@ -3322,122 +3442,57 @@ bnx2_init_cpus(struct bnx2 *bp) load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2); /* Initialize the RX Processor. */ - cpu_reg.mode = BNX2_RXP_CPU_MODE; - cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT; - cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA; - cpu_reg.state = BNX2_RXP_CPU_STATE; - cpu_reg.state_value_clear = 0xffffff; - cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE; - cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK; - cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER; - cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION; - cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT; - cpu_reg.spad_base = BNX2_RXP_SCRATCH; - cpu_reg.mips_view_base = 0x8000000; - if (CHIP_NUM(bp) == CHIP_NUM_5709) fw = &bnx2_rxp_fw_09; else fw = &bnx2_rxp_fw_06; fw->text = text; - rc = load_cpu_fw(bp, &cpu_reg, fw); + rc = load_cpu_fw(bp, &cpu_reg_rxp, fw); if (rc) goto init_cpu_err; /* Initialize the TX Processor. */ - cpu_reg.mode = BNX2_TXP_CPU_MODE; - cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT; - cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA; - cpu_reg.state = BNX2_TXP_CPU_STATE; - cpu_reg.state_value_clear = 0xffffff; - cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE; - cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK; - cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER; - cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION; - cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT; - cpu_reg.spad_base = BNX2_TXP_SCRATCH; - cpu_reg.mips_view_base = 0x8000000; - if (CHIP_NUM(bp) == CHIP_NUM_5709) fw = &bnx2_txp_fw_09; else fw = &bnx2_txp_fw_06; fw->text = text; - rc = load_cpu_fw(bp, &cpu_reg, fw); + rc = load_cpu_fw(bp, &cpu_reg_txp, fw); if (rc) goto init_cpu_err; /* Initialize the TX Patch-up Processor. */ - cpu_reg.mode = BNX2_TPAT_CPU_MODE; - cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT; - cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA; - cpu_reg.state = BNX2_TPAT_CPU_STATE; - cpu_reg.state_value_clear = 0xffffff; - cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE; - cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK; - cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER; - cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION; - cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT; - cpu_reg.spad_base = BNX2_TPAT_SCRATCH; - cpu_reg.mips_view_base = 0x8000000; - if (CHIP_NUM(bp) == CHIP_NUM_5709) fw = &bnx2_tpat_fw_09; else fw = &bnx2_tpat_fw_06; fw->text = text; - rc = load_cpu_fw(bp, &cpu_reg, fw); + rc = load_cpu_fw(bp, &cpu_reg_tpat, fw); if (rc) goto init_cpu_err; /* Initialize the Completion Processor. */ - cpu_reg.mode = BNX2_COM_CPU_MODE; - cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT; - cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA; - cpu_reg.state = BNX2_COM_CPU_STATE; - cpu_reg.state_value_clear = 0xffffff; - cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE; - cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK; - cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER; - cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION; - cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT; - cpu_reg.spad_base = BNX2_COM_SCRATCH; - cpu_reg.mips_view_base = 0x8000000; - if (CHIP_NUM(bp) == CHIP_NUM_5709) fw = &bnx2_com_fw_09; else fw = &bnx2_com_fw_06; fw->text = text; - rc = load_cpu_fw(bp, &cpu_reg, fw); + rc = load_cpu_fw(bp, &cpu_reg_com, fw); if (rc) goto init_cpu_err; /* Initialize the Command Processor. */ - cpu_reg.mode = BNX2_CP_CPU_MODE; - cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT; - cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA; - cpu_reg.state = BNX2_CP_CPU_STATE; - cpu_reg.state_value_clear = 0xffffff; - cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE; - cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK; - cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER; - cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION; - cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT; - cpu_reg.spad_base = BNX2_CP_SCRATCH; - cpu_reg.mips_view_base = 0x8000000; - if (CHIP_NUM(bp) == CHIP_NUM_5709) fw = &bnx2_cp_fw_09; else fw = &bnx2_cp_fw_06; fw->text = text; - rc = load_cpu_fw(bp, &cpu_reg, fw); + rc = load_cpu_fw(bp, &cpu_reg_cp, fw); init_cpu_err: vfree(text); @@ -4487,15 +4542,25 @@ bnx2_init_chip(struct bnx2 *bp) BNX2_HC_CONFIG_COLLECT_STATS; } - if (bp->flags & BNX2_FLAG_USING_MSIX) { - u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) + - BNX2_HC_SB_CONFIG_1; - + if (bp->irq_nvecs > 1) { REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, BNX2_HC_MSIX_BIT_VECTOR_VAL); + val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; + } + + if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) + val |= BNX2_HC_CONFIG_ONE_SHOT; + + REG_WR(bp, BNX2_HC_CONFIG, val); + + for (i = 1; i < bp->irq_nvecs; i++) { + u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) + + BNX2_HC_SB_CONFIG_1; + REG_WR(bp, base, BNX2_HC_SB_CONFIG_1_TX_TMR_MODE | + BNX2_HC_SB_CONFIG_1_RX_TMR_MODE | BNX2_HC_SB_CONFIG_1_ONE_SHOT); REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, @@ -4505,13 +4570,13 @@ bnx2_init_chip(struct bnx2 *bp) REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF, (bp->tx_ticks_int << 16) | bp->tx_ticks); - val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; - } - - if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) - val |= BNX2_HC_CONFIG_ONE_SHOT; + REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF, + (bp->rx_quick_cons_trip_int << 16) | + bp->rx_quick_cons_trip); - REG_WR(bp, BNX2_HC_CONFIG, val); + REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF, + (bp->rx_ticks_int << 16) | bp->rx_ticks); + } /* Clear internal stats counters. */ REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); @@ -4543,23 +4608,27 @@ static void bnx2_clear_ring_states(struct bnx2 *bp) { struct bnx2_napi *bnapi; + struct bnx2_tx_ring_info *txr; + struct bnx2_rx_ring_info *rxr; int i; for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { bnapi = &bp->bnx2_napi[i]; + txr = &bnapi->tx_ring; + rxr = &bnapi->rx_ring; - bnapi->tx_cons = 0; - bnapi->hw_tx_cons = 0; - bnapi->rx_prod_bseq = 0; - bnapi->rx_prod = 0; - bnapi->rx_cons = 0; - bnapi->rx_pg_prod = 0; - bnapi->rx_pg_cons = 0; + txr->tx_cons = 0; + txr->hw_tx_cons = 0; + rxr->rx_prod_bseq = 0; + rxr->rx_prod = 0; + rxr->rx_cons = 0; + rxr->rx_pg_prod = 0; + rxr->rx_pg_cons = 0; } } static void -bnx2_init_tx_context(struct bnx2 *bp, u32 cid) +bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr) { u32 val, offset0, offset1, offset2, offset3; u32 cid_addr = GET_CID_ADDR(cid); @@ -4581,43 +4650,43 @@ bnx2_init_tx_context(struct bnx2 *bp, u32 cid) val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); bnx2_ctx_wr(bp, cid_addr, offset1, val); - val = (u64) bp->tx_desc_mapping >> 32; + val = (u64) txr->tx_desc_mapping >> 32; bnx2_ctx_wr(bp, cid_addr, offset2, val); - val = (u64) bp->tx_desc_mapping & 0xffffffff; + val = (u64) txr->tx_desc_mapping & 0xffffffff; bnx2_ctx_wr(bp, cid_addr, offset3, val); } static void -bnx2_init_tx_ring(struct bnx2 *bp) +bnx2_init_tx_ring(struct bnx2 *bp, int ring_num) { struct tx_bd *txbd; u32 cid = TX_CID; struct bnx2_napi *bnapi; + struct bnx2_tx_ring_info *txr; - bp->tx_vec = 0; - if (bp->flags & BNX2_FLAG_USING_MSIX) { - cid = TX_TSS_CID; - bp->tx_vec = BNX2_TX_VEC; - REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM | - (TX_TSS_CID << 7)); - } - bnapi = &bp->bnx2_napi[bp->tx_vec]; + bnapi = &bp->bnx2_napi[ring_num]; + txr = &bnapi->tx_ring; + + if (ring_num == 0) + cid = TX_CID; + else + cid = TX_TSS_CID + ring_num - 1; bp->tx_wake_thresh = bp->tx_ring_size / 2; - txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT]; + txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT]; - txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32; - txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff; + txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32; + txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; - bp->tx_prod = 0; - bp->tx_prod_bseq = 0; + txr->tx_prod = 0; + txr->tx_prod_bseq = 0; - bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; - bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; + txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; + txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; - bnx2_init_tx_context(bp, cid); + bnx2_init_tx_context(bp, cid, txr); } static void @@ -4645,17 +4714,25 @@ bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size, } static void -bnx2_init_rx_ring(struct bnx2 *bp) +bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) { int i; u16 prod, ring_prod; - u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID); - struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; + u32 cid, rx_cid_addr, val; + struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num]; + struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; + + if (ring_num == 0) + cid = RX_CID; + else + cid = RX_RSS_CID + ring_num - 1; - bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping, + rx_cid_addr = GET_CID_ADDR(cid); + + bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping, bp->rx_buf_use_size, bp->rx_max_ring); - bnx2_init_rx_context0(bp); + bnx2_init_rx_context(bp, cid); if (CHIP_NUM(bp) == CHIP_NUM_5709) { val = REG_RD(bp, BNX2_MQ_MAP_L2_5); @@ -4664,54 +4741,101 @@ bnx2_init_rx_ring(struct bnx2 *bp) bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); if (bp->rx_pg_ring_size) { - bnx2_init_rxbd_rings(bp->rx_pg_desc_ring, - bp->rx_pg_desc_mapping, + bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring, + rxr->rx_pg_desc_mapping, PAGE_SIZE, bp->rx_max_pg_ring); val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, - BNX2_L2CTX_RBDC_JUMBO_KEY); + BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num); - val = (u64) bp->rx_pg_desc_mapping[0] >> 32; + val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); - val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff; + val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); if (CHIP_NUM(bp) == CHIP_NUM_5709) REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); } - val = (u64) bp->rx_desc_mapping[0] >> 32; + val = (u64) rxr->rx_desc_mapping[0] >> 32; bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); - val = (u64) bp->rx_desc_mapping[0] & 0xffffffff; + val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); - ring_prod = prod = bnapi->rx_pg_prod; + ring_prod = prod = rxr->rx_pg_prod; for (i = 0; i < bp->rx_pg_ring_size; i++) { - if (bnx2_alloc_rx_page(bp, ring_prod) < 0) + if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0) break; prod = NEXT_RX_BD(prod); ring_prod = RX_PG_RING_IDX(prod); } - bnapi->rx_pg_prod = prod; + rxr->rx_pg_prod = prod; - ring_prod = prod = bnapi->rx_prod; + ring_prod = prod = rxr->rx_prod; for (i = 0; i < bp->rx_ring_size; i++) { - if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) { + if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0) break; - } prod = NEXT_RX_BD(prod); ring_prod = RX_RING_IDX(prod); } - bnapi->rx_prod = prod; + rxr->rx_prod = prod; + + rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX; + rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ; + rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX; - REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX, - bnapi->rx_pg_prod); - REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod); + REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); + REG_WR16(bp, rxr->rx_bidx_addr, prod); - REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq); + REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); +} + +static void +bnx2_init_all_rings(struct bnx2 *bp) +{ + int i; + u32 val; + + bnx2_clear_ring_states(bp); + + REG_WR(bp, BNX2_TSCH_TSS_CFG, 0); + for (i = 0; i < bp->num_tx_rings; i++) + bnx2_init_tx_ring(bp, i); + + if (bp->num_tx_rings > 1) + REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) | + (TX_TSS_CID << 7)); + + REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0); + bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0); + + for (i = 0; i < bp->num_rx_rings; i++) + bnx2_init_rx_ring(bp, i); + + if (bp->num_rx_rings > 1) { + u32 tbl_32; + u8 *tbl = (u8 *) &tbl_32; + + bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, + BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES); + + for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) { + tbl[i % 4] = i % (bp->num_rx_rings - 1); + if ((i % 4) == 3) + bnx2_reg_wr_ind(bp, + BNX2_RXP_SCRATCH_RSS_TBL + i, + cpu_to_be32(tbl_32)); + } + + val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI | + BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI; + + REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val); + + } } static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size) @@ -4739,12 +4863,12 @@ bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) u32 rx_size, rx_space, jumbo_size; /* 8 for CRC and VLAN */ - rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8; + rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8; rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD + sizeof(struct skb_shared_info); - bp->rx_copy_thresh = RX_COPY_THRESH; + bp->rx_copy_thresh = BNX2_RX_COPY_THRESH; bp->rx_pg_ring_size = 0; bp->rx_max_pg_ring = 0; bp->rx_max_pg_ring_idx = 0; @@ -4759,14 +4883,14 @@ bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, MAX_RX_PG_RINGS); bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1; - rx_size = RX_COPY_THRESH + bp->rx_offset; + rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET; bp->rx_copy_thresh = 0; } bp->rx_buf_use_size = rx_size; /* hw alignment */ bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN; - bp->rx_jumbo_thresh = rx_size - bp->rx_offset; + bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET; bp->rx_ring_size = size; bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS); bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1; @@ -4777,36 +4901,42 @@ bnx2_free_tx_skbs(struct bnx2 *bp) { int i; - if (bp->tx_buf_ring == NULL) - return; - - for (i = 0; i < TX_DESC_CNT; ) { - struct sw_bd *tx_buf = &bp->tx_buf_ring[i]; - struct sk_buff *skb = tx_buf->skb; - int j, last; + for (i = 0; i < bp->num_tx_rings; i++) { + struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; + struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; + int j; - if (skb == NULL) { - i++; + if (txr->tx_buf_ring == NULL) continue; - } - pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping), + for (j = 0; j < TX_DESC_CNT; ) { + struct sw_bd *tx_buf = &txr->tx_buf_ring[j]; + struct sk_buff *skb = tx_buf->skb; + int k, last; + + if (skb == NULL) { + j++; + continue; + } + + pci_unmap_single(bp->pdev, + pci_unmap_addr(tx_buf, mapping), skb_headlen(skb), PCI_DMA_TODEVICE); - tx_buf->skb = NULL; + tx_buf->skb = NULL; - last = skb_shinfo(skb)->nr_frags; - for (j = 0; j < last; j++) { - tx_buf = &bp->tx_buf_ring[i + j + 1]; - pci_unmap_page(bp->pdev, - pci_unmap_addr(tx_buf, mapping), - skb_shinfo(skb)->frags[j].size, - PCI_DMA_TODEVICE); + last = skb_shinfo(skb)->nr_frags; + for (k = 0; k < last; k++) { + tx_buf = &txr->tx_buf_ring[j + k + 1]; + pci_unmap_page(bp->pdev, + pci_unmap_addr(tx_buf, mapping), + skb_shinfo(skb)->frags[j].size, + PCI_DMA_TODEVICE); + } + dev_kfree_skb(skb); + j += k + 1; } - dev_kfree_skb(skb); - i += j + 1; } - } static void @@ -4814,25 +4944,33 @@ bnx2_free_rx_skbs(struct bnx2 *bp) { int i; - if (bp->rx_buf_ring == NULL) - return; + for (i = 0; i < bp->num_rx_rings; i++) { + struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; + struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; + int j; - for (i = 0; i < bp->rx_max_ring_idx; i++) { - struct sw_bd *rx_buf = &bp->rx_buf_ring[i]; - struct sk_buff *skb = rx_buf->skb; + if (rxr->rx_buf_ring == NULL) + return; - if (skb == NULL) - continue; + for (j = 0; j < bp->rx_max_ring_idx; j++) { + struct sw_bd *rx_buf = &rxr->rx_buf_ring[j]; + struct sk_buff *skb = rx_buf->skb; - pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping), - bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); + if (skb == NULL) + continue; - rx_buf->skb = NULL; + pci_unmap_single(bp->pdev, + pci_unmap_addr(rx_buf, mapping), + bp->rx_buf_use_size, + PCI_DMA_FROMDEVICE); - dev_kfree_skb(skb); + rx_buf->skb = NULL; + + dev_kfree_skb(skb); + } + for (j = 0; j < bp->rx_max_pg_ring_idx; j++) + bnx2_free_rx_page(bp, rxr, j); } - for (i = 0; i < bp->rx_max_pg_ring_idx; i++) - bnx2_free_rx_page(bp, i); } static void @@ -4855,14 +4993,12 @@ bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) if ((rc = bnx2_init_chip(bp)) != 0) return rc; - bnx2_clear_ring_states(bp); - bnx2_init_tx_ring(bp); - bnx2_init_rx_ring(bp); + bnx2_init_all_rings(bp); return 0; } static int -bnx2_init_nic(struct bnx2 *bp) +bnx2_init_nic(struct bnx2 *bp, int reset_phy) { int rc; @@ -4870,7 +5006,7 @@ bnx2_init_nic(struct bnx2 *bp) return rc; spin_lock_bh(&bp->phy_lock); - bnx2_init_phy(bp); + bnx2_init_phy(bp, reset_phy); bnx2_set_link(bp); if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) bnx2_remote_phy_event(bp); @@ -4916,7 +5052,7 @@ bnx2_test_registers(struct bnx2 *bp) { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 }, { 0x1000, 0, 0x00000000, 0x00000001 }, - { 0x1004, 0, 0x00000000, 0x000f0001 }, + { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 }, { 0x1408, 0, 0x01c00800, 0x00000000 }, { 0x149c, 0, 0x8000ffff, 0x00000000 }, @@ -5130,11 +5266,13 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) struct l2_fhdr *rx_hdr; int ret = -ENODEV; struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; + struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; + struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; tx_napi = bnapi; - if (bp->flags & BNX2_FLAG_USING_MSIX) - tx_napi = &bp->bnx2_napi[BNX2_TX_VEC]; + txr = &tx_napi->tx_ring; + rxr = &bnapi->rx_ring; if (loopback_mode == BNX2_MAC_LOOPBACK) { bp->loopback = MAC_LOOPBACK; bnx2_set_mac_loopback(bp); @@ -5172,7 +5310,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) num_pkts = 0; - txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)]; + txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)]; txbd->tx_bd_haddr_hi = (u64) map >> 32; txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; @@ -5180,11 +5318,11 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; num_pkts++; - bp->tx_prod = NEXT_TX_BD(bp->tx_prod); - bp->tx_prod_bseq += pkt_size; + txr->tx_prod = NEXT_TX_BD(txr->tx_prod); + txr->tx_prod_bseq += pkt_size; - REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod); - REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); + REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); + REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); udelay(100); @@ -5198,7 +5336,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE); dev_kfree_skb(skb); - if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod) + if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod) goto loopback_test_done; rx_idx = bnx2_get_hw_rx_cons(bnapi); @@ -5206,11 +5344,11 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) goto loopback_test_done; } - rx_buf = &bp->rx_buf_ring[rx_start_idx]; + rx_buf = &rxr->rx_buf_ring[rx_start_idx]; rx_skb = rx_buf->skb; rx_hdr = (struct l2_fhdr *) rx_skb->data; - skb_reserve(rx_skb, bp->rx_offset); + skb_reserve(rx_skb, BNX2_RX_OFFSET); pci_dma_sync_single_for_cpu(bp->pdev, pci_unmap_addr(rx_buf, mapping), @@ -5258,7 +5396,7 @@ bnx2_test_loopback(struct bnx2 *bp) bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); spin_lock_bh(&bp->phy_lock); - bnx2_init_phy(bp); + bnx2_init_phy(bp, 1); spin_unlock_bh(&bp->phy_lock); if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK)) rc |= BNX2_MAC_LOOPBACK_FAILED; @@ -5520,7 +5658,6 @@ bnx2_restart_timer: static int bnx2_request_irq(struct bnx2 *bp) { - struct net_device *dev = bp->dev; unsigned long flags; struct bnx2_irq *irq; int rc = 0, i; @@ -5533,7 +5670,7 @@ bnx2_request_irq(struct bnx2 *bp) for (i = 0; i < bp->irq_nvecs; i++) { irq = &bp->irq_tbl[i]; rc = request_irq(irq->vector, irq->handler, flags, irq->name, - dev); + &bp->bnx2_napi[i]); if (rc) break; irq->requested = 1; @@ -5544,14 +5681,13 @@ bnx2_request_irq(struct bnx2 *bp) static void bnx2_free_irq(struct bnx2 *bp) { - struct net_device *dev = bp->dev; struct bnx2_irq *irq; int i; for (i = 0; i < bp->irq_nvecs; i++) { irq = &bp->irq_tbl[i]; if (irq->requested) - free_irq(irq->vector, dev); + free_irq(irq->vector, &bp->bnx2_napi[i]); irq->requested = 0; } if (bp->flags & BNX2_FLAG_USING_MSI) @@ -5563,7 +5699,7 @@ bnx2_free_irq(struct bnx2 *bp) } static void -bnx2_enable_msix(struct bnx2 *bp) +bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) { int i, rc; struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC]; @@ -5576,21 +5712,16 @@ bnx2_enable_msix(struct bnx2 *bp) for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { msix_ent[i].entry = i; msix_ent[i].vector = 0; + + strcpy(bp->irq_tbl[i].name, bp->dev->name); + bp->irq_tbl[i].handler = bnx2_msi_1shot; } rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC); if (rc != 0) return; - bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot; - bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix; - - strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name); - strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base"); - strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name); - strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx"); - - bp->irq_nvecs = BNX2_MAX_MSIX_VEC; + bp->irq_nvecs = msix_vecs; bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) bp->irq_tbl[i].vector = msix_ent[i].vector; @@ -5599,13 +5730,16 @@ bnx2_enable_msix(struct bnx2 *bp) static void bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) { + int cpus = num_online_cpus(); + int msix_vecs = min(cpus + 1, RX_MAX_RSS_RINGS); + bp->irq_tbl[0].handler = bnx2_interrupt; strcpy(bp->irq_tbl[0].name, bp->dev->name); bp->irq_nvecs = 1; bp->irq_tbl[0].vector = bp->pdev->irq; - if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi) - bnx2_enable_msix(bp); + if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1) + bnx2_enable_msix(bp, msix_vecs); if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi && !(bp->flags & BNX2_FLAG_USING_MSIX)) { @@ -5620,6 +5754,8 @@ bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) bp->irq_tbl[0].vector = bp->pdev->irq; } } + bp->num_tx_rings = 1; + bp->num_rx_rings = bp->irq_nvecs; } /* Called with rtnl_lock */ @@ -5634,29 +5770,19 @@ bnx2_open(struct net_device *dev) bnx2_set_power_state(bp, PCI_D0); bnx2_disable_int(bp); + bnx2_setup_int_mode(bp, disable_msi); + bnx2_napi_enable(bp); rc = bnx2_alloc_mem(bp); if (rc) - return rc; + goto open_err; - bnx2_setup_int_mode(bp, disable_msi); - bnx2_napi_enable(bp); rc = bnx2_request_irq(bp); + if (rc) + goto open_err; - if (rc) { - bnx2_napi_disable(bp); - bnx2_free_mem(bp); - return rc; - } - - rc = bnx2_init_nic(bp); - - if (rc) { - bnx2_napi_disable(bp); - bnx2_free_irq(bp); - bnx2_free_skbs(bp); - bnx2_free_mem(bp); - return rc; - } + rc = bnx2_init_nic(bp, 1); + if (rc) + goto open_err; mod_timer(&bp->timer, jiffies + bp->current_interval); @@ -5680,17 +5806,14 @@ bnx2_open(struct net_device *dev) bnx2_setup_int_mode(bp, 1); - rc = bnx2_init_nic(bp); + rc = bnx2_init_nic(bp, 0); if (!rc) rc = bnx2_request_irq(bp); if (rc) { - bnx2_napi_disable(bp); - bnx2_free_skbs(bp); - bnx2_free_mem(bp); del_timer_sync(&bp->timer); - return rc; + goto open_err; } bnx2_enable_int(bp); } @@ -5703,6 +5826,13 @@ bnx2_open(struct net_device *dev) netif_start_queue(dev); return 0; + +open_err: + bnx2_napi_disable(bp); + bnx2_free_skbs(bp); + bnx2_free_irq(bp); + bnx2_free_mem(bp); + return rc; } static void @@ -5713,14 +5843,12 @@ bnx2_reset_task(struct work_struct *work) if (!netif_running(bp->dev)) return; - bp->in_reset_task = 1; bnx2_netif_stop(bp); - bnx2_init_nic(bp); + bnx2_init_nic(bp, 1); atomic_set(&bp->intr_sem, 1); bnx2_netif_start(bp); - bp->in_reset_task = 0; } static void @@ -5762,9 +5890,10 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) u32 len, vlan_tag_flags, last_frag, mss; u16 prod, ring_prod; int i; - struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec]; + struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; + struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; - if (unlikely(bnx2_tx_avail(bp, bnapi) < + if (unlikely(bnx2_tx_avail(bp, txr) < (skb_shinfo(skb)->nr_frags + 1))) { netif_stop_queue(dev); printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n", @@ -5773,7 +5902,7 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) return NETDEV_TX_BUSY; } len = skb_headlen(skb); - prod = bp->tx_prod; + prod = txr->tx_prod; ring_prod = TX_RING_IDX(prod); vlan_tag_flags = 0; @@ -5835,11 +5964,11 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE); - tx_buf = &bp->tx_buf_ring[ring_prod]; + tx_buf = &txr->tx_buf_ring[ring_prod]; tx_buf->skb = skb; pci_unmap_addr_set(tx_buf, mapping, mapping); - txbd = &bp->tx_desc_ring[ring_prod]; + txbd = &txr->tx_desc_ring[ring_prod]; txbd->tx_bd_haddr_hi = (u64) mapping >> 32; txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; @@ -5853,12 +5982,12 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) prod = NEXT_TX_BD(prod); ring_prod = TX_RING_IDX(prod); - txbd = &bp->tx_desc_ring[ring_prod]; + txbd = &txr->tx_desc_ring[ring_prod]; len = frag->size; mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset, len, PCI_DMA_TODEVICE); - pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod], + pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping, mapping); txbd->tx_bd_haddr_hi = (u64) mapping >> 32; @@ -5870,19 +5999,19 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; prod = NEXT_TX_BD(prod); - bp->tx_prod_bseq += skb->len; + txr->tx_prod_bseq += skb->len; - REG_WR16(bp, bp->tx_bidx_addr, prod); - REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); + REG_WR16(bp, txr->tx_bidx_addr, prod); + REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); mmiowb(); - bp->tx_prod = prod; + txr->tx_prod = prod; dev->trans_start = jiffies; - if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) { + if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) { netif_stop_queue(dev); - if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh) + if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh) netif_wake_queue(dev); } @@ -5896,12 +6025,7 @@ bnx2_close(struct net_device *dev) struct bnx2 *bp = netdev_priv(dev); u32 reset_code; - /* Calling flush_scheduled_work() may deadlock because - * linkwatch_event() may be on the workqueue and it will try to get - * the rtnl_lock which we are holding. - */ - while (bp->in_reset_task) - msleep(1); + cancel_work_sync(&bp->reset_task); bnx2_disable_int_sync(bp); bnx2_napi_disable(bp); @@ -6410,7 +6534,7 @@ bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) if (netif_running(bp->dev)) { bnx2_netif_stop(bp); - bnx2_init_nic(bp); + bnx2_init_nic(bp, 0); bnx2_netif_start(bp); } @@ -6453,7 +6577,7 @@ bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx) rc = bnx2_alloc_mem(bp); if (rc) return rc; - bnx2_init_nic(bp); + bnx2_init_nic(bp, 0); bnx2_netif_start(bp); } return 0; @@ -6721,7 +6845,7 @@ bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); } else { - bnx2_init_nic(bp); + bnx2_init_nic(bp, 1); bnx2_netif_start(bp); } @@ -7104,6 +7228,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) } pci_set_master(pdev); + pci_save_state(pdev); bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); if (bp->pm_cap == 0) { @@ -7290,8 +7415,6 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->mac_addr[4] = (u8) (reg >> 8); bp->mac_addr[5] = (u8) reg; - bp->rx_offset = sizeof(struct l2_fhdr) + 2; - bp->tx_ring_size = MAX_TX_DESC_CNT; bnx2_set_rx_ring_size(bp, 255); @@ -7447,15 +7570,19 @@ static void __devinit bnx2_init_napi(struct bnx2 *bp) { int i; - struct bnx2_napi *bnapi; for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { - bnapi = &bp->bnx2_napi[i]; + struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; + int (*poll)(struct napi_struct *, int); + + if (i == 0) + poll = bnx2_poll; + else + poll = bnx2_poll_msix; + + netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64); bnapi->bp = bp; } - netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64); - netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll, - 64); } static int __devinit @@ -7608,11 +7735,97 @@ bnx2_resume(struct pci_dev *pdev) bnx2_set_power_state(bp, PCI_D0); netif_device_attach(dev); - bnx2_init_nic(bp); + bnx2_init_nic(bp, 1); bnx2_netif_start(bp); return 0; } +/** + * bnx2_io_error_detected - called when PCI error is detected + * @pdev: Pointer to PCI device + * @state: The current pci connection state + * + * This function is called after a PCI bus error affecting + * this device has been detected. + */ +static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + struct net_device *dev = pci_get_drvdata(pdev); + struct bnx2 *bp = netdev_priv(dev); + + rtnl_lock(); + netif_device_detach(dev); + + if (netif_running(dev)) { + bnx2_netif_stop(bp); + del_timer_sync(&bp->timer); + bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); + } + + pci_disable_device(pdev); + rtnl_unlock(); + + /* Request a slot slot reset. */ + return PCI_ERS_RESULT_NEED_RESET; +} + +/** + * bnx2_io_slot_reset - called after the pci bus has been reset. + * @pdev: Pointer to PCI device + * + * Restart the card from scratch, as if from a cold-boot. + */ +static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev) +{ + struct net_device *dev = pci_get_drvdata(pdev); + struct bnx2 *bp = netdev_priv(dev); + + rtnl_lock(); + if (pci_enable_device(pdev)) { + dev_err(&pdev->dev, + "Cannot re-enable PCI device after reset.\n"); + rtnl_unlock(); + return PCI_ERS_RESULT_DISCONNECT; + } + pci_set_master(pdev); + pci_restore_state(pdev); + + if (netif_running(dev)) { + bnx2_set_power_state(bp, PCI_D0); + bnx2_init_nic(bp, 1); + } + + rtnl_unlock(); + return PCI_ERS_RESULT_RECOVERED; +} + +/** + * bnx2_io_resume - called when traffic can start flowing again. + * @pdev: Pointer to PCI device + * + * This callback is called when the error recovery driver tells us that + * its OK to resume normal operation. + */ +static void bnx2_io_resume(struct pci_dev *pdev) +{ + struct net_device *dev = pci_get_drvdata(pdev); + struct bnx2 *bp = netdev_priv(dev); + + rtnl_lock(); + if (netif_running(dev)) + bnx2_netif_start(bp); + + netif_device_attach(dev); + rtnl_unlock(); +} + +static struct pci_error_handlers bnx2_err_handler = { + .error_detected = bnx2_io_error_detected, + .slot_reset = bnx2_io_slot_reset, + .resume = bnx2_io_resume, +}; + static struct pci_driver bnx2_pci_driver = { .name = DRV_MODULE_NAME, .id_table = bnx2_pci_tbl, @@ -7620,6 +7833,7 @@ static struct pci_driver bnx2_pci_driver = { .remove = __devexit_p(bnx2_remove_one), .suspend = bnx2_suspend, .resume = bnx2_resume, + .err_handler = &bnx2_err_handler, }; static int __init bnx2_init(void)