X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnx2.c;h=8b552c6dd2e7b053248eff254abc103cbef38e87;hb=6e01d1a4b2f7110201e7fe16e561a721d76fab3e;hp=255197be35c1751c97b72b05ac6908e39508c8c7;hpb=583c28e5645c464b57b4f5d3d53113c06bb0ac5f;p=safe%2Fjmp%2Flinux-2.6 diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 255197b..8b552c6 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -56,8 +56,8 @@ #define DRV_MODULE_NAME "bnx2" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "1.7.2" -#define DRV_MODULE_RELDATE "January 21, 2008" +#define DRV_MODULE_VERSION "1.7.3" +#define DRV_MODULE_RELDATE "January 29, 2008" #define RUN_AT(x) (jiffies + (x)) @@ -266,6 +266,18 @@ bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) } static void +bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val) +{ + bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); +} + +static u32 +bnx2_shmem_rd(struct bnx2 *bp, u32 offset) +{ + return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset)); +} + +static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) { offset += cid_addr; @@ -685,7 +697,7 @@ bnx2_report_fw_link(struct bnx2 *bp) else fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; - REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status); + bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status); } static char * @@ -980,6 +992,42 @@ bnx2_copper_linkup(struct bnx2 *bp) return 0; } +static void +bnx2_init_rx_context0(struct bnx2 *bp) +{ + u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID); + + val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; + val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; + val |= 0x02 << 8; + + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + u32 lo_water, hi_water; + + if (bp->flow_ctrl & FLOW_CTRL_TX) + lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT; + else + lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS; + if (lo_water >= bp->rx_ring_size) + lo_water = 0; + + hi_water = bp->rx_ring_size / 4; + + if (hi_water <= lo_water) + lo_water = 0; + + hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE; + lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE; + + if (hi_water > 0xf) + hi_water = 0xf; + else if (hi_water == 0) + lo_water = 0; + val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT); + } + bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); +} + static int bnx2_set_mac_link(struct bnx2 *bp) { @@ -1044,6 +1092,9 @@ bnx2_set_mac_link(struct bnx2 *bp) /* Acknowledge the interrupt. */ REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); + if (CHIP_NUM(bp) == CHIP_NUM_5709) + bnx2_init_rx_context0(bp); + return 0; } @@ -1378,14 +1429,14 @@ bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP)) speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE; - if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM)) + if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM)) speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE; if (port == PORT_TP) speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE | BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED; - REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg); + bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg); spin_unlock_bh(&bp->phy_lock); bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0); @@ -1530,9 +1581,9 @@ bnx2_set_default_remote_link(struct bnx2 *bp) u32 link; if (bp->phy_port == PORT_TP) - link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK); + link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK); else - link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK); + link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK); if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) { bp->req_line_speed = 0; @@ -1584,7 +1635,7 @@ bnx2_set_default_link(struct bnx2 *bp) bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; - reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG); + reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG); reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { bp->autoneg = 0; @@ -1616,7 +1667,7 @@ bnx2_remote_phy_event(struct bnx2 *bp) u8 link_up = bp->link_up; u8 old_port; - msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS); + msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED) bnx2_send_heart_beat(bp); @@ -1693,7 +1744,7 @@ bnx2_set_remote_link(struct bnx2 *bp) { u32 evt_code; - evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB); + evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB); switch (evt_code) { case BNX2_FW_EVT_CODE_LINK_EVENT: bnx2_remote_phy_event(bp); @@ -1905,14 +1956,13 @@ bnx2_init_5708s_phy(struct bnx2 *bp) bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); } - val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) & + val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) & BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK; if (val) { u32 is_backplane; - is_backplane = REG_RD_IND(bp, bp->shmem_base + - BNX2_SHARED_HW_CFG_CONFIG); + is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) { bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_TX_MISC); @@ -2111,13 +2161,13 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent) bp->fw_wr_seq++; msg_data |= bp->fw_wr_seq; - REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data); + bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); /* wait for an acknowledgement. */ for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) { msleep(10); - val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB); + val = bnx2_shmem_rd(bp, BNX2_FW_MB); if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) break; @@ -2134,7 +2184,7 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent) msg_data &= ~BNX2_DRV_MSG_CODE; msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; - REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data); + bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); return -EBUSY; } @@ -2226,7 +2276,7 @@ bnx2_init_context(struct bnx2 *bp) /* Zero out the context. */ for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) - CTX_WR(bp, vcid_addr, offset, 0); + bnx2_ctx_wr(bp, vcid_addr, offset, 0); } } } @@ -2251,11 +2301,12 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp) good_mbuf_cnt = 0; /* Allocate a bunch of mbufs and save the good ones in an array. */ - val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); + val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { - REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ); + bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND, + BNX2_RBUF_COMMAND_ALLOC_REQ); - val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC); + val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC); val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; @@ -2265,7 +2316,7 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp) good_mbuf_cnt++; } - val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); + val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); } /* Free the good ones back to the mbuf pool thus discarding @@ -2276,7 +2327,7 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp) val = good_mbuf[good_mbuf_cnt]; val = (val << 9) | val | 1; - REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val); + bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val); } kfree(good_mbuf); return 0; @@ -3111,7 +3162,7 @@ bnx2_set_rx_mode(struct net_device *dev) } static void -load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, +load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len, u32 rv2p_proc) { int i; @@ -3119,9 +3170,9 @@ load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, for (i = 0; i < rv2p_code_len; i += 8) { - REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code)); + REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code)); rv2p_code++; - REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code)); + REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code)); rv2p_code++; if (rv2p_proc == RV2P_PROC1) { @@ -3151,10 +3202,10 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) int rc; /* Halt the CPU. */ - val = REG_RD_IND(bp, cpu_reg->mode); + val = bnx2_reg_rd_ind(bp, cpu_reg->mode); val |= cpu_reg->mode_value_halt; - REG_WR_IND(bp, cpu_reg->mode, val); - REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); + bnx2_reg_wr_ind(bp, cpu_reg->mode, val); + bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); /* Load the Text area. */ offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); @@ -3167,7 +3218,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) return rc; for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { - REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j])); + bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j])); } } @@ -3177,7 +3228,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) int j; for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { - REG_WR_IND(bp, offset, fw->data[j]); + bnx2_reg_wr_ind(bp, offset, fw->data[j]); } } @@ -3187,7 +3238,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) int j; for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { - REG_WR_IND(bp, offset, 0); + bnx2_reg_wr_ind(bp, offset, 0); } } @@ -3197,7 +3248,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) int j; for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { - REG_WR_IND(bp, offset, 0); + bnx2_reg_wr_ind(bp, offset, 0); } } @@ -3208,19 +3259,19 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) int j; for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { - REG_WR_IND(bp, offset, fw->rodata[j]); + bnx2_reg_wr_ind(bp, offset, fw->rodata[j]); } } /* Clear the pre-fetch instruction. */ - REG_WR_IND(bp, cpu_reg->inst, 0); - REG_WR_IND(bp, cpu_reg->pc, fw->start_addr); + bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); + bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr); /* Start the CPU. */ - val = REG_RD_IND(bp, cpu_reg->mode); + val = bnx2_reg_rd_ind(bp, cpu_reg->mode); val &= ~cpu_reg->mode_value_halt; - REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); - REG_WR_IND(bp, cpu_reg->mode, val); + bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); + bnx2_reg_wr_ind(bp, cpu_reg->mode, val); return 0; } @@ -3704,10 +3755,8 @@ bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) val = REG_RD(bp, BNX2_NVM_COMMAND); if (val & BNX2_NVM_COMMAND_DONE) { - val = REG_RD(bp, BNX2_NVM_READ); - - val = be32_to_cpu(val); - memcpy(ret_val, &val, 4); + __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ)); + memcpy(ret_val, &v, 4); break; } } @@ -3721,7 +3770,8 @@ bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) static int bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) { - u32 cmd, val32; + u32 cmd; + __be32 val32; int j; /* Build the command word. */ @@ -3738,10 +3788,9 @@ bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); memcpy(&val32, val, 4); - val32 = cpu_to_be32(val32); /* Write the data. */ - REG_WR(bp, BNX2_NVM_WRITE, val32); + REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32)); /* Address of the NVRAM to write to. */ REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); @@ -3835,7 +3884,7 @@ bnx2_init_nvram(struct bnx2 *bp) } get_flash_size: - val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2); + val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2); val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; if (val) bp->flash_size = val; @@ -4144,14 +4193,14 @@ bnx2_init_remote_phy(struct bnx2 *bp) if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) return; - val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB); + val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB); if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) return; if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) { bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; - val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS); + val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); if (val & BNX2_LINK_STATUS_SERDES_LINK) bp->phy_port = PORT_FIBRE; else @@ -4169,8 +4218,7 @@ bnx2_init_remote_phy(struct bnx2 *bp) } sig = BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_REMOTE_PHY_CAPABLE; - REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB, - sig); + bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig); } } } @@ -4206,8 +4254,8 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) /* Deposit a driver reset signature so the firmware knows that * this is a soft reset. */ - REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE, - BNX2_DRV_RESET_SIGNATURE_MAGIC); + bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE, + BNX2_DRV_RESET_SIGNATURE_MAGIC); /* Do a dummy read to force the chip to complete all current transaction * before we issue a reset. */ @@ -4440,18 +4488,21 @@ bnx2_init_chip(struct bnx2 *bp) } if (bp->flags & BNX2_FLAG_USING_MSIX) { + u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) + + BNX2_HC_SB_CONFIG_1; + REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, BNX2_HC_MSIX_BIT_VECTOR_VAL); - REG_WR(bp, BNX2_HC_SB_CONFIG_1, + REG_WR(bp, base, BNX2_HC_SB_CONFIG_1_TX_TMR_MODE | BNX2_HC_SB_CONFIG_1_ONE_SHOT); - REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP_1, + REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); - REG_WR(bp, BNX2_HC_TX_TICKS_1, + REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF, (bp->tx_ticks_int << 16) | bp->tx_ticks); val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; @@ -4511,6 +4562,7 @@ static void bnx2_init_tx_context(struct bnx2 *bp, u32 cid) { u32 val, offset0, offset1, offset2, offset3; + u32 cid_addr = GET_CID_ADDR(cid); if (CHIP_NUM(bp) == CHIP_NUM_5709) { offset0 = BNX2_L2CTX_TYPE_XI; @@ -4524,16 +4576,16 @@ bnx2_init_tx_context(struct bnx2 *bp, u32 cid) offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; } val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; - CTX_WR(bp, GET_CID_ADDR(cid), offset0, val); + bnx2_ctx_wr(bp, cid_addr, offset0, val); val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); - CTX_WR(bp, GET_CID_ADDR(cid), offset1, val); + bnx2_ctx_wr(bp, cid_addr, offset1, val); val = (u64) bp->tx_desc_mapping >> 32; - CTX_WR(bp, GET_CID_ADDR(cid), offset2, val); + bnx2_ctx_wr(bp, cid_addr, offset2, val); val = (u64) bp->tx_desc_mapping & 0xffffffff; - CTX_WR(bp, GET_CID_ADDR(cid), offset3, val); + bnx2_ctx_wr(bp, cid_addr, offset3, val); } static void @@ -4603,36 +4655,38 @@ bnx2_init_rx_ring(struct bnx2 *bp) bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping, bp->rx_buf_use_size, bp->rx_max_ring); - CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); + bnx2_init_rx_context0(bp); + + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + val = REG_RD(bp, BNX2_MQ_MAP_L2_5); + REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); + } + + bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); if (bp->rx_pg_ring_size) { bnx2_init_rxbd_rings(bp->rx_pg_desc_ring, bp->rx_pg_desc_mapping, PAGE_SIZE, bp->rx_max_pg_ring); val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; - CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); - CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, + bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); + bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, BNX2_L2CTX_RBDC_JUMBO_KEY); val = (u64) bp->rx_pg_desc_mapping[0] >> 32; - CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); + bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff; - CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); + bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); if (CHIP_NUM(bp) == CHIP_NUM_5709) REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); } - val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; - val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; - val |= 0x02 << 8; - CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); - val = (u64) bp->rx_desc_mapping[0] >> 32; - CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); + bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); val = (u64) bp->rx_desc_mapping[0] & 0xffffffff; - CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); + bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); ring_prod = prod = bnapi->rx_pg_prod; for (i = 0; i < bp->rx_pg_ring_size; i++) { @@ -5005,9 +5059,9 @@ bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) for (offset = 0; offset < size; offset += 4) { - REG_WR_IND(bp, start + offset, test_pattern[i]); + bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]); - if (REG_RD_IND(bp, start + offset) != + if (bnx2_reg_rd_ind(bp, start + offset) != test_pattern[i]) { return -ENODEV; } @@ -5217,7 +5271,7 @@ bnx2_test_loopback(struct bnx2 *bp) static int bnx2_test_nvram(struct bnx2 *bp) { - u32 buf[NVRAM_SIZE / 4]; + __be32 buf[NVRAM_SIZE / 4]; u8 *data = (u8 *) buf; int rc = 0; u32 magic, csum; @@ -5317,7 +5371,7 @@ bnx2_5706_serdes_has_link(struct bnx2 *bp) bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); - if (an_dbg & MISC_SHDW_AN_DBG_NOSYNC) + if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID)) return 0; bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); @@ -5442,7 +5496,8 @@ bnx2_timer(unsigned long data) bnx2_send_heart_beat(bp); - bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT); + bp->stats_blk->stat_FwRxDrop = + bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT); /* workaround occasional corrupted counters */ if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks) @@ -7157,20 +7212,20 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bnx2_init_nvram(bp); - reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE); + reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE); if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == BNX2_SHM_HDR_SIGNATURE_SIG) { u32 off = PCI_FUNC(pdev->devfn) << 2; - bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off); + bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off); } else bp->shmem_base = HOST_VIEW_SHMEM_BASE; /* Get the permanent MAC address. First we need to make sure the * firmware is actually running. */ - reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE); + reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE); if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != BNX2_DEV_INFO_SIGNATURE_MAGIC) { @@ -7179,7 +7234,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) goto err_out_unmap; } - reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV); + reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV); for (i = 0, j = 0; i < 3; i++) { u8 num, k, skip0; @@ -7193,7 +7248,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) if (i != 2) bp->fw_version[j++] = '.'; } - reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE); + reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); if (reg & BNX2_PORT_FEATURE_WOL_ENABLED) bp->wol = 1; @@ -7201,34 +7256,33 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->flags |= BNX2_FLAG_ASF_ENABLE; for (i = 0; i < 30; i++) { - reg = REG_RD_IND(bp, bp->shmem_base + - BNX2_BC_STATE_CONDITION); + reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); if (reg & BNX2_CONDITION_MFW_RUN_MASK) break; msleep(10); } } - reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION); + reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); reg &= BNX2_CONDITION_MFW_RUN_MASK; if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && reg != BNX2_CONDITION_MFW_RUN_NONE) { int i; - u32 addr = REG_RD_IND(bp, bp->shmem_base + BNX2_MFW_VER_PTR); + u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR); bp->fw_version[j++] = ' '; for (i = 0; i < 3; i++) { - reg = REG_RD_IND(bp, addr + i * 4); + reg = bnx2_reg_rd_ind(bp, addr + i * 4); reg = swab32(reg); memcpy(&bp->fw_version[j], ®, 4); j += 4; } } - reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER); + reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER); bp->mac_addr[0] = (u8) (reg >> 8); bp->mac_addr[1] = (u8) reg; - reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER); + reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER); bp->mac_addr[2] = (u8) (reg >> 24); bp->mac_addr[3] = (u8) (reg >> 16); bp->mac_addr[4] = (u8) (reg >> 8); @@ -7267,8 +7321,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->phy_port = PORT_TP; if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { bp->phy_port = PORT_FIBRE; - reg = REG_RD_IND(bp, bp->shmem_base + - BNX2_SHARED_HW_CFG_CONFIG); + reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { bp->flags |= BNX2_FLAG_NO_WOL; bp->wol = 0;