X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=arch%2Fsh%2Fmm%2FKconfig;h=1b4364871899bceec8b93829c14115af5fb49cf8;hb=3f5ab768164df9a44721660b96e0accb92eb2c24;hp=b773361892c9a959b6e090355594bf7b8ecd498f;hpb=5f8c9908f200b775a3d6c345bc6f3e928e2426a9;p=safe%2Fjmp%2Flinux-2.6 diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig index b773361..1b43648 100644 --- a/arch/sh/mm/Kconfig +++ b/arch/sh/mm/Kconfig @@ -1,221 +1,3 @@ -menu "Processor selection" - -# -# Processor families -# -config CPU_SH2 - select SH_WRITETHROUGH if !CPU_SH2A - bool - -config CPU_SH2A - bool - select CPU_SH2 - -config CPU_SH3 - bool - select CPU_HAS_INTEVT - select CPU_HAS_SR_RB - -config CPU_SH4 - bool - select CPU_HAS_INTEVT - select CPU_HAS_SR_RB - select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2 - -config CPU_SH4A - bool - select CPU_SH4 - -config CPU_SH4AL_DSP - bool - select CPU_SH4A - -config CPU_SUBTYPE_ST40 - bool - select CPU_SH4 - select CPU_HAS_INTC2_IRQ - -config CPU_SHX2 - bool - -# -# Processor subtypes -# - -comment "SH-2 Processor Support" - -config CPU_SUBTYPE_SH7604 - bool "Support SH7604 processor" - select CPU_SH2 - -config CPU_SUBTYPE_SH7619 - bool "Support SH7619 processor" - select CPU_SH2 - -comment "SH-2A Processor Support" - -config CPU_SUBTYPE_SH7206 - bool "Support SH7206 processor" - select CPU_SH2A - -comment "SH-3 Processor Support" - -config CPU_SUBTYPE_SH7300 - bool "Support SH7300 processor" - select CPU_SH3 - -config CPU_SUBTYPE_SH7705 - bool "Support SH7705 processor" - select CPU_SH3 - select CPU_HAS_IPR_IRQ - select CPU_HAS_PINT_IRQ - -config CPU_SUBTYPE_SH7706 - bool "Support SH7706 processor" - select CPU_SH3 - select CPU_HAS_IPR_IRQ - help - Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. - -config CPU_SUBTYPE_SH7707 - bool "Support SH7707 processor" - select CPU_SH3 - select CPU_HAS_PINT_IRQ - help - Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. - -config CPU_SUBTYPE_SH7708 - bool "Support SH7708 processor" - select CPU_SH3 - help - Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or - if you have a 100 Mhz SH-3 HD6417708R CPU. - -config CPU_SUBTYPE_SH7709 - bool "Support SH7709 processor" - select CPU_SH3 - select CPU_HAS_IPR_IRQ - select CPU_HAS_PINT_IRQ - help - Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. - -config CPU_SUBTYPE_SH7710 - bool "Support SH7710 processor" - select CPU_SH3 - select CPU_HAS_IPR_IRQ - help - Select SH7710 if you have a SH3-DSP SH7710 CPU. - -config CPU_SUBTYPE_SH7712 - bool "Support SH7712 processor" - select CPU_SH3 - select CPU_HAS_IPR_IRQ - help - Select SH7712 if you have a SH3-DSP SH7712 CPU. - -comment "SH-4 Processor Support" - -config CPU_SUBTYPE_SH7750 - bool "Support SH7750 processor" - select CPU_SH4 - select CPU_HAS_IPR_IRQ - help - Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. - -config CPU_SUBTYPE_SH7091 - bool "Support SH7091 processor" - select CPU_SH4 - select CPU_SUBTYPE_SH7750 - help - Select SH7091 if you have an SH-4 based Sega device (such as - the Dreamcast, Naomi, and Naomi 2). - -config CPU_SUBTYPE_SH7750R - bool "Support SH7750R processor" - select CPU_SH4 - select CPU_SUBTYPE_SH7750 - select CPU_HAS_IPR_IRQ - -config CPU_SUBTYPE_SH7750S - bool "Support SH7750S processor" - select CPU_SH4 - select CPU_SUBTYPE_SH7750 - select CPU_HAS_IPR_IRQ - -config CPU_SUBTYPE_SH7751 - bool "Support SH7751 processor" - select CPU_SH4 - select CPU_HAS_IPR_IRQ - help - Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, - or if you have a HD6417751R CPU. - -config CPU_SUBTYPE_SH7751R - bool "Support SH7751R processor" - select CPU_SH4 - select CPU_SUBTYPE_SH7751 - select CPU_HAS_IPR_IRQ - -config CPU_SUBTYPE_SH7760 - bool "Support SH7760 processor" - select CPU_SH4 - select CPU_HAS_INTC2_IRQ - select CPU_HAS_IPR_IRQ - -config CPU_SUBTYPE_SH4_202 - bool "Support SH4-202 processor" - select CPU_SH4 - -comment "ST40 Processor Support" - -config CPU_SUBTYPE_ST40STB1 - bool "Support ST40STB1/ST40RA processors" - select CPU_SUBTYPE_ST40 - help - Select ST40STB1 if you have a ST40RA CPU. - This was previously called the ST40STB1, hence the option name. - -config CPU_SUBTYPE_ST40GX1 - bool "Support ST40GX1 processor" - select CPU_SUBTYPE_ST40 - help - Select ST40GX1 if you have a ST40GX1 CPU. - -comment "SH-4A Processor Support" - -config CPU_SUBTYPE_SH7770 - bool "Support SH7770 processor" - select CPU_SH4A - -config CPU_SUBTYPE_SH7780 - bool "Support SH7780 processor" - select CPU_SH4A - select CPU_HAS_INTC2_IRQ - -config CPU_SUBTYPE_SH7785 - bool "Support SH7785 processor" - select CPU_SH4A - select CPU_SHX2 - select CPU_HAS_INTC2_IRQ - -comment "SH4AL-DSP Processor Support" - -config CPU_SUBTYPE_SH73180 - bool "Support SH73180 processor" - select CPU_SH4AL_DSP - -config CPU_SUBTYPE_SH7343 - bool "Support SH7343 processor" - select CPU_SH4AL_DSP - -config CPU_SUBTYPE_SH7722 - bool "Support SH7722 processor" - select CPU_SH4AL_DSP - select CPU_SHX2 - select CPU_HAS_IPR_IRQ - -endmenu - menu "Memory management options" config QUICKLIST @@ -235,9 +17,33 @@ config MMU config PAGE_OFFSET hex - default "0x80000000" if MMU + default "0x80000000" if MMU && SUPERH32 + default "0x20000000" if MMU && SUPERH64 default "0x00000000" +config FORCE_MAX_ZONEORDER + int "Maximum zone order" + range 9 64 if PAGE_SIZE_16KB + default "9" if PAGE_SIZE_16KB + range 7 64 if PAGE_SIZE_64KB + default "7" if PAGE_SIZE_64KB + range 11 64 + default "14" if !MMU + default "11" + help + The kernel memory allocator divides physically contiguous memory + blocks into "zones", where each zone is a power of two number of + pages. This option selects the largest power of two that the kernel + keeps in the memory allocator. If you need to allocate very large + blocks of physically contiguous memory, then you may need to + increase this value. + + This config option is actually maximum order plus one. For example, + a value of 11 means that the largest free memory block is 2^10 pages. + + The page size is not necessarily 4KB. Keep this in mind when + choosing a value for this option. + config MEMORY_START hex "Physical memory start address" default "0x08000000" @@ -256,26 +62,61 @@ config MEMORY_START config MEMORY_SIZE hex "Physical memory size" - default "0x00400000" + default "0x04000000" help This sets the default memory size assumed by your SH kernel. It can be overridden as normal by the 'mem=' argument on the kernel command line. If unsure, consult your board specifications or just leave it - as 0x00400000 which was the default value before this became + as 0x04000000 which was the default value before this became configurable. +# Physical addressing modes + +config 29BIT + def_bool !32BIT + depends on SUPERH32 + config 32BIT + bool + default y if CPU_SH5 + +config PMB_ENABLE bool "Support 32-bit physical addressing through PMB" - depends on CPU_SH4A && MMU && (!X2TLB || BROKEN) + depends on MMU && EXPERIMENTAL && CPU_SH4A default y help If you say Y here, physical addressing will be extended to 32-bits through the SH-4A PMB. If this is not set, legacy 29-bit physical addressing will be used. +choice + prompt "PMB handling type" + depends on PMB_ENABLE + default PMB_FIXED + +config PMB + bool "PMB" + depends on MMU && EXPERIMENTAL && CPU_SH4A + help + If you say Y here, physical addressing will be extended to + 32-bits through the SH-4A PMB. If this is not set, legacy + 29-bit physical addressing will be used. + +config PMB_FIXED + bool "fixed PMB" + depends on MMU && EXPERIMENTAL && CPU_SH4A + select 32BIT + help + If this option is enabled, fixed PMB mappings are inherited + from the boot loader, and the kernel does not attempt dynamic + management. This is the closest to legacy 29-bit physical mode, + and allows systems to support up to 512MiB of system memory. + +endchoice + config X2TLB bool "Enable extended TLB mode" - depends on CPU_SHX2 && MMU && EXPERIMENTAL + depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL help Selecting this option will enable the extended mode of the SH-X2 TLB. For legacy SH-X behaviour and interoperability, say N. For @@ -284,7 +125,7 @@ config X2TLB config VSYSCALL bool "Support vsyscall page" - depends on MMU + depends on MMU && (CPU_SH3 || CPU_SH4) default y help This will enable support for the kernel mapping a vDSO page @@ -295,48 +136,118 @@ config VSYSCALL For systems with an MMU that can afford to give up a page, (the default value) say Y. +config NUMA + bool "Non Uniform Memory Access (NUMA) Support" + depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL + default n + help + Some SH systems have many various memories scattered around + the address space, each with varying latencies. This enables + support for these blocks by binding them to nodes and allowing + memory policies to be used for prioritizing and controlling + allocation behaviour. + config NODES_SHIFT int + default "3" if CPU_SUBTYPE_SHX3 default "1" depends on NEED_MULTIPLE_NODES config ARCH_FLATMEM_ENABLE def_bool y + depends on !NUMA + +config ARCH_SPARSEMEM_ENABLE + def_bool y + select SPARSEMEM_STATIC + +config ARCH_SPARSEMEM_DEFAULT + def_bool y + +config MAX_ACTIVE_REGIONS + int + default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM) + default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \ + CPU_SUBTYPE_SH7785) + default "1" config ARCH_POPULATES_NODE_MAP def_bool y +config ARCH_SELECT_MEMORY_MODEL + def_bool y + +config ARCH_ENABLE_MEMORY_HOTPLUG + def_bool y + depends on SPARSEMEM && MMU + +config ARCH_ENABLE_MEMORY_HOTREMOVE + def_bool y + depends on SPARSEMEM && MMU + +config ARCH_MEMORY_PROBE + def_bool y + depends on MEMORY_HOTPLUG + +choice + prompt "Page table layout" + default PGTABLE_LEVELS_3 if X2TLB + default PGTABLE_LEVELS_2 + +config PGTABLE_LEVELS_2 + bool "2 Levels" + help + This is the default page table layout for all SuperH CPUs. + +config PGTABLE_LEVELS_3 + bool "3 Levels" + depends on X2TLB + help + This enables a 3 level page table structure. + +endchoice + choice prompt "Kernel page size" + default PAGE_SIZE_8KB if X2TLB default PAGE_SIZE_4KB config PAGE_SIZE_4KB bool "4kB" + depends on !MMU || !X2TLB || PGTABLE_LEVELS_3 help This is the default page size used by all SuperH CPUs. config PAGE_SIZE_8KB bool "8kB" - depends on EXPERIMENTAL && X2TLB + depends on !MMU || X2TLB help This enables 8kB pages as supported by SH-X2 and later MMUs. +config PAGE_SIZE_16KB + bool "16kB" + depends on !MMU + help + This enables 16kB pages on MMU-less SH systems. + config PAGE_SIZE_64KB bool "64kB" - depends on EXPERIMENTAL && CPU_SH4 + depends on !MMU || CPU_SH4 || CPU_SH5 help This enables support for 64kB pages, possible on all SH-4 - CPUs and later. Highly experimental, not recommended. + CPUs and later. endchoice choice prompt "HugeTLB page size" - depends on HUGETLB_PAGE && CPU_SH4 && MMU + depends on HUGETLB_PAGE + default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB default HUGETLB_PAGE_SIZE_64K config HUGETLB_PAGE_SIZE_64K bool "64kB" + depends on !PAGE_SIZE_64KB config HUGETLB_PAGE_SIZE_256K bool "256kB" @@ -353,10 +264,23 @@ config HUGETLB_PAGE_SIZE_64MB bool "64MB" depends on X2TLB +config HUGETLB_PAGE_SIZE_512MB + bool "512MB" + depends on CPU_SH5 + endchoice source "mm/Kconfig" +config SCHED_MC + bool "Multi-core scheduler support" + depends on SMP + default y + help + Multi-core scheduler support improves the CPU scheduler's decision + making when dealing with multi-core CPU chips at a cost of slightly + increased overhead in some places. If unsure say N here. + endmenu menu "Cache configuration" @@ -366,20 +290,16 @@ config SH7705_CACHE_32KB depends on CPU_SUBTYPE_SH7705 default y -config SH_DIRECT_MAPPED - bool "Use direct-mapped caching" - default n - help - Selecting this option will configure the caches to be direct-mapped, - even if the cache supports a 2 or 4-way mode. This is useful primarily - for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R, - SH4-202, SH4-501, etc.) +choice + prompt "Cache mode" + default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 + default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) - Turn this option off for platforms that do not have a direct-mapped - cache, and you have no need to run the caches in such a configuration. +config CACHE_WRITEBACK + bool "Write-back" -config SH_WRITETHROUGH - bool "Use write-through caching" +config CACHE_WRITETHROUGH + bool "Write-through" help Selecting this option will configure the caches in write-through mode, as opposed to the default write-back configuration. @@ -390,15 +310,9 @@ config SH_WRITETHROUGH If unsure, say N. -config SH_OCRAM - bool "Operand Cache RAM (OCRAM) support" - help - Selecting this option will automatically tear down the number of - sets in the dcache by half, which in turn exposes a memory range. +config CACHE_OFF + bool "Off" - The addresses for the OC RAM base will vary according to the - processor version. Consult vendor documentation for specifics. - - If unsure, say N. +endchoice endmenu