X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=arch%2Fblackfin%2FKconfig;h=c078849df7f9712349e0e5c1f721d977953f8e3f;hb=b054b747a694927879c94dd11af54d04346aed7d;hp=72ff71949045b688217b3a18839010210695b382;hpb=55e359a825d25cecea2007db3e4018675e42f1af;p=safe%2Fjmp%2Flinux-2.6 diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 72ff719..c078849 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -5,64 +5,76 @@ mainmenu "Blackfin Kernel Configuration" +config SYMBOL_PREFIX + string + default "_" + config MMU - bool - default n + def_bool n config FPU - bool - default n + def_bool n config RWSEM_GENERIC_SPINLOCK - bool - default y + def_bool y config RWSEM_XCHGADD_ALGORITHM - bool - default n + def_bool n config BLACKFIN - bool - default y + def_bool y + select HAVE_ARCH_KGDB + select HAVE_ARCH_TRACEHOOK + select HAVE_FUNCTION_GRAPH_TRACER + select HAVE_FUNCTION_TRACER + select HAVE_FUNCTION_TRACE_MCOUNT_TEST select HAVE_IDE + select HAVE_KERNEL_GZIP if RAMKERNEL + select HAVE_KERNEL_BZIP2 if RAMKERNEL + select HAVE_KERNEL_LZMA if RAMKERNEL select HAVE_OPROFILE select ARCH_WANT_OPTIONAL_GPIOLIB +config GENERIC_CSUM + def_bool y + +config GENERIC_BUG + def_bool y + depends on BUG + config ZONE_DMA - bool - default y + def_bool y config GENERIC_FIND_NEXT_BIT - bool - default y - -config GENERIC_HWEIGHT - bool - default y + def_bool y config GENERIC_HARDIRQS - bool - default y + def_bool y config GENERIC_IRQ_PROBE - bool - default y + def_bool y + +config GENERIC_HARDIRQS_NO__DO_IRQ + def_bool y config GENERIC_GPIO - bool - default y + def_bool y config FORCE_MAX_ZONEORDER int default "14" config GENERIC_CALIBRATE_DELAY - bool - default y + def_bool y + +config LOCKDEP_SUPPORT + def_bool y + +config STACKTRACE_SUPPORT + def_bool y -config HARDWARE_PM +config TRACE_IRQFLAGS_SUPPORT def_bool y - depends on OPROFILE source "init/Kconfig" @@ -168,31 +180,56 @@ config BF539 help BF539 Processor Support. -config BF542 +config BF542_std bool "BF542" help BF542 Processor Support. -config BF544 +config BF542M + bool "BF542m" + help + BF542 Processor Support. + +config BF544_std bool "BF544" help BF544 Processor Support. -config BF547 +config BF544M + bool "BF544m" + help + BF544 Processor Support. + +config BF547_std bool "BF547" help BF547 Processor Support. -config BF548 +config BF547M + bool "BF547m" + help + BF547 Processor Support. + +config BF548_std bool "BF548" help BF548 Processor Support. -config BF549 +config BF548M + bool "BF548m" + help + BF548 Processor Support. + +config BF549_std bool "BF549" help BF549 Processor Support. +config BF549M + bool "BF549m" + help + BF549 Processor Support. + config BF561 bool "BF561" help @@ -202,6 +239,7 @@ endchoice config SMP depends on BF561 + select TICKSOURCE_CORETMR bool "Symmetric multi-processing support" ---help--- This enables support for systems with more than one CPU, @@ -215,52 +253,55 @@ config NR_CPUS depends on SMP default 2 if BF561 +config HOTPLUG_CPU + bool "Support for hot-pluggable CPUs" + depends on SMP && HOTPLUG + default y + config IRQ_PER_CPU bool depends on SMP default y -config TICK_SOURCE_SYSTMR0 - bool - select BFIN_GPTIMERS +config HAVE_LEGACY_PER_CPU_AREA + def_bool y depends on SMP - default y config BF_REV_MIN int - default 0 if (BF51x || BF52x || BF54x) + default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) default 2 if (BF537 || BF536 || BF534) - default 3 if (BF561 ||BF533 || BF532 || BF531) + default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) default 4 if (BF538 || BF539) config BF_REV_MAX int - default 2 if (BF51x || BF52x || BF54x) - default 3 if (BF537 || BF536 || BF534) + default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) + default 3 if (BF537 || BF536 || BF534 || BF54xM) default 5 if (BF561 || BF538 || BF539) default 6 if (BF533 || BF532 || BF531) choice prompt "Silicon Rev" - default BF_REV_0_1 if (BF51x || BF52x || BF54x) - default BF_REV_0_2 if (BF534 || BF536 || BF537) - default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561) + default BF_REV_0_0 if (BF51x || BF52x) + default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) + default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) config BF_REV_0_0 bool "0.0" - depends on (BF51x || BF52x || BF54x) + depends on (BF51x || BF52x || (BF54x && !BF54xM)) config BF_REV_0_1 bool "0.1" - depends on (BF52x || BF54x) + depends on (BF51x || BF52x || (BF54x && !BF54xM)) config BF_REV_0_2 bool "0.2" - depends on (BF52x || BF537 || BF536 || BF534 || BF54x) + depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) config BF_REV_0_3 bool "0.3" - depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) + depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) config BF_REV_0_4 bool "0.4" @@ -282,26 +323,11 @@ config BF_REV_NONE endchoice -config BF51x - bool - depends on (BF512 || BF514 || BF516 || BF518) - default y - -config BF52x - bool - depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) - default y - config BF53x bool depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) default y -config BF54x - bool - depends on (BF542 || BF544 || BF547 || BF548 || BF549) - default y - config MEM_GENERIC_BOARD bool depends on GENERIC_BOARD @@ -315,8 +341,9 @@ config MEM_MT48LC64M4A2FB_7E config MEM_MT48LC16M16A2TG_75 bool depends on (BFIN533_EZKIT || BFIN561_EZKIT \ - || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ - || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) + || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ + || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ + || BFIN527_BLUETECHNIX_CM) default y config MEM_MT48LC32M8A2_75 @@ -331,7 +358,17 @@ config MEM_MT48LC8M32B2B5_7 config MEM_MT48LC32M16A2TG_75 bool - depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) + depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP) + default y + +config MEM_MT48LC32M8A2_75 + bool + depends on (BFIN518F_EZBRD) + default y + +config MEM_MT48H32M16LFCJ_75 + bool + depends on (BFIN526_EZBRD) default y source "arch/blackfin/mach-bf518/Kconfig" @@ -372,21 +409,30 @@ config BOOT_LOAD config ROM_BASE hex "Kernel ROM Base" - default "0x20040000" + depends on ROMKERNEL + default "0x20040040" range 0x20000000 0x20400000 if !(BF54x || BF561) range 0x20000000 0x30000000 if (BF54x || BF561) help + Make sure your ROM base does not include any file-header + information that is prepended to the kernel. + + For example, the bootable U-Boot format (created with + mkimage) has a 64 byte header (0x40). So while the image + you write to flash might start at say 0x20080000, you have + to add 0x40 to get the kernel's ROM base as it will come + after the header. comment "Clock/PLL Setup" config CLKIN_HZ int "Frequency of the crystal on the board in Hz" + default "10000000" if BFIN532_IP0X default "11059200" if BFIN533_STAMP + default "24576000" if PNAV10 + default "25000000" # most people use this default "27000000" if BFIN533_EZKIT - default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD) default "30000000" if BFIN561_EZKIT - default "24576000" if PNAV10 - default "10000000" if BFIN532_IP0X help The frequency of CLKIN crystal oscillator on the board in Hz. Warning: This value should match the crystal on the board. Otherwise, @@ -419,9 +465,9 @@ config VCO_MULT range 1 64 default "22" if BFIN533_EZKIT default "45" if BFIN533_STAMP - default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) + default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) default "22" if BFIN533_BLUETECHNIX_CM - default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) + default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) default "20" if BFIN561_EZKIT default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) help @@ -472,13 +518,60 @@ config MEM_MT46V32M16_5B bool "MT46V32M16_5B" endchoice -config MAX_MEM_SIZE - int "Max SDRAM Memory Size in MBytes" - depends on !MPU - default 512 +choice + prompt "DDR/SDRAM Timing" + depends on BFIN_KERNEL_CLOCK + default BFIN_KERNEL_CLOCK_MEMINIT_CALC + help + This option allows you to specify Blackfin SDRAM/DDR Timing parameters + The calculated SDRAM timing parameters may not be 100% + accurate - This option is therefore marked experimental. + +config BFIN_KERNEL_CLOCK_MEMINIT_CALC + bool "Calculate Timings (EXPERIMENTAL)" + depends on EXPERIMENTAL + +config BFIN_KERNEL_CLOCK_MEMINIT_SPEC + bool "Provide accurate Timings based on target SCLK" help - This is the max memory size that the kernel will create CPLB - tables for. Your system will not be able to handle any more. + Please consult the Blackfin Hardware Reference Manuals as well + as the memory device datasheet. + http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram +endchoice + +menu "Memory Init Control" + depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC + +config MEM_DDRCTL0 + depends on BF54x + hex "DDRCTL0" + default 0x0 + +config MEM_DDRCTL1 + depends on BF54x + hex "DDRCTL1" + default 0x0 + +config MEM_DDRCTL2 + depends on BF54x + hex "DDRCTL2" + default 0x0 + +config MEM_EBIU_DDRQUE + depends on BF54x + hex "DDRQUE" + default 0x0 + +config MEM_SDRRC + depends on !BF54x + hex "SDRRC" + default 0x0 + +config MEM_SDGCTL + depends on !BF54x + hex "SDGCTL" + default 0x0 +endmenu # # Max & Min Speeds for various Chips @@ -489,8 +582,8 @@ config MAX_VCO_HZ default 400000000 if BF514 default 400000000 if BF516 default 400000000 if BF518 - default 600000000 if BF522 - default 400000000 if BF523 + default 400000000 if BF522 + default 600000000 if BF523 default 400000000 if BF524 default 600000000 if BF525 default 400000000 if BF526 @@ -527,21 +620,31 @@ comment "Kernel Timer/Scheduler" source kernel/Kconfig.hz config GENERIC_TIME - bool "Generic time" - depends on !SMP - default y + def_bool y config GENERIC_CLOCKEVENTS bool "Generic clock events" - depends on GENERIC_TIME default y -config CYCLES_CLOCKSOURCE - bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" - depends on EXPERIMENTAL +menu "Clock event device" depends on GENERIC_CLOCKEVENTS +config TICKSOURCE_GPTMR0 + bool "GPTimer0" + depends on !SMP + select BFIN_GPTIMERS + +config TICKSOURCE_CORETMR + bool "Core timer" + default y +endmenu + +menu "Clock souce" + depends on GENERIC_CLOCKEVENTS +config CYCLES_CLOCKSOURCE + bool "CYCLES" + default y depends on !BFIN_SCRATCH_REG_CYCLES - default n + depends on !SMP help If you say Y here, you will enable support for using the 'cycles' registers as a clock source. Doing so means you will be unable to @@ -549,6 +652,16 @@ config CYCLES_CLOCKSOURCE still be able to read it (such as for performance monitoring), but writing the registers will most likely crash the kernel. +config GPTMR0_CLOCKSOURCE + bool "GPTimer0" + select BFIN_GPTIMERS + depends on !TICKSOURCE_GPTMR0 +endmenu + +config ARCH_USES_GETTIMEOFFSET + depends on !GENERIC_CLOCKEVENTS + def_bool y + source kernel/time/Kconfig comment "Misc" @@ -698,7 +811,7 @@ config CACHELINE_ALIGNED_L1 default n if BF54x depends on !BF531 help - If enabled, cacheline_anligned data is linked + If enabled, cacheline_aligned data is linked into L1 data memory. (less latency) config SYSCALL_TAB_L1 @@ -729,7 +842,7 @@ config APP_STACK_L1 config EXCEPTION_L1_SCRATCH bool "Locate exception stack in L1 Scratch Memory" default n - depends on !APP_STACK_L1 && !SYSCALL_TAB_L1 + depends on !APP_STACK_L1 help Whenever an exception occurs, use the L1 Scratch memory for stack storage. You cannot place the stacks of FLAT binaries @@ -793,7 +906,7 @@ config BFIN_GPTIMERS are unsure, say N. To compile this driver as a module, choose M here: the module - will be called gptimers.ko. + will be called gptimers. choice prompt "Uncached DMA region" @@ -804,29 +917,49 @@ config DMA_UNCACHED_2M bool "Enable 2M DMA region" config DMA_UNCACHED_1M bool "Enable 1M DMA region" +config DMA_UNCACHED_512K + bool "Enable 512K DMA region" +config DMA_UNCACHED_256K + bool "Enable 256K DMA region" +config DMA_UNCACHED_128K + bool "Enable 128K DMA region" config DMA_UNCACHED_NONE bool "Disable DMA region" endchoice comment "Cache Support" + config BFIN_ICACHE bool "Enable ICACHE" + default y +config BFIN_EXTMEM_ICACHEABLE + bool "Enable ICACHE for external memory" + depends on BFIN_ICACHE + default y +config BFIN_L2_ICACHEABLE + bool "Enable ICACHE for L2 SRAM" + depends on BFIN_ICACHE + depends on BF54x || BF561 + default n + config BFIN_DCACHE bool "Enable DCACHE" + default y config BFIN_DCACHE_BANKA bool "Enable only 16k BankA DCACHE - BankB is SRAM" depends on BFIN_DCACHE && !BF531 default n -config BFIN_ICACHE_LOCK - bool "Enable Instruction Cache Locking" - -choice - prompt "Policy" +config BFIN_EXTMEM_DCACHEABLE + bool "Enable DCACHE for external memory" depends on BFIN_DCACHE - default BFIN_WB if !SMP - default BFIN_WT if SMP -config BFIN_WB + default y +choice + prompt "External memory DCACHE policy" + depends on BFIN_EXTMEM_DCACHEABLE + default BFIN_EXTMEM_WRITEBACK if !SMP + default BFIN_EXTMEM_WRITETHROUGH if SMP +config BFIN_EXTMEM_WRITEBACK bool "Write back" depends on !SMP help @@ -844,7 +977,7 @@ config BFIN_WB If you are unsure of the options and you want to be safe, then go with Write Through. -config BFIN_WT +config BFIN_EXTMEM_WRITETHROUGH bool "Write through" help Write Back Policy: @@ -863,13 +996,24 @@ config BFIN_WT endchoice -config BFIN_L2_CACHEABLE - bool "Cache L2 SRAM" - depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561) +config BFIN_L2_DCACHEABLE + bool "Enable DCACHE for L2 SRAM" + depends on BFIN_DCACHE + depends on (BF54x || BF561) && !SMP default n - help - Select to make L2 SRAM cacheable in L1 data and instruction cache. +choice + prompt "L2 SRAM DCACHE policy" + depends on BFIN_L2_DCACHEABLE + default BFIN_L2_WRITEBACK +config BFIN_L2_WRITEBACK + bool "Write back" + +config BFIN_L2_WRITETHROUGH + bool "Write through" +endchoice + +comment "Memory Protection Unit" config MPU bool "Enable the memory protection unit (EXPERIMENTAL)" default n @@ -878,7 +1022,7 @@ config MPU memory they do not own. This comes at a performance penalty and is recommended only for debugging. -comment "Asynchonous Memory Configuration" +comment "Asynchronous Memory Configuration" menu "EBIU_AMGCTL Global Control" config C_AMCKEN @@ -910,7 +1054,7 @@ config C_B3PEN default n choice - prompt"Enable Asynchonous Memory Banks" + prompt "Enable Asynchronous Memory Banks" default C_AMBEN_ALL config C_AMBEN @@ -932,21 +1076,34 @@ endmenu menu "EBIU_AMBCTL Control" config BANK_0 - hex "Bank 0" + hex "Bank 0 (AMBCTL0.L)" default 0x7BB0 + help + These are the low 16 bits of the EBIU_AMBCTL0 MMR which are + used to control the Asynchronous Memory Bank 0 settings. config BANK_1 - hex "Bank 1" + hex "Bank 1 (AMBCTL0.H)" default 0x7BB0 default 0x5558 if BF54x + help + These are the high 16 bits of the EBIU_AMBCTL0 MMR which are + used to control the Asynchronous Memory Bank 1 settings. config BANK_2 - hex "Bank 2" + hex "Bank 2 (AMBCTL1.L)" default 0x7BB0 + help + These are the low 16 bits of the EBIU_AMBCTL1 MMR which are + used to control the Asynchronous Memory Bank 2 settings. config BANK_3 - hex "Bank 3" + hex "Bank 3 (AMBCTL1.H)" default 0x99B3 + help + These are the high 16 bits of the EBIU_AMBCTL1 MMR which are + used to control the Asynchronous Memory Bank 3 settings. + endmenu config EBIU_MBSCTLVAL @@ -976,24 +1133,6 @@ config PCI source "drivers/pci/Kconfig" -config HOTPLUG - bool "Support for hot-pluggable device" - help - Say Y here if you want to plug devices into your computer while - the system is running, and be able to use them quickly. In many - cases, the devices can likewise be unplugged at any time too. - - One well known example of this is PCMCIA- or PC-cards, credit-card - size devices such as network cards, modems or hard drives which are - plugged into slots found on all modern laptop computers. Another - example, used on modern desktops as well as laptops, is USB. - - Enable HOTPLUG and build a modular kernel. Get agent software - (from ) and install it. - Then your kernel will automatically call out to a user mode "policy - agent" (/sbin/hotplug) to load modules and set up software needed - to use devices as you hotplug them. - source "drivers/pcmcia/Kconfig" source "drivers/pci/hotplug/Kconfig" @@ -1007,11 +1146,11 @@ source "fs/Kconfig.binfmt" endmenu menu "Power management options" + source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE def_bool y - depends on !SMP choice prompt "Standby Power Saving Mode" @@ -1050,6 +1189,7 @@ endchoice config PM_WAKEUP_BY_GPIO bool "Allow Wakeup from Standby by GPIO" + depends on PM && !BF54x config PM_WAKEUP_GPIO_NUMBER int "GPIO number" @@ -1089,6 +1229,12 @@ config PM_BFIN_WAKE_GP default n help Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) + (all processors, except ADSP-BF549). This option sets + the general-purpose wake-up enable (GPWE) control bit to enable + wake-up upon detection of an active low signal on the /GPW (PH7) pin. + On ADSP-BF549 this option enables the the same functionality on the + /MRXON pin also PH7. + endmenu menu "CPU Frequency scaling" @@ -1103,13 +1249,13 @@ config BFIN_CPU_FREQ config CPU_VOLTAGE bool "CPU Voltage scaling" - depends on EXPERIMENTAL + depends on EXPERIMENTAL depends on CPU_FREQ default n help Say Y here if you want CPU voltage scaling according to the CPU frequency. This option violates the PLL BYPASS recommendation in the Blackfin Processor - manuals. There is a theoretical risk that during VDDINT transitions + manuals. There is a theoretical risk that during VDDINT transitions the PLL may unlock. endmenu @@ -1118,6 +1264,8 @@ source "net/Kconfig" source "drivers/Kconfig" +source "drivers/firmware/Kconfig" + source "fs/Kconfig" source "arch/blackfin/Kconfig.debug"