X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=arch%2Fblackfin%2FKconfig;h=8102c79aaa94044369612ab3a8dc3bb6e33aa807;hb=3201b5d9f0f7ef392886cd76dcd2c69186d9d5cd;hp=a241a0a27de2de0477dfb6e60f0ed3318a2252ec;hpb=1545a1111a02b5aafe6f141e133a6269c5741285;p=safe%2Fjmp%2Flinux-2.6
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index a241a0a..8102c79 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -24,15 +24,13 @@ config RWSEM_XCHGADD_ALGORITHM
config BLACKFIN
bool
default y
+ select HAVE_IDE
+ select HAVE_OPROFILE
config ZONE_DMA
bool
default y
-config SEMAPHORE_SLEEPERS
- bool
- default y
-
config GENERIC_FIND_NEXT_BIT
bool
default y
@@ -49,10 +47,6 @@ config GENERIC_IRQ_PROBE
bool
default y
-config GENERIC_TIME
- bool
- default n
-
config GENERIC_GPIO
bool
default y
@@ -168,16 +162,28 @@ config BF549
config BF561
bool "BF561"
help
- Not Supported Yet - Work in progress - BF561 Processor Support.
+ BF561 Processor Support.
endchoice
+config BF_REV_MIN
+ int
+ default 0 if (BF52x || BF54x)
+ default 2 if (BF537 || BF536 || BF534)
+ default 3 if (BF561 ||BF533 || BF532 || BF531)
+
+config BF_REV_MAX
+ int
+ default 2 if (BF52x || BF54x)
+ default 3 if (BF537 || BF536 || BF534)
+ default 5 if (BF561)
+ default 6 if (BF533 || BF532 || BF531)
+
choice
prompt "Silicon Rev"
- default BF_REV_0_1 if BF527
- default BF_REV_0_2 if BF537
- default BF_REV_0_3 if BF533
- default BF_REV_0_0 if BF549
+ default BF_REV_0_1 if (BF52x || BF54x)
+ default BF_REV_0_2 if (BF534 || BF536 || BF537)
+ default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
config BF_REV_0_0
bool "0.0"
@@ -189,7 +195,7 @@ config BF_REV_0_1
config BF_REV_0_2
bool "0.2"
- depends on (BF537 || BF536 || BF534)
+ depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
config BF_REV_0_3
bool "0.3"
@@ -203,6 +209,10 @@ config BF_REV_0_5
bool "0.5"
depends on (BF561 || BF533 || BF532 || BF531)
+config BF_REV_0_6
+ bool "0.6"
+ depends on (BF533 || BF532 || BF531)
+
config BF_REV_ANY
bool "any"
@@ -226,16 +236,6 @@ config BF54x
depends on (BF542 || BF544 || BF547 || BF548 || BF549)
default y
-config BFIN_DUAL_CORE
- bool
- depends on (BF561)
- default y
-
-config BFIN_SINGLE_CORE
- bool
- depends on !BFIN_DUAL_CORE
- default y
-
config MEM_GENERIC_BOARD
bool
depends on GENERIC_BOARD
@@ -250,7 +250,7 @@ config MEM_MT48LC16M16A2TG_75
bool
depends on (BFIN533_EZKIT || BFIN561_EZKIT \
|| BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
- || H8606_HVSISTEMAS)
+ || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
default y
config MEM_MT48LC32M8A2_75
@@ -265,12 +265,7 @@ config MEM_MT48LC8M32B2B5_7
config MEM_MT48LC32M16A2TG_75
bool
- depends on (BFIN527_EZKIT)
- default y
-
-config BFIN_SHARED_FLASH_ENET
- bool
- depends on (BFIN533_STAMP)
+ depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
default y
source "arch/blackfin/mach-bf527/Kconfig"
@@ -293,17 +288,41 @@ config CMDLINE
to the kernel, you may specify one here. As a minimum, you should specify
the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
+config BOOT_LOAD
+ hex "Kernel load address for booting"
+ default "0x1000"
+ range 0x1000 0x20000000
+ help
+ This option allows you to set the load address of the kernel.
+ This can be useful if you are on a board which has a small amount
+ of memory or you wish to reserve some memory at the beginning of
+ the address space.
+
+ Note that you need to keep this value above 4k (0x1000) as this
+ memory region is used to capture NULL pointer references as well
+ as some core kernel functions.
+
+config ROM_BASE
+ hex "Kernel ROM Base"
+ default "0x20040000"
+ range 0x20000000 0x20400000 if !(BF54x || BF561)
+ range 0x20000000 0x30000000 if (BF54x || BF561)
+ help
+
comment "Clock/PLL Setup"
config CLKIN_HZ
- int "Crystal Frequency in Hz"
+ int "Frequency of the crystal on the board in Hz"
default "11059200" if BFIN533_STAMP
default "27000000" if BFIN533_EZKIT
- default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
+ default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
default "30000000" if BFIN561_EZKIT
default "24576000" if PNAV10
+ default "10000000" if BFIN532_IP0X
help
The frequency of CLKIN crystal oscillator on the board in Hz.
+ Warning: This value should match the crystal on the board. Otherwise,
+ peripherals won't work properly.
config BFIN_KERNEL_CLOCK
bool "Re-program Clocks while Kernel boots?"
@@ -332,12 +351,11 @@ config VCO_MULT
range 1 64
default "22" if BFIN533_EZKIT
default "45" if BFIN533_STAMP
- default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
+ default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
default "22" if BFIN533_BLUETECHNIX_CM
- default "20" if BFIN537_BLUETECHNIX_CM
- default "20" if BFIN561_BLUETECHNIX_CM
+ default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
default "20" if BFIN561_EZKIT
- default "16" if H8606_HVSISTEMAS
+ default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
help
This controls the frequency of the on-chip PLL. This can be between 1 and 64.
PLL Frequency = (Crystal Frequency) * (this setting)
@@ -367,19 +385,33 @@ config SCLK_DIV
int "System Clock Divider"
depends on BFIN_KERNEL_CLOCK
range 1 15
- default 5 if BFIN533_EZKIT
- default 5 if BFIN533_STAMP
- default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
- default 5 if BFIN533_BLUETECHNIX_CM
- default 4 if BFIN537_BLUETECHNIX_CM
- default 4 if BFIN561_BLUETECHNIX_CM
- default 5 if BFIN561_EZKIT
- default 3 if H8606_HVSISTEMAS
+ default 5
help
This sets the frequency of the system clock (including SDRAM or DDR).
This can be between 1 and 15
System Clock = (PLL frequency) / (this setting)
+choice
+ prompt "DDR SDRAM Chip Type"
+ depends on BFIN_KERNEL_CLOCK
+ depends on BF54x
+ default MEM_MT46V32M16_5B
+
+config MEM_MT46V32M16_6T
+ bool "MT46V32M16_6T"
+
+config MEM_MT46V32M16_5B
+ bool "MT46V32M16_5B"
+endchoice
+
+config MAX_MEM_SIZE
+ int "Max SDRAM Memory Size in MBytes"
+ depends on !MPU
+ default 512
+ help
+ This is the max memory size that the kernel will create CPLB
+ tables for. Your system will not be able to handle any more.
+
#
# Max & Min Speeds for various Chips
#
@@ -422,66 +454,31 @@ comment "Kernel Timer/Scheduler"
source kernel/Kconfig.hz
-comment "Memory Setup"
-
-config MEM_SIZE
- int "SDRAM Memory Size in MBytes"
- default 32 if BFIN533_EZKIT
- default 64 if BFIN527_EZKIT
- default 64 if BFIN537_STAMP
- default 64 if BFIN548_EZKIT
- default 64 if BFIN561_EZKIT
- default 128 if BFIN533_STAMP
- default 64 if PNAV10
- default 32 if H8606_HVSISTEMAS
-
-config MEM_ADD_WIDTH
- int "SDRAM Memory Address Width"
- depends on (!BF54x)
- default 9 if BFIN533_EZKIT
- default 9 if BFIN561_EZKIT
- default 9 if H8606_HVSISTEMAS
- default 10 if BFIN527_EZKIT
- default 10 if BFIN537_STAMP
- default 11 if BFIN533_STAMP
- default 10 if PNAV10
-
-
-choice
- prompt "DDR SDRAM Chip Type"
- depends on BFIN548_EZKIT
- default MEM_MT46V32M16_5B
-
-config MEM_MT46V32M16_6T
- bool "MT46V32M16_6T"
+config GENERIC_TIME
+ bool "Generic time"
+ default y
-config MEM_MT46V32M16_5B
- bool "MT46V32M16_5B"
-endchoice
+config GENERIC_CLOCKEVENTS
+ bool "Generic clock events"
+ depends on GENERIC_TIME
+ default y
-config ENET_FLASH_PIN
- int "PF port/pin used for flash and ethernet sharing"
- depends on (BFIN533_STAMP)
- default 0
+config CYCLES_CLOCKSOURCE
+ bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
+ depends on EXPERIMENTAL
+ depends on GENERIC_CLOCKEVENTS
+ depends on !BFIN_SCRATCH_REG_CYCLES
+ default n
help
- PF port/pin used for flash and ethernet sharing to allow other PF
- pins to be used on other platforms without having to touch common
- code.
- For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
+ If you say Y here, you will enable support for using the 'cycles'
+ registers as a clock source. Doing so means you will be unable to
+ safely write to the 'cycles' register during runtime. You will
+ still be able to read it (such as for performance monitoring), but
+ writing the registers will most likely crash the kernel.
-config BOOT_LOAD
- hex "Kernel load address for booting"
- default "0x1000"
- range 0x1000 0x20000000
- help
- This option allows you to set the load address of the kernel.
- This can be useful if you are on a board which has a small amount
- of memory or you wish to reserve some memory at the beginning of
- the address space.
+source kernel/time/Kconfig
- Note that you need to keep this value above 4k (0x1000) as this
- memory region is used to capture NULL pointer references as well
- as some core kernel functions.
+comment "Misc"
choice
prompt "Blackfin Exception Scratch Register"
@@ -548,7 +545,7 @@ config EXCPT_IRQ_SYSC_L1
default y
help
If enabled, the entire ASM lowlevel exception and interrupt entry code
- (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
+ (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
(less latency)
config DO_IRQ_L1
@@ -646,6 +643,42 @@ config CPLB_SWITCH_TAB_L1
If enabled, the CPLB Switch Tables are linked
into L1 data memory. (less latency)
+config APP_STACK_L1
+ bool "Support locating application stack in L1 Scratch Memory"
+ default y
+ help
+ If enabled the application stack can be located in L1
+ scratch memory (less latency).
+
+ Currently only works with FLAT binaries.
+
+comment "Speed Optimizations"
+config BFIN_INS_LOWOVERHEAD
+ bool "ins[bwl] low overhead, higher interrupt latency"
+ default y
+ help
+ Reads on the Blackfin are speculative. In Blackfin terms, this means
+ they can be interrupted at any time (even after they have been issued
+ on to the external bus), and re-issued after the interrupt occurs.
+ For memory - this is not a big deal, since memory does not change if
+ it sees a read.
+
+ If a FIFO is sitting on the end of the read, it will see two reads,
+ when the core only sees one since the FIFO receives both the read
+ which is cancelled (and not delivered to the core) and the one which
+ is re-issued (which is delivered to the core).
+
+ To solve this, interrupts are turned off before reads occur to
+ I/O space. This option controls which the overhead/latency of
+ controlling interrupts during this time
+ "n" turns interrupts off every read
+ (higher overhead, but lower interrupt latency)
+ "y" turns interrupts off every loop
+ (low overhead, but longer interrupt latency)
+
+ default behavior is to leave this set to on (type "Y"). If you are experiencing
+ interrupt latency issues, it is safe and OK to turn this off.
+
endmenu
@@ -668,14 +701,6 @@ endchoice
source "mm/Kconfig"
-config LARGE_ALLOCS
- bool "Allow allocating large blocks (> 1MB) of memory"
- help
- Allow the slab memory allocator to keep chains for very large
- memory sizes - upto 32MB. You may need this if your system has
- a lot of RAM, and you need to able to allocate very large
- contiguous chunks. If unsure, say N.
-
config BFIN_GPTIMERS
tristate "Enable Blackfin General Purpose Timers API"
default n
@@ -697,6 +722,8 @@ choice
prompt "Uncached SDRAM region"
default DMA_UNCACHED_1M
depends on BFIN_DMA_5XX
+config DMA_UNCACHED_4M
+ bool "Enable 4M DMA region"
config DMA_UNCACHED_2M
bool "Enable 2M DMA region"
config DMA_UNCACHED_1M
@@ -758,12 +785,20 @@ config BFIN_WT
endchoice
-config L1_MAX_PIECE
- int "Set the max L1 SRAM pieces"
- default 16
+config BFIN_L2_CACHEABLE
+ bool "Cache L2 SRAM"
+ depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+ default n
+ help
+ Select to make L2 SRAM cacheable in L1 data and instruction cache.
+
+config MPU
+ bool "Enable the memory protection unit (EXPERIMENTAL)"
+ default n
help
- Set the max memory pieces for the L1 SRAM allocation algorithm.
- Min value is 16. Max value is 1024.
+ Use the processor's MPU to protect applications from accessing
+ memory they do not own. This comes at a performance penalty
+ and is recommended only for debugging.
comment "Asynchonous Memory Configuration"
@@ -774,7 +809,6 @@ config C_AMCKEN
config C_CDPRIO
bool "DMA has priority over core for ext. accesses"
- depends on !BF54x
default n
config C_B0PEN
@@ -826,6 +860,7 @@ config BANK_0
config BANK_1
hex "Bank 1"
default 0x7BB0
+ default 0x5558 if BF54x
config BANK_2
hex "Bank 2"
@@ -857,6 +892,7 @@ menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
config PCI
bool "PCI support"
+ depends on BROKEN
help
Support for PCI bus.
@@ -874,8 +910,8 @@ config HOTPLUG
plugged into slots found on all modern laptop computers. Another
example, used on modern desktops as well as laptops, is USB.
- Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
- software (at ) and install it.
+ Enable HOTPLUG and build a modular kernel. Get agent software
+ (from ) and install it.
Then your kernel will automatically call out to a user mode "policy
agent" (/sbin/hotplug) to load modules and set up software needed
to use devices as you hotplug them.
@@ -895,33 +931,50 @@ endmenu
menu "Power management options"
source "kernel/power/Kconfig"
+config ARCH_SUSPEND_POSSIBLE
+ def_bool y
+ depends on !SMP
+
choice
- prompt "Select PM Wakeup Event Source"
- default PM_WAKEUP_GPIO_BY_SIC_IWR
+ prompt "Standby Power Saving Mode"
depends on PM
+ default PM_BFIN_SLEEP_DEEPER
+config PM_BFIN_SLEEP_DEEPER
+ bool "Sleep Deeper"
help
- If you have a GPIO already configured as input with the corresponding PORTx_MASK
- bit set - "Specify Wakeup Event by SIC_IWR value"
-
-config PM_WAKEUP_GPIO_BY_SIC_IWR
- bool "Specify Wakeup Event by SIC_IWR value"
-config PM_WAKEUP_BY_GPIO
- bool "Cause Wakeup Event by GPIO"
-config PM_WAKEUP_GPIO_API
- bool "Configure Wakeup Event by PM GPIO API"
-
+ Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
+ power dissipation by disabling the clock to the processor core (CCLK).
+ Furthermore, Standby sets the internal power supply voltage (VDDINT)
+ to 0.85 V to provide the greatest power savings, while preserving the
+ processor state.
+ The PLL and system clock (SCLK) continue to operate at a very low
+ frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
+ the SDRAM is put into Self Refresh Mode. Typically an external event
+ such as GPIO interrupt or RTC activity wakes up the processor.
+ Various Peripherals such as UART, SPORT, PPI may not function as
+ normal during Sleep Deeper, due to the reduced SCLK frequency.
+ When in the sleep mode, system DMA access to L1 memory is not supported.
+
+ If unsure, select "Sleep Deeper".
+
+config PM_BFIN_SLEEP
+ bool "Sleep"
+ help
+ Sleep Mode (High Power Savings) - The sleep mode reduces power
+ dissipation by disabling the clock to the processor core (CCLK).
+ The PLL and system clock (SCLK), however, continue to operate in
+ this mode. Typically an external event or RTC activity will wake
+ up the processor. When in the sleep mode, system DMA access to L1
+ memory is not supported.
+
+ If unsure, select "Sleep Deeper".
endchoice
-config PM_WAKEUP_SIC_IWR
- hex "Wakeup Events (SIC_IWR)"
- depends on PM_WAKEUP_GPIO_BY_SIC_IWR
- default 0x80000000 if (BF537 || BF536 || BF534)
- default 0x100000 if (BF533 || BF532 || BF531)
- default 0x800000 if (BF54x)
- default 0x800000 if (BF52x)
+config PM_WAKEUP_BY_GPIO
+ bool "Allow Wakeup from Standby by GPIO"
config PM_WAKEUP_GPIO_NUMBER
- int "Wakeup GPIO number"
+ int "GPIO number"
range 0 47
depends on PM_WAKEUP_BY_GPIO
default 2 if BFIN537_STAMP
@@ -942,23 +995,40 @@ config PM_WAKEUP_GPIO_POLAR_EDGE_B
bool "Both EDGE"
endchoice
-endmenu
+comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
+ depends on PM
-if (BF537 || BF533 || BF54x)
+config PM_BFIN_WAKE_PH6
+ bool "Allow Wake-Up from on-chip PHY or PH6 GP"
+ depends on PM && (BF52x || BF534 || BF536 || BF537)
+ default n
+ help
+ Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
+
+config PM_BFIN_WAKE_GP
+ bool "Allow Wake-Up from GPIOs"
+ depends on PM && BF54x
+ default n
+ help
+ Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
+endmenu
menu "CPU Frequency scaling"
source "drivers/cpufreq/Kconfig"
-config CPU_FREQ
- bool
+config CPU_VOLTAGE
+ bool "CPU Voltage scaling"
+ depends on EXPERIMENTAL
+ depends on CPU_FREQ
default n
help
- If you want to enable this option, you should select the
- DPMC driver from Character Devices.
-endmenu
+ Say Y here if you want CPU voltage scaling according to the CPU frequency.
+ This option violates the PLL BYPASS recommendation in the Blackfin Processor
+ manuals. There is a theoretical risk that during VDDINT transitions
+ the PLL may unlock.
-endif
+endmenu
source "net/Kconfig"
@@ -966,8 +1036,6 @@ source "drivers/Kconfig"
source "fs/Kconfig"
-source "kernel/Kconfig.instrumentation"
-
source "arch/blackfin/Kconfig.debug"
source "security/Kconfig"