X-Git-Url: http://ftp.safe.ca/?a=blobdiff_plain;f=arch%2Fblackfin%2FKconfig;h=220635a1ebdd7b99437dbe93a7f2df81f48f35ca;hb=41ba653f24a39a0e6a4afe9b2763a95a57e042c2;hp=368bc7fe167e70c1400b38e30188dda6b87baa00;hpb=cfefe3c683e0d14c9ce3aeb883c55c7f30c20183;p=safe%2Fjmp%2Flinux-2.6
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 368bc7f..220635a 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -6,73 +6,72 @@
mainmenu "Blackfin Kernel Configuration"
config MMU
- bool
- default n
+ def_bool n
config FPU
- bool
- default n
+ def_bool n
config RWSEM_GENERIC_SPINLOCK
- bool
- default y
+ def_bool y
config RWSEM_XCHGADD_ALGORITHM
- bool
- default n
+ def_bool n
config BLACKFIN
- bool
- default y
+ def_bool y
+ select HAVE_FUNCTION_GRAPH_TRACER
+ select HAVE_FUNCTION_TRACER
+ select HAVE_IDE
+ select HAVE_KERNEL_GZIP
+ select HAVE_KERNEL_BZIP2
+ select HAVE_KERNEL_LZMA
select HAVE_OPROFILE
+ select ARCH_WANT_OPTIONAL_GPIOLIB
-config ZONE_DMA
- bool
- default y
+config GENERIC_BUG
+ def_bool y
+ depends on BUG
-config SEMAPHORE_SLEEPERS
- bool
- default y
+config ZONE_DMA
+ def_bool y
config GENERIC_FIND_NEXT_BIT
- bool
- default y
+ def_bool y
config GENERIC_HWEIGHT
- bool
- default y
+ def_bool y
config GENERIC_HARDIRQS
- bool
- default y
+ def_bool y
config GENERIC_IRQ_PROBE
- bool
- default y
-
-config GENERIC_TIME
- bool
- default n
+ def_bool y
config GENERIC_GPIO
- bool
- default y
+ def_bool y
config FORCE_MAX_ZONEORDER
int
default "14"
config GENERIC_CALIBRATE_DELAY
- bool
- default y
+ def_bool y
-config HARDWARE_PM
+config LOCKDEP_SUPPORT
+ def_bool y
+
+config STACKTRACE_SUPPORT
+ def_bool y
+
+config TRACE_IRQFLAGS_SUPPORT
def_bool y
- depends on OPROFILE
source "init/Kconfig"
+
source "kernel/Kconfig.preempt"
+source "kernel/Kconfig.freezer"
+
menu "Blackfin Processor Options"
comment "Processor and Board Settings"
@@ -81,6 +80,26 @@ choice
prompt "CPU"
default BF533
+config BF512
+ bool "BF512"
+ help
+ BF512 Processor Support.
+
+config BF514
+ bool "BF514"
+ help
+ BF514 Processor Support.
+
+config BF516
+ bool "BF516"
+ help
+ BF516 Processor Support.
+
+config BF518
+ bool "BF518"
+ help
+ BF518 Processor Support.
+
config BF522
bool "BF522"
help
@@ -141,68 +160,141 @@ config BF537
help
BF537 Processor Support.
+config BF538
+ bool "BF538"
+ help
+ BF538 Processor Support.
+
+config BF539
+ bool "BF539"
+ help
+ BF539 Processor Support.
+
config BF542
bool "BF542"
help
BF542 Processor Support.
+config BF542M
+ bool "BF542m"
+ help
+ BF542 Processor Support.
+
config BF544
bool "BF544"
help
BF544 Processor Support.
+config BF544M
+ bool "BF544m"
+ help
+ BF544 Processor Support.
+
config BF547
bool "BF547"
help
BF547 Processor Support.
+config BF547M
+ bool "BF547m"
+ help
+ BF547 Processor Support.
+
config BF548
bool "BF548"
help
BF548 Processor Support.
+config BF548M
+ bool "BF548m"
+ help
+ BF548 Processor Support.
+
config BF549
bool "BF549"
help
BF549 Processor Support.
+config BF549M
+ bool "BF549m"
+ help
+ BF549 Processor Support.
+
config BF561
bool "BF561"
help
- Not Supported Yet - Work in progress - BF561 Processor Support.
+ BF561 Processor Support.
endchoice
+config SMP
+ depends on BF561
+ select GENERIC_TIME
+ bool "Symmetric multi-processing support"
+ ---help---
+ This enables support for systems with more than one CPU,
+ like the dual core BF561. If you have a system with only one
+ CPU, say N. If you have a system with more than one CPU, say Y.
+
+ If you don't know what to do here, say N.
+
+config NR_CPUS
+ int
+ depends on SMP
+ default 2 if BF561
+
+config IRQ_PER_CPU
+ bool
+ depends on SMP
+ default y
+
+config BF_REV_MIN
+ int
+ default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
+ default 2 if (BF537 || BF536 || BF534)
+ default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
+ default 4 if (BF538 || BF539)
+
+config BF_REV_MAX
+ int
+ default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
+ default 3 if (BF537 || BF536 || BF534 || BF54xM)
+ default 5 if (BF561 || BF538 || BF539)
+ default 6 if (BF533 || BF532 || BF531)
+
choice
prompt "Silicon Rev"
- default BF_REV_0_1 if BF527
- default BF_REV_0_2 if BF537
- default BF_REV_0_3 if BF533
- default BF_REV_0_0 if BF549
+ default BF_REV_0_0 if (BF51x || BF52x)
+ default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
+ default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
config BF_REV_0_0
bool "0.0"
- depends on (BF52x || BF54x)
+ depends on (BF51x || BF52x || (BF54x && !BF54xM))
config BF_REV_0_1
bool "0.1"
- depends on (BF52x || BF54x)
+ depends on (BF51x || BF52x || (BF54x && !BF54xM))
config BF_REV_0_2
bool "0.2"
- depends on (BF537 || BF536 || BF534)
+ depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
config BF_REV_0_3
bool "0.3"
- depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
+ depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
config BF_REV_0_4
bool "0.4"
- depends on (BF561 || BF533 || BF532 || BF531)
+ depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
config BF_REV_0_5
bool "0.5"
- depends on (BF561 || BF533 || BF532 || BF531)
+ depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
+
+config BF_REV_0_6
+ bool "0.6"
+ depends on (BF533 || BF532 || BF531)
config BF_REV_ANY
bool "any"
@@ -212,6 +304,11 @@ config BF_REV_NONE
endchoice
+config BF51x
+ bool
+ depends on (BF512 || BF514 || BF516 || BF518)
+ default y
+
config BF52x
bool
depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
@@ -222,19 +319,14 @@ config BF53x
depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
default y
-config BF54x
- bool
- depends on (BF542 || BF544 || BF547 || BF548 || BF549)
- default y
-
-config BFIN_DUAL_CORE
+config BF54xM
bool
- depends on (BF561)
+ depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
default y
-config BFIN_SINGLE_CORE
+config BF54x
bool
- depends on !BFIN_DUAL_CORE
+ depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
default y
config MEM_GENERIC_BOARD
@@ -251,12 +343,12 @@ config MEM_MT48LC16M16A2TG_75
bool
depends on (BFIN533_EZKIT || BFIN561_EZKIT \
|| BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
- || H8606_HVSISTEMAS)
+ || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
default y
config MEM_MT48LC32M8A2_75
bool
- depends on (BFIN537_STAMP || PNAV10)
+ depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
default y
config MEM_MT48LC8M32B2B5_7
@@ -266,13 +358,20 @@ config MEM_MT48LC8M32B2B5_7
config MEM_MT48LC32M16A2TG_75
bool
- depends on (BFIN527_EZKIT)
+ depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
default y
+config MEM_MT48LC32M8A2_75
+ bool
+ depends on (BFIN518F_EZBRD)
+ default y
+
+source "arch/blackfin/mach-bf518/Kconfig"
source "arch/blackfin/mach-bf527/Kconfig"
source "arch/blackfin/mach-bf533/Kconfig"
source "arch/blackfin/mach-bf561/Kconfig"
source "arch/blackfin/mach-bf537/Kconfig"
+source "arch/blackfin/mach-bf538/Kconfig"
source "arch/blackfin/mach-bf548/Kconfig"
menu "Board customizations"
@@ -289,17 +388,42 @@ config CMDLINE
to the kernel, you may specify one here. As a minimum, you should specify
the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
+config BOOT_LOAD
+ hex "Kernel load address for booting"
+ default "0x1000"
+ range 0x1000 0x20000000
+ help
+ This option allows you to set the load address of the kernel.
+ This can be useful if you are on a board which has a small amount
+ of memory or you wish to reserve some memory at the beginning of
+ the address space.
+
+ Note that you need to keep this value above 4k (0x1000) as this
+ memory region is used to capture NULL pointer references as well
+ as some core kernel functions.
+
+config ROM_BASE
+ hex "Kernel ROM Base"
+ depends on ROMKERNEL
+ default "0x20040000"
+ range 0x20000000 0x20400000 if !(BF54x || BF561)
+ range 0x20000000 0x30000000 if (BF54x || BF561)
+ help
+
comment "Clock/PLL Setup"
config CLKIN_HZ
- int "Crystal Frequency in Hz"
+ int "Frequency of the crystal on the board in Hz"
+ default "10000000" if BFIN532_IP0X
default "11059200" if BFIN533_STAMP
+ default "24576000" if PNAV10
+ default "25000000" # most people use this
default "27000000" if BFIN533_EZKIT
- default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
default "30000000" if BFIN561_EZKIT
- default "24576000" if PNAV10
help
The frequency of CLKIN crystal oscillator on the board in Hz.
+ Warning: This value should match the crystal on the board. Otherwise,
+ peripherals won't work properly.
config BFIN_KERNEL_CLOCK
bool "Re-program Clocks while Kernel boots?"
@@ -328,12 +452,11 @@ config VCO_MULT
range 1 64
default "22" if BFIN533_EZKIT
default "45" if BFIN533_STAMP
- default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
+ default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
default "22" if BFIN533_BLUETECHNIX_CM
- default "20" if BFIN537_BLUETECHNIX_CM
- default "20" if BFIN561_BLUETECHNIX_CM
+ default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
default "20" if BFIN561_EZKIT
- default "16" if H8606_HVSISTEMAS
+ default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
help
This controls the frequency of the on-chip PLL. This can be between 1 and 64.
PLL Frequency = (Crystal Frequency) * (this setting)
@@ -363,24 +486,89 @@ config SCLK_DIV
int "System Clock Divider"
depends on BFIN_KERNEL_CLOCK
range 1 15
- default 5 if BFIN533_EZKIT
- default 5 if BFIN533_STAMP
- default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
- default 5 if BFIN533_BLUETECHNIX_CM
- default 4 if BFIN537_BLUETECHNIX_CM
- default 4 if BFIN561_BLUETECHNIX_CM
- default 5 if BFIN561_EZKIT
- default 3 if H8606_HVSISTEMAS
+ default 5
help
This sets the frequency of the system clock (including SDRAM or DDR).
This can be between 1 and 15
System Clock = (PLL frequency) / (this setting)
+choice
+ prompt "DDR SDRAM Chip Type"
+ depends on BFIN_KERNEL_CLOCK
+ depends on BF54x
+ default MEM_MT46V32M16_5B
+
+config MEM_MT46V32M16_6T
+ bool "MT46V32M16_6T"
+
+config MEM_MT46V32M16_5B
+ bool "MT46V32M16_5B"
+endchoice
+
+choice
+ prompt "DDR/SDRAM Timing"
+ depends on BFIN_KERNEL_CLOCK
+ default BFIN_KERNEL_CLOCK_MEMINIT_CALC
+ help
+ This option allows you to specify Blackfin SDRAM/DDR Timing parameters
+ The calculated SDRAM timing parameters may not be 100%
+ accurate - This option is therefore marked experimental.
+
+config BFIN_KERNEL_CLOCK_MEMINIT_CALC
+ bool "Calculate Timings (EXPERIMENTAL)"
+ depends on EXPERIMENTAL
+
+config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+ bool "Provide accurate Timings based on target SCLK"
+ help
+ Please consult the Blackfin Hardware Reference Manuals as well
+ as the memory device datasheet.
+ http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
+endchoice
+
+menu "Memory Init Control"
+ depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+
+config MEM_DDRCTL0
+ depends on BF54x
+ hex "DDRCTL0"
+ default 0x0
+
+config MEM_DDRCTL1
+ depends on BF54x
+ hex "DDRCTL1"
+ default 0x0
+
+config MEM_DDRCTL2
+ depends on BF54x
+ hex "DDRCTL2"
+ default 0x0
+
+config MEM_EBIU_DDRQUE
+ depends on BF54x
+ hex "DDRQUE"
+ default 0x0
+
+config MEM_SDRRC
+ depends on !BF54x
+ hex "SDRRC"
+ default 0x0
+
+config MEM_SDGCTL
+ depends on !BF54x
+ hex "SDGCTL"
+ default 0x0
+endmenu
+
#
# Max & Min Speeds for various Chips
#
config MAX_VCO_HZ
int
+ default 400000000 if BF512
+ default 400000000 if BF514
+ default 400000000 if BF516
+ default 400000000 if BF518
default 600000000 if BF522
default 400000000 if BF523
default 400000000 if BF524
@@ -418,66 +606,49 @@ comment "Kernel Timer/Scheduler"
source kernel/Kconfig.hz
-comment "Memory Setup"
-
-config MEM_SIZE
- int "SDRAM Memory Size in MBytes"
- default 32 if BFIN533_EZKIT
- default 64 if BFIN527_EZKIT
- default 64 if BFIN537_STAMP
- default 64 if BFIN548_EZKIT
- default 64 if BFIN561_EZKIT
- default 128 if BFIN533_STAMP
- default 64 if PNAV10
- default 32 if H8606_HVSISTEMAS
-
-config MEM_ADD_WIDTH
- int "SDRAM Memory Address Width"
- depends on (!BF54x)
- default 9 if BFIN533_EZKIT
- default 9 if BFIN561_EZKIT
- default 9 if H8606_HVSISTEMAS
- default 10 if BFIN527_EZKIT
- default 10 if BFIN537_STAMP
- default 11 if BFIN533_STAMP
- default 10 if PNAV10
+config GENERIC_TIME
+ bool "Generic time"
+ default y
+config GENERIC_CLOCKEVENTS
+ bool "Generic clock events"
+ depends on GENERIC_TIME
+ default y
choice
- prompt "DDR SDRAM Chip Type"
- depends on BFIN548_EZKIT
- default MEM_MT46V32M16_5B
+ prompt "Kernel Tick Source"
+ depends on GENERIC_CLOCKEVENTS
+ default TICKSOURCE_CORETMR
-config MEM_MT46V32M16_6T
- bool "MT46V32M16_6T"
+config TICKSOURCE_GPTMR0
+ bool "Gptimer0 (SCLK domain)"
+ select BFIN_GPTIMERS
+
+config TICKSOURCE_CORETMR
+ bool "Core timer (CCLK domain)"
-config MEM_MT46V32M16_5B
- bool "MT46V32M16_5B"
endchoice
-config ENET_FLASH_PIN
- int "PF port/pin used for flash and ethernet sharing"
- depends on (BFIN533_STAMP)
- default 0
+config CYCLES_CLOCKSOURCE
+ bool "Use 'CYCLES' as a clocksource"
+ depends on GENERIC_CLOCKEVENTS
+ depends on !BFIN_SCRATCH_REG_CYCLES
+ depends on !SMP
help
- PF port/pin used for flash and ethernet sharing to allow other PF
- pins to be used on other platforms without having to touch common
- code.
- For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
+ If you say Y here, you will enable support for using the 'cycles'
+ registers as a clock source. Doing so means you will be unable to
+ safely write to the 'cycles' register during runtime. You will
+ still be able to read it (such as for performance monitoring), but
+ writing the registers will most likely crash the kernel.
-config BOOT_LOAD
- hex "Kernel load address for booting"
- default "0x1000"
- range 0x1000 0x20000000
- help
- This option allows you to set the load address of the kernel.
- This can be useful if you are on a board which has a small amount
- of memory or you wish to reserve some memory at the beginning of
- the address space.
+config GPTMR0_CLOCKSOURCE
+ bool "Use GPTimer0 as a clocksource (higher rating)"
+ depends on GENERIC_CLOCKEVENTS
+ depends on !TICKSOURCE_GPTMR0
- Note that you need to keep this value above 4k (0x1000) as this
- memory region is used to capture NULL pointer references as well
- as some core kernel functions.
+source kernel/time/Kconfig
+
+comment "Misc"
choice
prompt "Blackfin Exception Scratch Register"
@@ -529,6 +700,7 @@ endmenu
menu "Blackfin Kernel Optimizations"
+ depends on !SMP
comment "Memory Optimizations"
@@ -623,7 +795,7 @@ config CACHELINE_ALIGNED_L1
default n if BF54x
depends on !BF531
help
- If enabled, cacheline_anligned data is linked
+ If enabled, cacheline_aligned data is linked
into L1 data memory. (less latency)
config SYSCALL_TAB_L1
@@ -642,8 +814,54 @@ config CPLB_SWITCH_TAB_L1
If enabled, the CPLB Switch Tables are linked
into L1 data memory. (less latency)
-endmenu
+config APP_STACK_L1
+ bool "Support locating application stack in L1 Scratch Memory"
+ default y
+ help
+ If enabled the application stack can be located in L1
+ scratch memory (less latency).
+ Currently only works with FLAT binaries.
+
+config EXCEPTION_L1_SCRATCH
+ bool "Locate exception stack in L1 Scratch Memory"
+ default n
+ depends on !APP_STACK_L1
+ help
+ Whenever an exception occurs, use the L1 Scratch memory for
+ stack storage. You cannot place the stacks of FLAT binaries
+ in L1 when using this option.
+
+ If you don't use L1 Scratch, then you should say Y here.
+
+comment "Speed Optimizations"
+config BFIN_INS_LOWOVERHEAD
+ bool "ins[bwl] low overhead, higher interrupt latency"
+ default y
+ help
+ Reads on the Blackfin are speculative. In Blackfin terms, this means
+ they can be interrupted at any time (even after they have been issued
+ on to the external bus), and re-issued after the interrupt occurs.
+ For memory - this is not a big deal, since memory does not change if
+ it sees a read.
+
+ If a FIFO is sitting on the end of the read, it will see two reads,
+ when the core only sees one since the FIFO receives both the read
+ which is cancelled (and not delivered to the core) and the one which
+ is re-issued (which is delivered to the core).
+
+ To solve this, interrupts are turned off before reads occur to
+ I/O space. This option controls which the overhead/latency of
+ controlling interrupts during this time
+ "n" turns interrupts off every read
+ (higher overhead, but lower interrupt latency)
+ "y" turns interrupts off every loop
+ (low overhead, but longer interrupt latency)
+
+ default behavior is to leave this set to on (type "Y"). If you are experiencing
+ interrupt latency issues, it is safe and OK to turn this off.
+
+endmenu
choice
prompt "Kernel executes from"
@@ -664,14 +882,6 @@ endchoice
source "mm/Kconfig"
-config LARGE_ALLOCS
- bool "Allow allocating large blocks (> 1MB) of memory"
- help
- Allow the slab memory allocator to keep chains for very large
- memory sizes - upto 32MB. You may need this if your system has
- a lot of RAM, and you need to able to allocate very large
- contiguous chunks. If unsure, say N.
-
config BFIN_GPTIMERS
tristate "Enable Blackfin General Purpose Timers API"
default n
@@ -680,19 +890,13 @@ config BFIN_GPTIMERS
are unsure, say N.
To compile this driver as a module, choose M here: the module
- will be called gptimers.ko.
-
-config BFIN_DMA_5XX
- bool "Enable DMA Support"
- depends on (BF52x || BF53x || BF561 || BF54x)
- default y
- help
- DMA driver for BF5xx.
+ will be called gptimers.
choice
- prompt "Uncached SDRAM region"
+ prompt "Uncached DMA region"
default DMA_UNCACHED_1M
- depends on BFIN_DMA_5XX
+config DMA_UNCACHED_4M
+ bool "Enable 4M DMA region"
config DMA_UNCACHED_2M
bool "Enable 2M DMA region"
config DMA_UNCACHED_1M
@@ -703,23 +907,43 @@ endchoice
comment "Cache Support"
+
config BFIN_ICACHE
bool "Enable ICACHE"
+ default y
+config BFIN_ICACHE_LOCK
+ bool "Enable Instruction Cache Locking"
+ depends on BFIN_ICACHE
+ default n
+config BFIN_EXTMEM_ICACHEABLE
+ bool "Enable ICACHE for external memory"
+ depends on BFIN_ICACHE
+ default y
+config BFIN_L2_ICACHEABLE
+ bool "Enable ICACHE for L2 SRAM"
+ depends on BFIN_ICACHE
+ depends on BF54x || BF561
+ default n
+
config BFIN_DCACHE
bool "Enable DCACHE"
+ default y
config BFIN_DCACHE_BANKA
bool "Enable only 16k BankA DCACHE - BankB is SRAM"
depends on BFIN_DCACHE && !BF531
default n
-config BFIN_ICACHE_LOCK
- bool "Enable Instruction Cache Locking"
-
-choice
- prompt "Policy"
+config BFIN_EXTMEM_DCACHEABLE
+ bool "Enable DCACHE for external memory"
depends on BFIN_DCACHE
- default BFIN_WB
-config BFIN_WB
+ default y
+choice
+ prompt "External memory DCACHE policy"
+ depends on BFIN_EXTMEM_DCACHEABLE
+ default BFIN_EXTMEM_WRITEBACK if !SMP
+ default BFIN_EXTMEM_WRITETHROUGH if SMP
+config BFIN_EXTMEM_WRITEBACK
bool "Write back"
+ depends on !SMP
help
Write Back Policy:
Cached data will be written back to SDRAM only when needed.
@@ -735,7 +959,7 @@ config BFIN_WB
If you are unsure of the options and you want to be safe,
then go with Write Through.
-config BFIN_WT
+config BFIN_EXTMEM_WRITETHROUGH
bool "Write through"
help
Write Back Policy:
@@ -754,14 +978,26 @@ config BFIN_WT
endchoice
-config L1_MAX_PIECE
- int "Set the max L1 SRAM pieces"
- default 16
- help
- Set the max memory pieces for the L1 SRAM allocation algorithm.
- Min value is 16. Max value is 1024.
+config BFIN_L2_DCACHEABLE
+ bool "Enable DCACHE for L2 SRAM"
+ depends on BFIN_DCACHE
+ depends on BF54x || BF561
+ default n
+choice
+ prompt "L2 SRAM DCACHE policy"
+ depends on BFIN_L2_DCACHEABLE
+ default BFIN_L2_WRITEBACK
+config BFIN_L2_WRITEBACK
+ bool "Write back"
+ depends on !SMP
+config BFIN_L2_WRITETHROUGH
+ bool "Write through"
+ depends on !SMP
+endchoice
+
+comment "Memory Protection Unit"
config MPU
bool "Enable the memory protection unit (EXPERIMENTAL)"
default n
@@ -770,7 +1006,7 @@ config MPU
memory they do not own. This comes at a performance penalty
and is recommended only for debugging.
-comment "Asynchonous Memory Configuration"
+comment "Asynchronous Memory Configuration"
menu "EBIU_AMGCTL Global Control"
config C_AMCKEN
@@ -802,7 +1038,7 @@ config C_B3PEN
default n
choice
- prompt"Enable Asynchonous Memory Banks"
+ prompt "Enable Asynchronous Memory Banks"
default C_AMBEN_ALL
config C_AMBEN
@@ -824,20 +1060,34 @@ endmenu
menu "EBIU_AMBCTL Control"
config BANK_0
- hex "Bank 0"
+ hex "Bank 0 (AMBCTL0.L)"
default 0x7BB0
+ help
+ These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
+ used to control the Asynchronous Memory Bank 0 settings.
config BANK_1
- hex "Bank 1"
+ hex "Bank 1 (AMBCTL0.H)"
default 0x7BB0
+ default 0x5558 if BF54x
+ help
+ These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
+ used to control the Asynchronous Memory Bank 1 settings.
config BANK_2
- hex "Bank 2"
+ hex "Bank 2 (AMBCTL1.L)"
default 0x7BB0
+ help
+ These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
+ used to control the Asynchronous Memory Bank 2 settings.
config BANK_3
- hex "Bank 3"
+ hex "Bank 3 (AMBCTL1.H)"
default 0x99B3
+ help
+ These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
+ used to control the Asynchronous Memory Bank 3 settings.
+
endmenu
config EBIU_MBSCTLVAL
@@ -861,6 +1111,7 @@ menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
config PCI
bool "PCI support"
+ depends on BROKEN
help
Support for PCI bus.
@@ -878,8 +1129,8 @@ config HOTPLUG
plugged into slots found on all modern laptop computers. Another
example, used on modern desktops as well as laptops, is USB.
- Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
- software (at ) and install it.
+ Enable HOTPLUG and build a modular kernel. Get agent software
+ (from ) and install it.
Then your kernel will automatically call out to a user mode "policy
agent" (/sbin/hotplug) to load modules and set up software needed
to use devices as you hotplug them.
@@ -904,7 +1155,7 @@ config ARCH_SUSPEND_POSSIBLE
depends on !SMP
choice
- prompt "Default Power Saving Mode"
+ prompt "Standby Power Saving Mode"
depends on PM
default PM_BFIN_SLEEP_DEEPER
config PM_BFIN_SLEEP_DEEPER
@@ -923,6 +1174,8 @@ config PM_BFIN_SLEEP_DEEPER
normal during Sleep Deeper, due to the reduced SCLK frequency.
When in the sleep mode, system DMA access to L1 memory is not supported.
+ If unsure, select "Sleep Deeper".
+
config PM_BFIN_SLEEP
bool "Sleep"
help
@@ -930,18 +1183,21 @@ config PM_BFIN_SLEEP
dissipation by disabling the clock to the processor core (CCLK).
The PLL and system clock (SCLK), however, continue to operate in
this mode. Typically an external event or RTC activity will wake
- up the processor. When in the sleep mode,
- system DMA access to L1 memory is not supported.
+ up the processor. When in the sleep mode, system DMA access to L1
+ memory is not supported.
+
+ If unsure, select "Sleep Deeper".
endchoice
config PM_WAKEUP_BY_GPIO
- bool "Cause Wakeup Event by GPIO"
+ bool "Allow Wakeup from Standby by GPIO"
+ depends on PM && !BF54x
config PM_WAKEUP_GPIO_NUMBER
- int "Wakeup GPIO number"
+ int "GPIO number"
range 0 47
depends on PM_WAKEUP_BY_GPIO
- default 2 if BFIN537_STAMP
+ default 2
choice
prompt "GPIO Polarity"
@@ -959,23 +1215,52 @@ config PM_WAKEUP_GPIO_POLAR_EDGE_B
bool "Both EDGE"
endchoice
-endmenu
+comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
+ depends on PM
+
+config PM_BFIN_WAKE_PH6
+ bool "Allow Wake-Up from on-chip PHY or PH6 GP"
+ depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
+ default n
+ help
+ Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
+
+config PM_BFIN_WAKE_GP
+ bool "Allow Wake-Up from GPIOs"
+ depends on PM && BF54x
+ default n
+ help
+ Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
+ (all processors, except ADSP-BF549). This option sets
+ the general-purpose wake-up enable (GPWE) control bit to enable
+ wake-up upon detection of an active low signal on the /GPW (PH7) pin.
+ On ADSP-BF549 this option enables the the same functionality on the
+ /MRXON pin also PH7.
-if (BF537 || BF533 || BF54x)
+endmenu
menu "CPU Frequency scaling"
source "drivers/cpufreq/Kconfig"
-config CPU_FREQ
+config BFIN_CPU_FREQ
bool
+ depends on CPU_FREQ
+ select CPU_FREQ_TABLE
+ default y
+
+config CPU_VOLTAGE
+ bool "CPU Voltage scaling"
+ depends on EXPERIMENTAL
+ depends on CPU_FREQ
default n
help
- If you want to enable this option, you should select the
- DPMC driver from Character Devices.
-endmenu
+ Say Y here if you want CPU voltage scaling according to the CPU frequency.
+ This option violates the PLL BYPASS recommendation in the Blackfin Processor
+ manuals. There is a theoretical risk that during VDDINT transitions
+ the PLL may unlock.
-endif
+endmenu
source "net/Kconfig"