* Definitions for any platform device related flags or structures for
* Freescale processor devices
*
- * Maintainer: Kumar Gala (kumar.gala@freescale.com)
+ * Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2004 Freescale Semiconductor, Inc
*
* option) any later version.
*/
-#ifdef __KERNEL__
#ifndef _FSL_DEVICE_H_
#define _FSL_DEVICE_H_
*
*/
-struct gianfar_platform_data {
- /* device specific information */
- u32 device_flags;
- u32 phy_reg_addr;
+enum fsl_usb2_operating_modes {
+ FSL_USB2_MPH_HOST,
+ FSL_USB2_DR_HOST,
+ FSL_USB2_DR_DEVICE,
+ FSL_USB2_DR_OTG,
+};
+
+enum fsl_usb2_phy_modes {
+ FSL_USB2_PHY_NONE,
+ FSL_USB2_PHY_ULPI,
+ FSL_USB2_PHY_UTMI,
+ FSL_USB2_PHY_UTMI_WIDE,
+ FSL_USB2_PHY_SERIAL,
+};
+struct fsl_usb2_platform_data {
/* board specific information */
- u32 board_flags;
- u32 phyid;
- u32 interruptPHY;
- u8 mac_addr[6];
+ enum fsl_usb2_operating_modes operating_mode;
+ enum fsl_usb2_phy_modes phy_mode;
+ unsigned int port_enables;
};
-/* Flags related to gianfar device features */
-#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
-#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
-#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
-#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
+/* Flags in fsl_usb2_mph_platform_data */
+#define FSL_USB2_PORT0_ENABLED 0x00000001
+#define FSL_USB2_PORT1_ENABLED 0x00000002
-/* Flags in gianfar_platform_data */
-#define FSL_GIANFAR_BRD_HAS_PHY_INTR 0x00000001 /* if not set use a timer */
+struct spi_device;
-struct fsl_i2c_platform_data {
- /* device specific information */
- u32 device_flags;
+struct fsl_spi_platform_data {
+ u32 initial_spmode; /* initial SPMODE value */
+ s16 bus_num;
+ unsigned int flags;
+#define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */
+#define SPI_CPM_MODE (1 << 1) /* CPM/QE ("DMA") mode */
+#define SPI_CPM1 (1 << 2) /* SPI unit is in CPM1 block */
+#define SPI_CPM2 (1 << 3) /* SPI unit is in CPM2 block */
+#define SPI_QE (1 << 4) /* SPI unit is in QE block */
+ /* board specific information */
+ u16 max_chipselect;
+ void (*cs_control)(struct spi_device *spi, bool on);
+ u32 sysclk;
};
-/* Flags related to I2C device features */
-#define FSL_I2C_DEV_SEPARATE_DFSRR 0x00000001
-#define FSL_I2C_DEV_CLOCK_5200 0x00000002
+struct mpc8xx_pcmcia_ops {
+ void(*hw_ctrl)(int slot, int enable);
+ int(*voltage_set)(int slot, int vcc, int vpp);
+};
+
+/* Returns non-zero if the current suspend operation would
+ * lead to a deep sleep (i.e. power removed from the core,
+ * instead of just the clock).
+ */
+#if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND)
+int fsl_deep_sleep(void);
+#else
+static inline int fsl_deep_sleep(void) { return 0; }
+#endif
-#endif /* _FSL_DEVICE_H_ */
-#endif /* __KERNEL__ */
+#endif /* _FSL_DEVICE_H_ */