vga16fb, drm: vga16fb->drm handoff

[safe/jmp/linux-2.6] / include / linux / fsl_devices.h

diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 3da29e2..28e33fe 100644 (file)
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -14,7 +14,6 @@
  * option) any later version.
  */
 
-#ifdef __KERNEL__
 #ifndef _FSL_DEVICE_H_
 #define _FSL_DEVICE_H_
 
@@ -44,44 +43,6 @@
  *
  */
 
-struct gianfar_platform_data {
-       /* device specific information */
-       u32     device_flags;
-       /* board specific information */
-       u32     board_flags;
-       u32     bus_id;
-       u32     phy_id;
-       u8      mac_addr[6];
-};
-
-struct gianfar_mdio_data {
-       /* board specific information */
-       int     irq[32];
-};
-
-/* Flags related to gianfar device features */
-#define FSL_GIANFAR_DEV_HAS_GIGABIT            0x00000001
-#define FSL_GIANFAR_DEV_HAS_COALESCE           0x00000002
-#define FSL_GIANFAR_DEV_HAS_RMON               0x00000004
-#define FSL_GIANFAR_DEV_HAS_MULTI_INTR         0x00000008
-#define FSL_GIANFAR_DEV_HAS_CSUM               0x00000010
-#define FSL_GIANFAR_DEV_HAS_VLAN               0x00000020
-#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH      0x00000040
-#define FSL_GIANFAR_DEV_HAS_PADDING            0x00000080
-
-/* Flags in gianfar_platform_data */
-#define FSL_GIANFAR_BRD_HAS_PHY_INTR   0x00000001 /* set or use a timer */
-#define FSL_GIANFAR_BRD_IS_REDUCED     0x00000002 /* Set if RGMII, RMII */
-
-struct fsl_i2c_platform_data {
-       /* device specific information */
-       u32     device_flags;
-};
-
-/* Flags related to I2C device features */
-#define FSL_I2C_DEV_SEPARATE_DFSRR     0x00000001
-#define FSL_I2C_DEV_CLOCK_5200         0x00000002
-
 enum fsl_usb2_operating_modes {
        FSL_USB2_MPH_HOST,
        FSL_USB2_DR_HOST,
@@ -108,55 +69,36 @@ struct fsl_usb2_platform_data {
 #define FSL_USB2_PORT0_ENABLED 0x00000001
 #define FSL_USB2_PORT1_ENABLED 0x00000002
 
+struct spi_device;
+
 struct fsl_spi_platform_data {
        u32     initial_spmode; /* initial SPMODE value */
-       u16     bus_num;
-
+       s16     bus_num;
+       unsigned int flags;
+#define SPI_QE_CPU_MODE                (1 << 0) /* QE CPU ("PIO") mode */
+#define SPI_CPM_MODE           (1 << 1) /* CPM/QE ("DMA") mode */
+#define SPI_CPM1               (1 << 2) /* SPI unit is in CPM1 block */
+#define SPI_CPM2               (1 << 3) /* SPI unit is in CPM2 block */
+#define SPI_QE                 (1 << 4) /* SPI unit is in QE block */
        /* board specific information */
        u16     max_chipselect;
-       void    (*activate_cs)(u8 cs, u8 polarity);
-       void    (*deactivate_cs)(u8 cs, u8 polarity);
+       void    (*cs_control)(struct spi_device *spi, bool on);
        u32     sysclk;
 };
 
-/* Ethernet interface (phy management and speed)
-*/
-enum enet_interface {
-       ENET_10_MII,            /* 10 Base T,   MII interface */
-       ENET_10_RMII,           /* 10 Base T,  RMII interface */
-       ENET_10_RGMII,          /* 10 Base T, RGMII interface */
-       ENET_100_MII,           /* 100 Base T,   MII interface */
-       ENET_100_RMII,          /* 100 Base T,  RMII interface */
-       ENET_100_RGMII,         /* 100 Base T, RGMII interface */
-       ENET_1000_GMII,         /* 1000 Base T,  GMII interface */
-       ENET_1000_RGMII,        /* 1000 Base T, RGMII interface */
-       ENET_1000_TBI,          /* 1000 Base T,   TBI interface */
-       ENET_1000_RTBI          /* 1000 Base T,  RTBI interface */
+struct mpc8xx_pcmcia_ops {
+       void(*hw_ctrl)(int slot, int enable);
+       int(*voltage_set)(int slot, int vcc, int vpp);
 };
 
-struct ucc_geth_platform_data {
-       /* device specific information */
-       u32                     device_flags;
-       u32                     phy_reg_addr;
-
-       /* board specific information */
-       u32                     board_flags;
-       u8                      rx_clock;
-       u8                      tx_clock;
-       u32                     phy_id;
-       enum enet_interface     phy_interface;
-       u32                     phy_interrupt;
-       u8                      mac_addr[6];
-};
-
-/* Flags related to UCC Gigabit Ethernet device features */
-#define FSL_UGETH_DEV_HAS_GIGABIT              0x00000001
-#define FSL_UGETH_DEV_HAS_COALESCE             0x00000002
-#define FSL_UGETH_DEV_HAS_RMON                 0x00000004
-
-/* Flags in ucc_geth_platform_data */
-#define FSL_UGETH_BRD_HAS_PHY_INTR             0x00000001
-                               /* if not set use a timer */
+/* Returns non-zero if the current suspend operation would
+ * lead to a deep sleep (i.e. power removed from the core,
+ * instead of just the clock).
+ */
+#if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND)
+int fsl_deep_sleep(void);
+#else
+static inline int fsl_deep_sleep(void) { return 0; }
+#endif
 
 #endif /* _FSL_DEVICE_H_ */
-#endif /* __KERNEL__ */