tty: i386/x86_64 arbitary speed support

[safe/jmp/linux-2.6] / include / asm-x86_64 / cache.h

diff --git a/include/asm-x86_64/cache.h b/include/asm-x86_64/cache.h
index 33e5342..052df75 100644 (file)
--- a/include/asm-x86_64/cache.h
+++ b/include/asm-x86_64/cache.h
@@ -1,14 +1,26 @@
 /*
- * include/asm-x8664/cache.h
+ * include/asm-x86_64/cache.h
  */
 #ifndef __ARCH_X8664_CACHE_H
 #define __ARCH_X8664_CACHE_H
 
-#include <linux/config.h>
 
 /* L1 cache line size */
 #define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#define L1_CACHE_SHIFT_MAX 7   /* largest L1 which this arch supports */
+
+#ifdef CONFIG_X86_VSMP
+
+/* vSMP Internode cacheline shift */
+#define INTERNODE_CACHE_SHIFT (12)
+#ifdef CONFIG_SMP
+#define __cacheline_aligned_in_smp                                     \
+       __attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT))))         \
+       __attribute__((__section__(".data.page_aligned")))
+#endif
+
+#endif
+
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
 
 #endif