x86: use generic register name in the thread and tss structures

[safe/jmp/linux-2.6] / include / asm-x86 / system_32.h

diff --git a/include/asm-x86/system_32.h b/include/asm-x86/system_32.h
index d69ba93..f5b3f77 100644 (file)
--- a/include/asm-x86/system_32.h
+++ b/include/asm-x86/system_32.h
@@ -7,6 +7,7 @@
 #include <asm/cmpxchg.h>
 
 #ifdef __KERNEL__
+#define AT_VECTOR_SIZE_ARCH 2 /* entries in ARCH_DLINFO */
 
 struct task_struct;    /* one of the stranger aspects of C forward declarations.. */
 extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
@@ -27,9 +28,9 @@ extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struc
                     "1:\t"                                             \
                     "popl %%ebp\n\t"                                   \
                     "popfl"                                            \
-                    :"=m" (prev->thread.esp),"=m" (prev->thread.eip),  \
+                    :"=m" (prev->thread.sp),"=m" (prev->thread.ip),    \
                      "=a" (last),"=S" (esi),"=D" (edi)                 \
-                    :"m" (next->thread.esp),"m" (next->thread.eip),    \
+                    :"m" (next->thread.sp),"m" (next->thread.ip),      \
                      "2" (prev), "d" (next));                          \
 } while (0)
 
@@ -141,7 +142,7 @@ static inline unsigned long native_read_cr4_safe(void)
 {
        unsigned long val;
        /* This could fault if %cr4 does not exist */
-       asm("1: movl %%cr4, %0          \n"
+       asm volatile("1: movl %%cr4, %0         \n"
                "2:                             \n"
                ".section __ex_table,\"a\"      \n"
                ".long 1b,2b                    \n"
@@ -160,6 +161,10 @@ static inline void native_wbinvd(void)
        asm volatile("wbinvd": : :"memory");
 }
 
+static inline void clflush(volatile void *__p)
+{
+       asm volatile("clflush %0" : "+m" (*(char __force *)__p));
+}
 
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
@@ -216,6 +221,7 @@ static inline unsigned long get_limit(unsigned long segment)
 
 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
+#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 
 /**
  * read_barrier_depends - Flush all pending reads that subsequents reads
@@ -271,18 +277,18 @@ static inline unsigned long get_limit(unsigned long segment)
 
 #define read_barrier_depends() do { } while(0)
 
+#ifdef CONFIG_SMP
+#define smp_mb()       mb()
+#ifdef CONFIG_X86_PPRO_FENCE
+# define smp_rmb()     rmb()
+#else
+# define smp_rmb()     barrier()
+#endif
 #ifdef CONFIG_X86_OOSTORE
-/* Actually there are no OOO store capable CPUs for now that do SSE, 
-   but make it already an possibility. */
-#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
+# define smp_wmb()     wmb()
 #else
-#define wmb()  __asm__ __volatile__ ("": : :"memory")
+# define smp_wmb()     barrier()
 #endif
-
-#ifdef CONFIG_SMP
-#define smp_mb()       mb()
-#define smp_rmb()      rmb()
-#define smp_wmb()      wmb()
 #define smp_read_barrier_depends()     read_barrier_depends()
 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 #else