AMD IOMMU: add MSI interrupt support

[safe/jmp/linux-2.6] / include / asm-x86 / amd_iommu_types.h

diff --git a/include/asm-x86/amd_iommu_types.h b/include/asm-x86/amd_iommu_types.h
index dcc4724..8533f09 100644 (file)
--- a/include/asm-x86/amd_iommu_types.h
+++ b/include/asm-x86/amd_iommu_types.h
@@ -37,6 +37,7 @@
 /* Capability offsets used by the driver */
 #define MMIO_CAP_HDR_OFFSET    0x00
 #define MMIO_RANGE_OFFSET      0x0c
+#define MMIO_MISC_OFFSET       0x10
 
 /* Masks, shifts and macros to parse the device range capability */
 #define MMIO_RANGE_LD_MASK     0xff000000
@@ -48,6 +49,7 @@
 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
+#define MMIO_MSI_NUM(x)        ((x) & 0x1f)
 
 /* Flag masks for the AMD IOMMU exclusion range */
 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
@@ -116,6 +118,10 @@
 #define MMIO_CMD_SIZE_SHIFT 56
 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
 
+/* constants for event buffer handling */
+#define EVT_BUFFER_SIZE                8192 /* 512 entries */
+#define EVT_LEN_MASK           (0x9ULL << 56)
+
 #define PAGE_MODE_1_LEVEL 0x01
 #define PAGE_MODE_2_LEVEL 0x02
 #define PAGE_MODE_3_LEVEL 0x03
@@ -211,8 +217,9 @@ struct amd_iommu {
        /* locks the accesses to the hardware */
        spinlock_t lock;
 
-       /* device id of this IOMMU */
-       u16 devid;
+       /* Pointer to PCI device of this IOMMU */
+       struct pci_dev *dev;
+
        /*
         * Capability pointer. There could be more than one IOMMU per PCI
         * device function if there are more than one AMD IOMMU capability
@@ -228,6 +235,9 @@ struct amd_iommu {
        /* capabilities of that IOMMU read from ACPI */
        u32 cap;
 
+       /* pci domain of this IOMMU */
+       u16 pci_seg;
+
        /* first device this IOMMU handles. read from PCI */
        u16 first_device;
        /* last device this IOMMU handles. read from PCI */
@@ -243,9 +253,19 @@ struct amd_iommu {
        /* size of command buffer */
        u32 cmd_buf_size;
 
+       /* event buffer virtual address */
+       u8 *evt_buf;
+       /* size of event buffer */
+       u32 evt_buf_size;
+       /* MSI number for event interrupt */
+       u16 evt_msi_num;
+
        /* if one, we need to send a completion wait command */
        int need_sync;
 
+       /* true if interrupts for this IOMMU are already enabled */
+       bool int_enabled;
+
        /* default dma_ops domain for that IOMMU */
        struct dma_ops_domain *default_dom;
 };