/* asm-sparc/floppy.h: Sparc specific parts of the Floppy driver.
*
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
*/
#ifndef __ASM_SPARC_FLOPPY_H
/* You'll only ever find one controller on a SparcStation anyways. */
static struct sun_flpy_controller *sun_fdc = NULL;
-volatile unsigned char *fdc_status;
+extern volatile unsigned char *fdc_status;
struct sun_floppy_ops {
unsigned char (*fd_inb)(int port);
#define fd_dma_mem_free(addr,size) (vfree((void *)(addr)))
#endif
-#define FLOPPY_MOTOR_MASK 0x10
-
/* XXX This isn't really correct. XXX */
#define get_dma_residue(x) (0)
#define CROSS_64KB(a,s) (0)
/* Routines unique to each controller type on a Sun. */
+static void sun_set_dor(unsigned char value, int fdc_82077)
+{
+ if (sparc_cpu_model == sun4c) {
+ unsigned int bits = 0;
+ if (value & 0x10)
+ bits |= AUXIO_FLPY_DSEL;
+ if ((value & 0x80) == 0)
+ bits |= AUXIO_FLPY_EJCT;
+ set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT));
+ }
+ if (fdc_82077) {
+ sun_fdc->dor_82077 = value;
+ }
+}
+
+static unsigned char sun_read_dir(void)
+{
+ if (sparc_cpu_model == sun4c)
+ return (get_auxio() & AUXIO_FLPY_DCHG) ? 0x80 : 0;
+ else
+ return sun_fdc->dir_82077;
+}
+
static unsigned char sun_82072_fd_inb(int port)
{
udelay(5);
case 5: /* FD_DATA */
return sun_fdc->data_82072;
case 7: /* FD_DIR */
- return (get_auxio() & AUXIO_FLPY_DCHG)? 0x80: 0;
+ return sun_read_dir();
};
panic("sun_82072_fd_inb: How did I get here?");
}
printk("floppy: Asked to write to unknown port %d\n", port);
panic("floppy: Port bolixed.");
case 2: /* FD_DOR */
- /* Oh geese, 82072 on the Sun has no DOR register,
- * the functionality is implemented via the AUXIO
- * I/O register. So we must emulate the behavior.
- *
- * ASSUMPTIONS: There will only ever be one floppy
- * drive attached to a Sun controller
- * and it will be at drive zero.
- */
- {
- unsigned bits = 0;
- if (value & 0x10) bits |= AUXIO_FLPY_DSEL;
- if ((value & 0x80) == 0) bits |= AUXIO_FLPY_EJCT;
- set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT));
- }
+ sun_set_dor(value, 0);
break;
case 5: /* FD_DATA */
sun_fdc->data_82072 = value;
default:
printk("floppy: Asked to read unknown port %d\n", port);
panic("floppy: Port bolixed.");
+ case 0: /* FD_STATUS_0 */
+ return sun_fdc->status1_82077;
+ case 1: /* FD_STATUS_1 */
+ return sun_fdc->status2_82077;
+ case 2: /* FD_DOR */
+ return sun_fdc->dor_82077;
+ case 3: /* FD_TDR */
+ return sun_fdc->tapectl_82077;
case 4: /* FD_STATUS */
return sun_fdc->status_82077 & ~STATUS_DMA;
case 5: /* FD_DATA */
return sun_fdc->data_82077;
case 7: /* FD_DIR */
- /* XXX: Is DCL on 0x80 in sun4m? */
- return sun_fdc->dir_82077;
+ return sun_read_dir();
};
- panic("sun_82072_fd_inb: How did I get here?");
+ panic("sun_82077_fd_inb: How did I get here?");
}
static void sun_82077_fd_outb(unsigned char value, int port)
printk("floppy: Asked to write to unknown port %d\n", port);
panic("floppy: Port bolixed.");
case 2: /* FD_DOR */
- /* Happily, the 82077 has a real DOR register. */
- sun_fdc->dor_82077 = value;
+ sun_set_dor(value, 1);
break;
case 5: /* FD_DATA */
sun_fdc->data_82077 = value;
case 4: /* FD_STATUS */
sun_fdc->status_82077 = value;
break;
+ case 3: /* FD_TDR */
+ sun_fdc->tapectl_82077 = value;
+ break;
};
return;
}
* underruns. If non-zero, doing_pdma encodes the direction of
* the transfer for debugging. 1=read 2=write
*/
-char *pdma_vaddr;
-unsigned long pdma_size;
-volatile int doing_pdma = 0;
+extern char *pdma_vaddr;
+extern unsigned long pdma_size;
+extern volatile int doing_pdma;
/* This is software state */
-char *pdma_base = NULL;
-unsigned long pdma_areasize;
+extern char *pdma_base;
+extern unsigned long pdma_areasize;
/* Common routines to all controller types on the Sparc. */
-static __inline__ void virtual_dma_init(void)
+static inline void virtual_dma_init(void)
{
/* nothing... */
}
-static __inline__ void sun_fd_disable_dma(void)
+static inline void sun_fd_disable_dma(void)
{
doing_pdma = 0;
if (pdma_base) {
}
}
-static __inline__ void sun_fd_set_dma_mode(int mode)
+static inline void sun_fd_set_dma_mode(int mode)
{
switch(mode) {
case DMA_MODE_READ:
}
}
-static __inline__ void sun_fd_set_dma_addr(char *buffer)
+static inline void sun_fd_set_dma_addr(char *buffer)
{
pdma_vaddr = buffer;
}
-static __inline__ void sun_fd_set_dma_count(int length)
+static inline void sun_fd_set_dma_count(int length)
{
pdma_size = length;
}
-static __inline__ void sun_fd_enable_dma(void)
+static inline void sun_fd_enable_dma(void)
{
pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
pdma_base = pdma_vaddr;
}
/* Our low-level entry point in arch/sparc/kernel/entry.S */
-irqreturn_t floppy_hardint(int irq, void *unused, struct pt_regs *regs);
+extern int sparc_floppy_request_irq(int irq, unsigned long flags,
+ irqreturn_t (*irq_handler)(int irq, void *));
static int sun_fd_request_irq(void)
{
if(!once) {
once = 1;
- error = request_fast_irq(FLOPPY_IRQ, floppy_hardint,
- IRQF_DISABLED, "floppy");
+ error = sparc_floppy_request_irq(FLOPPY_IRQ,
+ IRQF_DISABLED,
+ floppy_interrupt);
return ((error == 0) ? 0 : -1);
} else return 0;
}
goto no_sun_fdc;
}
- if(sparc_cpu_model == sun4c) {
- sun_fdops.fd_inb = sun_82072_fd_inb;
- sun_fdops.fd_outb = sun_82072_fd_outb;
- fdc_status = &sun_fdc->status_82072;
- /* printk("AUXIO @0x%lx\n", auxio_register); */ /* P3 */
- } else {
- sun_fdops.fd_inb = sun_82077_fd_inb;
- sun_fdops.fd_outb = sun_82077_fd_outb;
- fdc_status = &sun_fdc->status_82077;
- /* printk("DOR @0x%p\n", &sun_fdc->dor_82077); */ /* P3 */
+ sun_fdops.fd_inb = sun_82077_fd_inb;
+ sun_fdops.fd_outb = sun_82077_fd_outb;
+ fdc_status = &sun_fdc->status_82077;
+
+ if (sun_fdc->dor_82077 == 0x80) {
+ sun_fdc->dor_82077 = 0x02;
+ if (sun_fdc->dor_82077 == 0x80) {
+ sun_fdops.fd_inb = sun_82072_fd_inb;
+ sun_fdops.fd_outb = sun_82072_fd_outb;
+ fdc_status = &sun_fdc->status_82072;
+ }
}
/* Success... */
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