mm: dont clear PG_uptodate on truncate/invalidate

[safe/jmp/linux-2.6] / include / asm-mips / smtc.h

diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index e1941d1..3639b28 100644 (file)
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -34,6 +34,9 @@ typedef long asiduse;
 
 extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
 
+struct mm_struct;
+struct task_struct;
+
 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
 
 void smtc_flush_tlb_asid(unsigned long asid);
@@ -41,6 +44,7 @@ extern int mipsmt_build_cpu_map(int startslot);
 extern void mipsmt_prepare_cpus(void);
 extern void smtc_smp_finish(void);
 extern void smtc_boot_secondary(int cpu, struct task_struct *t);
+extern void smtc_cpus_done(void);
 
 /*
  * Sharing the TLB between multiple VPEs means that the
@@ -52,4 +56,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t);
 
 #define PARKED_INDEX   ((unsigned int)0x80000000)
 
+/*
+ * Define low-level interrupt mask for IPIs, if necessary.
+ * By default, use SW interrupt 1, which requires no external
+ * hardware support, but which works only for single-core
+ * MIPS MT systems.
+ */
+#ifndef MIPS_CPU_IPI_IRQ
+#define MIPS_CPU_IPI_IRQ 1
+#endif
+
 #endif /*  _ASM_SMTC_MT_H */