#include <asm/byteorder.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
+#include <asm-generic/iomap.h>
#include <asm/page.h>
#include <asm/pgtable-bits.h>
#include <asm/processor.h>
* hardware. An example use would be for flash memory that's used for
* execute in place.
*/
-# define __raw_ioswabb(a,x) (x)
-# define __raw_ioswabw(a,x) (x)
-# define __raw_ioswabl(a,x) (x)
-# define __raw_ioswabq(a,x) (x)
-# define ____raw_ioswabq(a,x) (x)
+# define __raw_ioswabb(a, x) (x)
+# define __raw_ioswabw(a, x) (x)
+# define __raw_ioswabl(a, x) (x)
+# define __raw_ioswabq(a, x) (x)
+# define ____raw_ioswabq(a, x) (x)
/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
* almost all conceivable cases a device driver should not be using
* this function
*/
-static inline unsigned long virt_to_phys(volatile void * address)
+static inline unsigned long virt_to_phys(volatile const void *address)
{
- return (unsigned long)address - PAGE_OFFSET;
+ return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET;
}
/*
*/
static inline void * phys_to_virt(unsigned long address)
{
- return (void *)(address + PAGE_OFFSET);
+ return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
}
/*
#define bus_to_virt phys_to_virt
/*
- * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
- * for the processor. This implies the assumption that there is only
- * one of these busses.
- */
-extern unsigned long isa_slot_offset;
-
-/*
* Change "struct page" to physical address.
*/
#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
-extern void __iounmap(volatile void __iomem *addr);
+extern void __iounmap(const volatile void __iomem *addr);
static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
unsigned long flags)
{
+ void __iomem *addr = plat_ioremap(offset, size, flags);
+
+ if (addr)
+ return addr;
+
#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
if (cpu_has_64bit_addresses) {
*/
if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
flags == _CACHE_UNCACHED)
- return (void __iomem *)CKSEG1ADDR(phys_addr);
+ return (void __iomem *)
+ (unsigned long)CKSEG1ADDR(phys_addr);
}
return __ioremap(offset, size, flags);
* memory-like regions on I/O busses.
*/
#define ioremap_cachable(offset, size) \
- __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
+ __ioremap_mode((offset), (size), _page_cachable_default)
/*
* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
#define ioremap_uncached_accelerated(offset, size) \
__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
-static inline void iounmap(volatile void __iomem *addr)
+static inline void iounmap(const volatile void __iomem *addr)
{
+ if (plat_iounmap(addr))
+ return;
+
#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
if (cpu_has_64bit_addresses ||
}
/*
- * Memory Mapped I/O
- */
-#define ioread8(addr) readb(addr)
-#define ioread16(addr) readw(addr)
-#define ioread32(addr) readl(addr)
-
-#define iowrite8(b,addr) writeb(b,addr)
-#define iowrite16(w,addr) writew(w,addr)
-#define iowrite32(l,addr) writel(l,addr)
-
-#define ioread8_rep(a,b,c) readsb(a,b,c)
-#define ioread16_rep(a,b,c) readsw(a,b,c)
-#define ioread32_rep(a,b,c) readsl(a,b,c)
-
-#define iowrite8_rep(a,b,c) writesb(a,b,c)
-#define iowrite16_rep(a,b,c) writesw(a,b,c)
-#define iowrite32_rep(a,b,c) writesl(a,b,c)
-
-/* Create a virtual mapping cookie for an IO port range */
-extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
-extern void ioport_unmap(void __iomem *);
-
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
-extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
-
-/*
- * ISA space is 'always mapped' on currently supported MIPS systems, no need
- * to explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
- */
-#define __ISA_IO_base ((char *)(isa_slot_offset))
-
-/*
- * We don't have csum_partial_copy_fromio() yet, so we cheat here and
- * just copy it. The net code will then do the checksum later.
- */
-#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
-
-/*
* The caches on some architectures aren't dma-coherent and have need to
* handle this in software. There are three types of operations that
* can be applied to dma buffers.
* caches. Dirty lines of the caches may be written back or simply
* be discarded. This operation is necessary before dma operations
* to the memory.
+ *
+ * This API used to be exported; it now is for arch code internal use only.
*/
#ifdef CONFIG_DMA_NONCOHERENT
extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
-#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size)
-#define dma_cache_wback(start, size) _dma_cache_wback(start,size)
-#define dma_cache_inv(start, size) _dma_cache_inv(start,size)
+#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
+#define dma_cache_wback(start, size) _dma_cache_wback(start, size)
+#define dma_cache_inv(start, size) _dma_cache_inv(start, size)
#else /* Sane hardware */
#define __CSR_32_ADJUST 0
#endif
-#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
+#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
/*
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff