maps4: rework TASK_SIZE macros

[safe/jmp/linux-2.6] / include / asm-mips / cpu-info.h

diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index d5cf519..0c5a358 100644 (file)
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -12,23 +12,18 @@
 #ifndef __ASM_CPU_INFO_H
 #define __ASM_CPU_INFO_H
 
-#include <linux/config.h>
 #include <asm/cache.h>
 
-#ifdef CONFIG_SGI_IP27
-#include <asm/sn/types.h>
-#endif
-
 /*
  * Descriptor for a cache
  */
 struct cache_desc {
-       unsigned short linesz;  /* Size of line in bytes */
-       unsigned short ways;    /* Number of ways */
-       unsigned short sets;    /* Number of lines per set */
        unsigned int waysize;   /* Bytes per way */
-       unsigned int waybit;    /* Bits to select in a cache set */
-       unsigned int flags;     /* Flags describing cache properties */
+       unsigned short sets;    /* Number of lines per set */
+       unsigned char ways;     /* Number of ways */
+       unsigned char linesz;   /* Size of line in bytes */
+       unsigned char waybit;   /* Bits to select in a cache set */
+       unsigned char flags;    /* Flags describing cache properties */
 };
 
 /*
@@ -39,24 +34,11 @@ struct cache_desc {
 #define MIPS_CACHE_ALIASES     0x00000004      /* Cache could have aliases */
 #define MIPS_CACHE_IC_F_DC     0x00000008      /* Ic can refill from D-cache */
 #define MIPS_IC_SNOOPS_REMOTE  0x00000010      /* Ic snoops remote stores */
+#define MIPS_CACHE_PINDEX      0x00000020      /* Physically indexed cache */
 
 struct cpuinfo_mips {
        unsigned long           udelay_val;
        unsigned long           asid_cache;
-#if defined(CONFIG_SGI_IP27)
-//     cpuid_t         p_cpuid;        /* PROM assigned cpuid */
-       cnodeid_t       p_nodeid;       /* my node ID in compact-id-space */
-       nasid_t         p_nasid;        /* my node ID in numa-as-id-space */
-       unsigned char   p_slice;        /* Physical position on node board */
-#endif
-#if 0
-       unsigned long           loops_per_sec;
-       unsigned long           ipi_count;
-       unsigned long           irq_attempt[NR_IRQS];
-       unsigned long           smp_local_irq_count;
-       unsigned long           prof_multiplier;
-       unsigned long           prof_counter;
-#endif
 
        /*
         * Capability and feature descriptor structure for MIPS CPU
@@ -72,13 +54,31 @@ struct cpuinfo_mips {
        struct cache_desc       dcache; /* Primary D or combined I/D cache */
        struct cache_desc       scache; /* Secondary cache */
        struct cache_desc       tcache; /* Tertiary/split secondary cache */
+       int                     srsets; /* Shadow register sets */
+       int                     core;   /* physical core number */
+#if defined(CONFIG_MIPS_MT_SMTC)
+       /*
+        * In the MIPS MT "SMTC" model, each TC is considered
+        * to be a "CPU" for the purposes of scheduling, but
+        * exception resources, ASID spaces, etc, are common
+        * to all TCs within the same VPE.
+        */
+       int                     vpe_id;  /* Virtual Processor number */
+#endif /* CONFIG_MIPS_MT */
+#ifdef CONFIG_MIPS_MT_SMTC
+       int                     tc_id;   /* Thread Context number */
+#endif
        void                    *data;  /* Additional data */
 } __attribute__((aligned(SMP_CACHE_BYTES)));
 
 extern struct cpuinfo_mips cpu_data[];
 #define current_cpu_data cpu_data[smp_processor_id()]
+#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
 
 extern void cpu_probe(void);
 extern void cpu_report(void);
 
+extern const char *__cpu_name[];
+#define cpu_name_string()      __cpu_name[smp_processor_id()]
+
 #endif /* __ASM_CPU_INFO_H */