*****************************************************************************/
/*
- * Copyright (C) 2000 - 2006, R. Byron Moore
+ * Copyright (C) 2000 - 2008, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#define ACPI_SIG_RSDT "RSDT" /* Root System Description Table */
#define ACPI_SIG_XSDT "XSDT" /* Extended System Description Table */
#define ACPI_SIG_SSDT "SSDT" /* Secondary System Description Table */
-#define ACPI_RSDP_NAME "RSDP"
+#define ACPI_RSDP_NAME "RSDP" /* Short name for RSDP, not signature */
/*
* All tables and structures must be byte-packed to match the ACPI
struct acpi_table_header header; /* Common ACPI table header */
u32 facs; /* 32-bit physical address of FACS */
u32 dsdt; /* 32-bit physical address of DSDT */
- u8 model; /* System Interrupt Model (ACPI 1.0) not used in ACPI 2.0+ */
+ u8 model; /* System Interrupt Model (ACPI 1.0) - not used in ACPI 2.0+ */
u8 preferred_profile; /* Conveys preferred power management profile to OSPM. */
u16 sci_interrupt; /* System vector of SCI interrupt */
- u32 smi_command; /* Port address of SMI command port */
+ u32 smi_command; /* 32-bit Port address of SMI command port */
u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
u8 S4bios_request; /* Value to write to SMI CMD to enter S4BIOS state */
u8 pstate_control; /* Processor performance state control */
- u32 pm1a_event_block; /* Port address of Power Mgt 1a Event Reg Blk */
- u32 pm1b_event_block; /* Port address of Power Mgt 1b Event Reg Blk */
- u32 pm1a_control_block; /* Port address of Power Mgt 1a Control Reg Blk */
- u32 pm1b_control_block; /* Port address of Power Mgt 1b Control Reg Blk */
- u32 pm2_control_block; /* Port address of Power Mgt 2 Control Reg Blk */
- u32 pm_timer_block; /* Port address of Power Mgt Timer Ctrl Reg Blk */
- u32 gpe0_block; /* Port addr of General Purpose acpi_event 0 Reg Blk */
- u32 gpe1_block; /* Port addr of General Purpose acpi_event 1 Reg Blk */
- u8 pm1_event_length; /* Byte Length of ports at pm1_x_evt_blk */
- u8 pm1_control_length; /* Byte Length of ports at pm1_x_cnt_blk */
- u8 pm2_control_length; /* Byte Length of ports at pm2_cnt_blk */
- u8 pm_timer_length; /* Byte Length of ports at pm_tmr_blk */
- u8 gpe0_block_length; /* Byte Length of ports at gpe0_blk */
- u8 gpe1_block_length; /* Byte Length of ports at gpe1_blk */
- u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
- u8 cst_control; /* Support for the _CST object and C States change notification. */
+ u32 pm1a_event_block; /* 32-bit Port address of Power Mgt 1a Event Reg Blk */
+ u32 pm1b_event_block; /* 32-bit Port address of Power Mgt 1b Event Reg Blk */
+ u32 pm1a_control_block; /* 32-bit Port address of Power Mgt 1a Control Reg Blk */
+ u32 pm1b_control_block; /* 32-bit Port address of Power Mgt 1b Control Reg Blk */
+ u32 pm2_control_block; /* 32-bit Port address of Power Mgt 2 Control Reg Blk */
+ u32 pm_timer_block; /* 32-bit Port address of Power Mgt Timer Ctrl Reg Blk */
+ u32 gpe0_block; /* 32-bit Port address of General Purpose Event 0 Reg Blk */
+ u32 gpe1_block; /* 32-bit Port address of General Purpose Event 1 Reg Blk */
+ u8 pm1_event_length; /* Byte Length of ports at pm1x_event_block */
+ u8 pm1_control_length; /* Byte Length of ports at pm1x_control_block */
+ u8 pm2_control_length; /* Byte Length of ports at pm2_control_block */
+ u8 pm_timer_length; /* Byte Length of ports at pm_timer_block */
+ u8 gpe0_block_length; /* Byte Length of ports at gpe0_block */
+ u8 gpe1_block_length; /* Byte Length of ports at gpe1_block */
+ u8 gpe1_base; /* Offset in GPE number space where GPE1 events start */
+ u8 cst_control; /* Support for the _CST object and C States change notification */
u16 C2latency; /* Worst case HW latency to enter/exit C2 state */
u16 C3latency; /* Worst case HW latency to enter/exit C3 state */
u16 flush_size; /* Processor's memory cache line width, in bytes */
u16 flush_stride; /* Number of flush strides that need to be read */
- u8 duty_offset; /* Processor's duty cycle index in processor's P_CNT reg */
- u8 duty_width; /* Processor's duty cycle value bit width in P_CNT register. */
+ u8 duty_offset; /* Processor duty cycle index in processor's P_CNT reg */
+ u8 duty_width; /* Processor duty cycle value bit width in P_CNT register */
u8 day_alarm; /* Index to day-of-month alarm in RTC CMOS RAM */
u8 month_alarm; /* Index to month-of-year alarm in RTC CMOS RAM */
u8 century; /* Index to century in RTC CMOS RAM */
- u16 boot_flags; /* IA-PC Boot Architecture Flags. See Table 5-10 for description */
+ u16 boot_flags; /* IA-PC Boot Architecture Flags (see below for individual flags) */
u8 reserved; /* Reserved, must be zero */
- u32 flags; /* Miscellaneous flag bits */
- struct acpi_generic_address reset_register; /* Reset register address in GAS format */
+ u32 flags; /* Miscellaneous flag bits (see below for individual flags) */
+ struct acpi_generic_address reset_register; /* 64-bit address of the Reset register */
u8 reset_value; /* Value to write to the reset_register port to reset the system */
- u8 reserved4[3]; /* These three bytes must be zero */
+ u8 reserved4[3]; /* Reserved, must be zero */
u64 Xfacs; /* 64-bit physical address of FACS */
u64 Xdsdt; /* 64-bit physical address of DSDT */
- struct acpi_generic_address xpm1a_event_block; /* Extended Power Mgt 1a acpi_event Reg Blk address */
- struct acpi_generic_address xpm1b_event_block; /* Extended Power Mgt 1b acpi_event Reg Blk address */
- struct acpi_generic_address xpm1a_control_block; /* Extended Power Mgt 1a Control Reg Blk address */
- struct acpi_generic_address xpm1b_control_block; /* Extended Power Mgt 1b Control Reg Blk address */
- struct acpi_generic_address xpm2_control_block; /* Extended Power Mgt 2 Control Reg Blk address */
- struct acpi_generic_address xpm_timer_block; /* Extended Power Mgt Timer Ctrl Reg Blk address */
- struct acpi_generic_address xgpe0_block; /* Extended General Purpose acpi_event 0 Reg Blk address */
- struct acpi_generic_address xgpe1_block; /* Extended General Purpose acpi_event 1 Reg Blk address */
+ struct acpi_generic_address xpm1a_event_block; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
+ struct acpi_generic_address xpm1b_event_block; /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
+ struct acpi_generic_address xpm1a_control_block; /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
+ struct acpi_generic_address xpm1b_control_block; /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
+ struct acpi_generic_address xpm2_control_block; /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
+ struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
+ struct acpi_generic_address xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */
+ struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */
};
+/* FADT Boot Architecture Flags (boot_flags) */
+
+#define ACPI_FADT_LEGACY_DEVICES (1) /* 00: [V2] System has LPC or ISA bus devices */
+#define ACPI_FADT_8042 (1<<1) /* 01: [V3] System has an 8042 controller on port 60/64 */
+#define ACPI_FADT_NO_VGA (1<<2) /* 02: [V4] It is not safe to probe for VGA hardware */
+#define ACPI_FADT_NO_MSI (1<<3) /* 03: [V4] Message Signaled Interrupts (MSI) must not be enabled */
+#define ACPI_FADT_NO_ASPM (1<<4) /* 04: [V4] PCIe ASPM control must not be enabled */
+
+#define FADT2_REVISION_ID 3
+
/* FADT flags */
-#define ACPI_FADT_WBINVD (1) /* 00: The wbinvd instruction works properly */
-#define ACPI_FADT_WBINVD_FLUSH (1<<1) /* 01: The wbinvd flushes but does not invalidate */
-#define ACPI_FADT_C1_SUPPORTED (1<<2) /* 02: All processors support C1 state */
-#define ACPI_FADT_C2_MP_SUPPORTED (1<<3) /* 03: C2 state works on MP system */
-#define ACPI_FADT_POWER_BUTTON (1<<4) /* 04: Power button is handled as a generic feature */
-#define ACPI_FADT_SLEEP_BUTTON (1<<5) /* 05: Sleep button is handled as a generic feature, or not present */
-#define ACPI_FADT_FIXED_RTC (1<<6) /* 06: RTC wakeup stat not in fixed register space */
-#define ACPI_FADT_S4_RTC_WAKE (1<<7) /* 07: RTC wakeup stat not possible from S4 */
-#define ACPI_FADT_32BIT_TIMER (1<<8) /* 08: tmr_val is 32 bits 0=24-bits */
-#define ACPI_FADT_DOCKING_SUPPORTED (1<<9) /* 09: Docking supported */
-#define ACPI_FADT_RESET_REGISTER (1<<10) /* 10: System reset via the FADT RESET_REG supported */
-#define ACPI_FADT_SEALED_CASE (1<<11) /* 11: No internal expansion capabilities and case is sealed */
-#define ACPI_FADT_HEADLESS (1<<12) /* 12: No local video capabilities or local input devices */
-#define ACPI_FADT_SLEEP_TYPE (1<<13) /* 13: Must execute native instruction after writing SLP_TYPx register */
-#define ACPI_FADT_PCI_EXPRESS_WAKE (1<<14) /* 14: System supports PCIEXP_WAKE (STS/EN) bits (ACPI 3.0) */
-#define ACPI_FADT_PLATFORM_CLOCK (1<<15) /* 15: OSPM should use platform-provided timer (ACPI 3.0) */
-#define ACPI_FADT_S4_RTC_VALID (1<<16) /* 16: Contents of RTC_STS valid after S4 wake (ACPI 3.0) */
-#define ACPI_FADT_REMOTE_POWER_ON (1<<17) /* 17: System is compatible with remote power on (ACPI 3.0) */
-#define ACPI_FADT_APIC_CLUSTER (1<<18) /* 18: All local APICs must use cluster model (ACPI 3.0) */
-#define ACPI_FADT_APIC_PHYSICAL (1<<19) /* 19: All local x_aPICs must use physical dest mode (ACPI 3.0) */
+#define ACPI_FADT_WBINVD (1) /* 00: [V1] The wbinvd instruction works properly */
+#define ACPI_FADT_WBINVD_FLUSH (1<<1) /* 01: [V1] wbinvd flushes but does not invalidate caches */
+#define ACPI_FADT_C1_SUPPORTED (1<<2) /* 02: [V1] All processors support C1 state */
+#define ACPI_FADT_C2_MP_SUPPORTED (1<<3) /* 03: [V1] C2 state works on MP system */
+#define ACPI_FADT_POWER_BUTTON (1<<4) /* 04: [V1] Power button is handled as a control method device */
+#define ACPI_FADT_SLEEP_BUTTON (1<<5) /* 05: [V1] Sleep button is handled as a control method device */
+#define ACPI_FADT_FIXED_RTC (1<<6) /* 06: [V1] RTC wakeup status not in fixed register space */
+#define ACPI_FADT_S4_RTC_WAKE (1<<7) /* 07: [V1] RTC alarm can wake system from S4 */
+#define ACPI_FADT_32BIT_TIMER (1<<8) /* 08: [V1] ACPI timer width is 32-bit (0=24-bit) */
+#define ACPI_FADT_DOCKING_SUPPORTED (1<<9) /* 09: [V1] Docking supported */
+#define ACPI_FADT_RESET_REGISTER (1<<10) /* 10: [V2] System reset via the FADT RESET_REG supported */
+#define ACPI_FADT_SEALED_CASE (1<<11) /* 11: [V3] No internal expansion capabilities and case is sealed */
+#define ACPI_FADT_HEADLESS (1<<12) /* 12: [V3] No local video capabilities or local input devices */
+#define ACPI_FADT_SLEEP_TYPE (1<<13) /* 13: [V3] Must execute native instruction after writing SLP_TYPx register */
+#define ACPI_FADT_PCI_EXPRESS_WAKE (1<<14) /* 14: [V4] System supports PCIEXP_WAKE (STS/EN) bits (ACPI 3.0) */
+#define ACPI_FADT_PLATFORM_CLOCK (1<<15) /* 15: [V4] OSPM should use platform-provided timer (ACPI 3.0) */
+#define ACPI_FADT_S4_RTC_VALID (1<<16) /* 16: [V4] Contents of RTC_STS valid after S4 wake (ACPI 3.0) */
+#define ACPI_FADT_REMOTE_POWER_ON (1<<17) /* 17: [V4] System is compatible with remote power on (ACPI 3.0) */
+#define ACPI_FADT_APIC_CLUSTER (1<<18) /* 18: [V4] All local APICs must use cluster model (ACPI 3.0) */
+#define ACPI_FADT_APIC_PHYSICAL (1<<19) /* 19: [V4] All local x_aPICs must use physical dest mode (ACPI 3.0) */
+
+/* FADT Prefered Power Management Profiles */
-/*
- * FADT Prefered Power Management Profiles
- */
enum acpi_prefered_pm_profiles {
PM_UNSPECIFIED = 0,
PM_DESKTOP = 1,
PM_APPLIANCE_PC = 6
};
-/* FADT Boot Arch Flags */
-
-#define BAF_LEGACY_DEVICES 0x0001
-#define BAF_8042_KEYBOARD_CONTROLLER 0x0002
-
-#define FADT2_REVISION_ID 3
-#define FADT2_MINUS_REVISION_ID 2
-
/* Reset to default packing */
#pragma pack()
#define ACPI_FADT_OFFSET(f) (u8) ACPI_OFFSET (struct acpi_table_fadt, f)
+union acpi_name_union {
+ u32 integer;
+ char ascii[4];
+};
+
+/*
+ * Internal ACPI Table Descriptor. One per ACPI table
+ */
+struct acpi_table_desc {
+ acpi_physical_address address;
+ struct acpi_table_header *pointer;
+ u32 length; /* Length fixed at 32 bits */
+ union acpi_name_union signature;
+ acpi_owner_id owner_id;
+ u8 flags;
+};
+
+/* Flags for above */
+
+#define ACPI_TABLE_ORIGIN_UNKNOWN (0)
+#define ACPI_TABLE_ORIGIN_MAPPED (1)
+#define ACPI_TABLE_ORIGIN_ALLOCATED (2)
+#define ACPI_TABLE_ORIGIN_OVERRIDE (4)
+#define ACPI_TABLE_ORIGIN_MASK (7)
+#define ACPI_TABLE_IS_LOADED (8)
+
/*
* Get the remaining ACPI tables
*/
+
#include <acpi/actbl1.h>
#endif /* __ACTBL_H__ */
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff