/* board types */
enum cirrus_board {
BT_NONE = 0,
- BT_SD64,
- BT_PICCOLO,
- BT_PICASSO,
- BT_SPECTRUM,
+ BT_SD64, /* GD5434 */
+ BT_PICCOLO, /* GD5426 */
+ BT_PICASSO, /* GD5426 or GD5428 */
+ BT_SPECTRUM, /* GD5426 or GD5428 */
BT_PICASSO4, /* GD5446 */
BT_ALPINE, /* GD543x/4x */
BT_GD5480,
.sr07 = 0xF0,
.sr07_1bpp = 0xF0,
.sr07_8bpp = 0xF1,
- .sr1f = 0x20
+ .sr1f = 0x1E
},
[BT_PICCOLO] = {
.name = "CL Piccolo",
.init_sr07 = true,
.init_sr1f = false,
.scrn_start_bit19 = true,
- .sr07 = 0x20,
- .sr07_1bpp = 0x20,
- .sr07_8bpp = 0x21,
+ .sr07 = 0xA0,
+ .sr07_1bpp = 0xA0,
+ .sr07_1bpp_mux = 0xA6,
+ .sr07_8bpp = 0xA1,
+ .sr07_8bpp_mux = 0xA7,
.sr1f = 0
},
[BT_ALPINE] = {
.init_sr1f = true,
.scrn_start_bit19 = true,
.sr07 = 0xA0,
- .sr07_1bpp = 0xA1,
- .sr07_1bpp_mux = 0xA7,
+ .sr07_1bpp = 0xA0,
+ .sr07_1bpp_mux = 0xA6,
.sr07_8bpp = 0xA1,
.sr07_8bpp_mux = 0xA7,
.sr1f = 0x1C
static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
u_short x, u_short y,
u_short width, u_short height,
- u32 color, u_short line_length);
+ u32 fg_color, u32 bg_color,
+ u_short line_length, u_char blitmode);
static void bestclock(long freq, int *nom, int *den, int *div);
/* If the frequency is greater than we can support, we might be able
* to use multiplexing for the video mode */
if (freq > maxclock) {
+ dev_err(info->device,
+ "Frequency greater than maxclock (%ld kHz)\n",
+ maxclock);
+ return -EINVAL;
+ }
+ /*
+ * Additional constraint: 8bpp uses DAC clock doubling to allow maximum
+ * pixel clock
+ */
+ if (var->bits_per_pixel == 8) {
switch (cinfo->btype) {
case BT_ALPINE:
+ case BT_SD64:
+ case BT_PICASSO4:
+ if (freq > 85500)
+ cinfo->multiplexing = 1;
+ break;
case BT_GD5480:
- cinfo->multiplexing = 1;
+ if (freq > 135100)
+ cinfo->multiplexing = 1;
break;
default:
- dev_err(info->device,
- "Frequency greater than maxclock (%ld kHz)\n",
- maxclock);
- return -EINVAL;
+ break;
}
}
#if 0
* the VCLK is double the pixel clock. */
switch (var->bits_per_pixel) {
case 16:
- case 32:
+ case 24:
if (var->xres <= 800)
/* Xbh has this type of clock for 32-bit */
freq /= 2;
int yres;
/* memory size in pixels */
unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
+ struct cirrusfb_info *cinfo = info->par;
switch (var->bits_per_pixel) {
case 1:
var->blue.length = 5;
break;
- case 32:
+ case 24:
if (isPReP) {
- var->red.offset = 8;
- var->green.offset = 16;
- var->blue.offset = 24;
+ var->red.offset = 0;
+ var->green.offset = 8;
+ var->blue.offset = 16;
} else {
var->red.offset = 16;
var->green.offset = 8;
if (cirrusfb_check_pixclock(var, info))
return -EINVAL;
+ if (!is_laguna(cinfo))
+ var->accel_flags = FB_ACCELF_TEXT;
+
return 0;
}
break;
case 16:
- case 32:
+ case 24:
info->fix.line_length = var->xres_virtual *
var->bits_per_pixel >> 3;
info->fix.visual = FB_VISUAL_TRUECOLOR;
vga_wcrt(regbase, CL_CRT1A, tmp);
freq = PICOS2KHZ(var->pixclock);
+ if (cinfo->btype == BT_ALPINE && var->bits_per_pixel == 24)
+ freq *= 3;
+ if (cinfo->multiplexing)
+ freq /= 2;
+
bestclock(freq, &nom, &den, &div);
dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n",
/* formula: VClk = (OSC * N) / (D * (1+P)) */
/* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
- if (cinfo->btype == BT_ALPINE) {
+ if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
+ cinfo->btype == BT_SD64) {
/* if freq is close to mclk or mclk/2 select mclk
* as clock source
*/
/* Extended Sequencer Mode */
switch (cinfo->btype) {
- case BT_SD64:
- /* setting the SEQRF on SD64 is not necessary
- * (only during init)
- */
- /* MCLK select */
- vga_wseq(regbase, CL_SEQR1F, 0x1a);
- break;
case BT_PICCOLO:
case BT_SPECTRUM:
- /* ### ueberall 0x22? */
- /* ##vorher 1c MCLK select */
- vga_wseq(regbase, CL_SEQR1F, 0x22);
/* evtl d0 bei 1 bit? avoid FIFO underruns..? */
vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO:
- /* ##vorher 22 MCLK select */
- vga_wseq(regbase, CL_SEQR1F, 0x22);
/* ## vorher d0 avoid FIFO underruns..? */
vga_wseq(regbase, CL_SEQRF, 0xd0);
break;
+ case BT_SD64:
case BT_PICASSO4:
case BT_ALPINE:
case BT_GD5480:
}
switch (cinfo->btype) {
- case BT_SD64:
- /* MCLK select */
- vga_wseq(regbase, CL_SEQR1F, 0x1d);
- break;
-
case BT_PICCOLO:
case BT_PICASSO:
case BT_SPECTRUM:
- /* ### vorher 1c MCLK select */
- vga_wseq(regbase, CL_SEQR1F, 0x22);
/* Fast Page-Mode writes */
vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
/* ### INCOMPLETE!! */
vga_wseq(regbase, CL_SEQRF, 0xb8);
#endif
-/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
- break;
-
case BT_ALPINE:
/* We already set SRF and SR1F */
break;
+ case BT_SD64:
case BT_GD5480:
case BT_LAGUNA:
case BT_LAGUNAB:
else if (var->bits_per_pixel == 16) {
dev_dbg(info->device, "preparing for 16 bit deep display\n");
switch (cinfo->btype) {
- case BT_SD64:
- /* Extended Sequencer Mode: 256c col. mode */
- vga_wseq(regbase, CL_SEQR7, 0xf7);
- /* MCLK select */
- vga_wseq(regbase, CL_SEQR1F, 0x1e);
- break;
-
case BT_PICCOLO:
case BT_SPECTRUM:
vga_wseq(regbase, CL_SEQR7, 0x87);
/* Fast Page-Mode writes */
vga_wseq(regbase, CL_SEQRF, 0xb0);
- /* MCLK select */
- vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_PICASSO:
vga_wseq(regbase, CL_SEQR7, 0x27);
/* Fast Page-Mode writes */
vga_wseq(regbase, CL_SEQRF, 0xb0);
- /* MCLK select */
- vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
+ case BT_SD64:
case BT_PICASSO4:
- vga_wseq(regbase, CL_SEQR7, 0x27);
-/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
- break;
-
case BT_ALPINE:
+ /* Extended Sequencer Mode: 256c col. mode */
vga_wseq(regbase, CL_SEQR7, 0xa7);
break;
/******************************************************
*
- * 32 bpp
+ * 24 bpp
*
*/
- else if (var->bits_per_pixel == 32) {
- dev_dbg(info->device, "preparing for 32 bit deep display\n");
+ else if (var->bits_per_pixel == 24) {
+ dev_dbg(info->device, "preparing for 24 bit deep display\n");
switch (cinfo->btype) {
- case BT_SD64:
- /* Extended Sequencer Mode: 256c col. mode */
- vga_wseq(regbase, CL_SEQR7, 0xf9);
- /* MCLK select */
- vga_wseq(regbase, CL_SEQR1F, 0x1e);
- break;
-
case BT_PICCOLO:
case BT_SPECTRUM:
vga_wseq(regbase, CL_SEQR7, 0x85);
/* Fast Page-Mode writes */
vga_wseq(regbase, CL_SEQRF, 0xb0);
- /* MCLK select */
- vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_PICASSO:
vga_wseq(regbase, CL_SEQR7, 0x25);
/* Fast Page-Mode writes */
vga_wseq(regbase, CL_SEQRF, 0xb0);
- /* MCLK select */
- vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
+ case BT_SD64:
case BT_PICASSO4:
- vga_wseq(regbase, CL_SEQR7, 0x25);
-/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
- break;
-
case BT_ALPINE:
- vga_wseq(regbase, CL_SEQR7, 0xa9);
+ /* Extended Sequencer Mode: 256c col. mode */
+ vga_wseq(regbase, CL_SEQR7, 0xa5);
break;
case BT_GD5480:
- vga_wseq(regbase, CL_SEQR7, 0x19);
+ vga_wseq(regbase, CL_SEQR7, 0x15);
/* We already set SRF and SR1F */
break;
case BT_LAGUNAB:
vga_wseq(regbase, CL_SEQR7,
vga_rseq(regbase, CL_SEQR7) & ~0x01);
- control |= 0x6000;
- format |= 0x3400;
+ control |= 0x4000;
+ format |= 0x2400;
threshold |= 0x20;
break;
unsigned char tmp, xpix;
struct cirrusfb_info *cinfo = info->par;
- dev_dbg(info->device,
- "virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
-
/* no range checks for xoffset and yoffset, */
/* as fb_pan_display has already done this */
if (var->vmode & FB_VMODE_YWRAP)
if (info->var.bits_per_pixel == 1)
vga_wattr(cinfo->regbase, CL_AR33, xpix);
- if (!is_laguna(cinfo))
- cirrusfb_WaitBLT(cinfo->regbase);
-
return 0;
}
/* disable flickerfixer */
vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
mdelay(100);
- /* from Klaus' NetBSD driver: */
- vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
- /* put blitter into 542x compat */
- vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
/* mode */
vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
- break;
-
- case BT_GD5480:
+ case BT_GD5480: /* fall through */
/* from Klaus' NetBSD driver: */
vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
+ case BT_ALPINE: /* fall through */
+ /* put blitter into 542x compat */
+ vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
break;
case BT_LAGUNA:
case BT_LAGUNAB:
- case BT_ALPINE:
/* Nothing to do to reset the board. */
break;
vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
}
- /* MCLK select etc. */
- if (bi->init_sr1f)
- vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
-
/* Screen A preset row scan: none */
vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
/* Text cursor start: disable text cursor */
info->var.bits_per_pixel,
(region->dx * m) / 8, region->dy,
(region->width * m) / 8, region->height,
- color,
- info->fix.line_length);
+ color, color,
+ info->fix.line_length, 0x40);
}
static void cirrusfb_copyarea(struct fb_info *info,
const struct fb_image *image)
{
struct cirrusfb_info *cinfo = info->par;
+ unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4;
- if (!is_laguna(cinfo))
- cirrusfb_WaitBLT(cinfo->regbase);
- cfb_imageblit(info, image);
+ if (info->state != FBINFO_STATE_RUNNING)
+ return;
+ /* Alpine acceleration does not work at 24bpp ?!? */
+ if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1 ||
+ (cinfo->btype == BT_ALPINE && op == 0xc))
+ cfb_imageblit(info, image);
+ else {
+ unsigned size = ((image->width + 7) >> 3) * image->height;
+ int m = info->var.bits_per_pixel;
+ u32 fg, bg;
+
+ if (info->var.bits_per_pixel == 8) {
+ fg = image->fg_color;
+ bg = image->bg_color;
+ } else {
+ fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
+ bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
+ }
+ if (info->var.bits_per_pixel == 24) {
+ /* clear background first */
+ cirrusfb_RectFill(cinfo->regbase,
+ info->var.bits_per_pixel,
+ (image->dx * m) / 8, image->dy,
+ (image->width * m) / 8,
+ image->height,
+ bg, bg,
+ info->fix.line_length, 0x40);
+ }
+ cirrusfb_RectFill(cinfo->regbase,
+ info->var.bits_per_pixel,
+ (image->dx * m) / 8, image->dy,
+ (image->width * m) / 8, image->height,
+ fg, bg,
+ info->fix.line_length, op);
+ memcpy(info->screen_base, image->data, size);
+ }
}
#ifdef CONFIG_PPC_PREP
| FBINFO_HWACCEL_XPAN
| FBINFO_HWACCEL_YPAN
| FBINFO_HWACCEL_FILLRECT
+ | FBINFO_HWACCEL_IMAGEBLIT
| FBINFO_HWACCEL_COPYAREA;
- if (noaccel || is_laguna(cinfo))
+ if (noaccel || is_laguna(cinfo)) {
info->flags |= FBINFO_HWACCEL_DISABLED;
+ info->fix.accel = FB_ACCEL_NONE;
+ } else
+ info->fix.accel = FB_ACCEL_CIRRUS_ALPINE;
+
info->fbops = &cirrusfb_ops;
+
if (cinfo->btype == BT_GD5480) {
if (var->bits_per_pixel == 16)
info->screen_base += 1 * MB_;
/* FIXME: map region at 0xB8000 if available, fill in here */
info->fix.mmio_len = 0;
- info->fix.accel = FB_ACCEL_NONE;
fb_alloc_cmap(&info->cmap, 256, 0);
err_dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
- cinfo->unmap(info);
- framebuffer_release(info);
return err;
}
zorro_set_drvdata(z, info);
+ /* MCLK select etc. */
+ if (cirrusfb_board_info[btype].init_sr1f)
+ vga_wseq(cinfo->regbase, CL_SEQR1F,
+ cirrusfb_board_info[btype].sr1f);
+
ret = cirrusfb_register(info);
- if (ret) {
- if (btype == BT_PICASSO4) {
- iounmap(info->screen_base);
- iounmap(cinfo->regbase - 0x600000);
- } else if (board_addr > 0x01000000)
- iounmap(info->screen_base);
- }
- return ret;
+ if (!ret)
+ return 0;
+
+ if (btype == BT_PICASSO4 || board_addr > 0x01000000)
+ iounmap(info->screen_base);
err_unmap_regbase:
- /* Parental advisory: explicit hack */
- iounmap(cinfo->regbase - 0x600000);
+ if (btype == BT_PICASSO4)
+ iounmap(cinfo->regbase - 0x600000);
err_release_region:
release_region(board_addr, board_size);
err_release_fb:
vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
/* and finally: GO! */
- vga_wgfx(regbase, CL_GR31, 0x82); /* BLT Start/status */
+ vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
}
/*******************************************************************
static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
u_short x, u_short y, u_short width, u_short height,
- u32 color, u_short line_length)
+ u32 fg_color, u32 bg_color, u_short line_length,
+ u_char blitmode)
{
u_long ndest = (y * line_length) + x;
u_char op;
/* This is a ColorExpand Blt, using the */
/* same color for foreground and background */
- vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
- vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /* background color */
+ vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);
+ vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);
- op = 0xc0;
+ op = 0x80;
if (bits_per_pixel >= 16) {
- vga_wgfx(regbase, CL_GR10, color >> 8); /* foreground color */
- vga_wgfx(regbase, CL_GR11, color >> 8); /* background color */
- op = 0xd0;
+ vga_wgfx(regbase, CL_GR10, bg_color >> 8);
+ vga_wgfx(regbase, CL_GR11, fg_color >> 8);
+ op = 0x90;
+ }
+ if (bits_per_pixel >= 24) {
+ vga_wgfx(regbase, CL_GR12, bg_color >> 16);
+ vga_wgfx(regbase, CL_GR13, fg_color >> 16);
+ op = 0xa0;
}
if (bits_per_pixel == 32) {
- vga_wgfx(regbase, CL_GR12, color >> 16);/* foreground color */
- vga_wgfx(regbase, CL_GR13, color >> 16);/* background color */
- vga_wgfx(regbase, CL_GR14, color >> 24);/* foreground color */
- vga_wgfx(regbase, CL_GR15, color >> 24);/* background color */
- op = 0xf0;
+ vga_wgfx(regbase, CL_GR14, bg_color >> 24);
+ vga_wgfx(regbase, CL_GR15, fg_color >> 24);
+ op = 0xb0;
}
cirrusfb_set_blitter(regbase, width - 1, height - 1,
- 0, ndest, op, line_length);
+ 0, ndest, op | blitmode, line_length);
}
/**************************************************************************
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff